2012 IEEE 30th VLSI Test Symposium (VTS)

Write-through Method for Embedded Memory with

Compression Scan-based Testing
Geewhun Seok

Hong Kim

Baker Mohammad

The University of Texas at Austin

Qualcomm
Austin, U.S.A
[email protected]

Qualcomm
Austin, U.S.A
[email protected]

Khalifa University of Science

Technology and Research
Abu Dhabi, UAE
[email protected]

AbstractDemands for low defects per million (DPM) rates

are increasing as process technology scaling is able to increase
transistor density and add more functionality to the integrated
circuits. For stuck at fault and delay testing, Scan-based testing
in conjunction with ATPG is the preferred approach to reduces
DPM compared to functional testing. However embedded memories have been a challenge to ATPG gate level simulation due to
limitation of gate level generation method and the additional logic
needed to prevent unknowns (Xs) to be propagated from memory
during ATPG testing, this X-propagation becomes more of an
issue when the design has a test compressor. This paper examines
the challenges of ATPG memory write through method on the
design with chip test compression logic and proposes new design
strategy and ATPG pattern generation method. The proposed
design will make the memory look like a one dimensional set
of registers and ATPG pattern generation method will support
write through mode without Xs propagation.

I. I NTRODUCTION
One of the most common design-for-test strategies for SOCs
is scan design which structures a general design to behave
as combinational logic gates. These gates models have been
understood by state-of the art ATPG tool and successfully
detected faults with patterns which are generated from ATPG.
However most processors and SOCs have a mixture of large
and small memories which are based on SRAMs, CAMs,
ROMs, register-files, FIFOS, and many other regular structures
Even though the memory structure itself may be covered using
other testing techniques like Built In Self Test (BIST), there
is a lot of logic between the regular structure and the rest of
the design (shadow logic) as shown in Figure 1.
Several ATPG vendors have provided the capability to
model memory structures with a behavioral model [1]. In
[2], Sitram and Sanjay presented impact and cost of handling
memory models for ATPG in which they showed improvement
of the stuck-at and transition fault test coverage with memory
modeling methodology.
Another major trend for SOC is to use on chip test compression [3]. A design with a compression methodology can
reduce test data volume and testing time. However one of the
major problems with an on-chip test compressor is that, if
there is feedback logic like memory in the scan chain whose
contents cannot be uniquely determined to be known values
during simulation (also called Xs or unknown logic values),
then the entire signature will get corrupted and will be of
c
978-1-4673-1074-1/12/$31.00 2012
IEEE

Scanable
FF

Scanable
FF

Scanable
FF

Shadow
Logic

Memory

Shadow
Logic

Scanable
FF

Scanable
FF

Fig. 1.

Shadow logic around memory

no use. This will result in masking many test patterns that

will affect coverage. Sources of Xs include uninitialized and
uncontrollable memory blocks, bus contention, floating buses,
multiple clock domains, and inaccurate simulation models [4].
To remove unknown logic values, a significant amount of
engineering effort is required through each design stage. There
is a possibility that an ATPG memory model generates Xs,
because it is difficult for the ATPG tool to comprehend all
the memory operation and control signals for the memory.
Moreover, if an SOC has in addition to compiler memory a
lot of custom memories, making the commercial ATPG understand these memories may be difficult. This chapter proposes a
new design and testing methodology to apply a write through
method which will improve test coverage and reduce scan
overhead for hard macros. The effect of using memory model
with on-chip test compression will be described. It provides
a solution to prevent Xs which are generated from memory
when ATPG does not have controllability of read and write
operation of the memory. This chapter is organized as follows:
Section II will introduce the method of modeling memory for
ATPG in the custom design flow and how the memory model
fits into the flow, Section III addresses current memory scan
testing methods, Section IV details the register based testing
strategy and Section V proposes virtual Xs prevention logic
for ATPG. Section VI report the experimental results from
an industry embedded processor with mixed memory and this

158

Scanable
FF

(2)

(1)

Macro level Design Start

Top level Design Start

Custom Macro Design

RTL Development

Syntesis

Schematic Design

Place & Route

Generate Gate Level Netlist

ATPG Macro level

simulation

ATPG memory model

Gate Level Netlist

Gate level model Validation

Memory model Validation

White Box Macro Model

ATPG Top level

initial simulation

Final macro gate level

model

ATPG Top level

Final simulation

Fig. 2.
High Level Overview of Design Flow with Custom Embedded
Memory Showing The ATPG Flow and The Memory Model

chapters conclude with Section VII.

II. M EMORY M ODELING FOR ATPG
A memory model is for describing generic memory to represent array behavior. A typical gate netlist can be generated
from a Synthesis flow (Figure 2-(1)) and most of the logic
in a custom design also can be translated into gate level
netlist(Figure 2-(2)). However structures like memory which
has bi-stable logic cannot be automatically translated and even
if generated, a memory netlist can not be understood by ATPG
tools [5]. From a test perspective, memory has been often
modeled as a black-box and the logic surrounding the memory
has not been covered due to propagation of X values from the
output of black boxed memory. Figure 1 shows the uncovered
logic by ATPG if a memory model was not used. Fault
coverage between the scan-frontier and the memory boundary
will be lost due to unknown status.
A method called write through memory, which uses a
memory model, can increase the test coverage. In other words,
the surrounding shadow logic can be tested by the write
through method. The write through method is also important
to do delay testing because the many paths through memory
do essential roles of justification on many delay paths. It
is good to know that the memory model is not for testing
memory itself. Instead, embedded memory can be tested by
BIST, functional test or memory scan.

often improper for a critical path. This method has issues with
at-speed testing coverage because the memory is modeled as
a black-box.
The second method for memory during ATPG is to use a
write through mode, it uses a memory model and requires
the control of read and write enable signals and the memory
clock. This method needs sequential ATPG to test the shadow
logic. Sequential ATPG patterns have more than two pulses
during capturing time. This allows input values to propagate
to the output of the memory like one cycle for writing and
another cycle for reading into memory. This technique is
attractive because it can provide at-speed testing coverage. It
can cover up macro to macro paths which are often timing
critical paths. However, Currently the write through method
has the following drawbacks:
1) Xs propagation; the ATPG memory model can generate
Xs if the memory accesses a location that was not written
to. It is difficult for the ATPG tool to understand all the
combinations of read, write, data and address. This may
result in reading memory contents that have not been written
to already through previous patterns. Due to the limitation
in tool capability for write through mode, the number of
patterns is increased to cover up to desired test coverage and
if the design has a scan compressor, the generated Xs give
more impact to pattern count. Table I shows how Xs from
memories can impact to static ATPG test coverage. The test
coverage came from the same design with different setup
mode, uncompress and compress mode. If there is no Xs
propagation, test coverage of compress mode is equal to or
greater than uncompress mode, but due to Xs from memories,
it suffered with Xs in scan chains. Because the outputs of the
scan chains must correspond exactly to the expected simulated
states, any dont-care bits will corrupt other scan chains.
Dont-care states from memories need to be eliminated if
XOR compression is used. By doing Xs source analysis the
percentage of Xs due to memory is found to be about 34
percent of the total Xs. Unfortunately, even some Xs can be
eliminated from the design, uncontrolled memories affect the
contents of scan chains during write-through mode due to
improper control of write and read enable signal. To avoid
further testability transgressions during automated test pattern
generation, the ATPG tool requires paying special attention to
the support needed for memories. However, it is difficult for
an ATPG algorithm to understand each custom macro design
and have proper control of the read and write enable signal
control. In order for the ATPG algorithm to create patterns
which pass data through memory, one of the requirements is

III. C URRENT M EMORY S CAN T ESTING M ETHODS

In this section, two design approaches to test the shadow
logic through scan will be addressed. The first is the bypass
method. It is most common and simple method. It uses wires to
bypass memory from the data input to data output and locates
the MUXs to output of the memory. It has a MUX delay at
output of the memory. Due to this MUX delay this design is
159

TABLE I

T HE E FFECT OF X P ROPAGATION IN T EST C OMPRESSION

Test Mode

Test Coverage

Pattern Count

Uncompress mode

98.57%

1247

Compress mode

93.24%

1743

that the write control lines need to be available from the top
level module, but it is impossible to add an additional top level
pin just for ATPG.
2) Improper memory model and verification time; Many
custom memories can not be described as simple behavior
codes. For example, memory can have multi-port read/write
access. Even after these modeling, it requires a lot of time to
verify ATPG model vs. real circuit behavior.

wAddr0
(5'b00000)

RdData0
Memory model - 1
32bit data set

IV. T HE R EGISTER BASED T EST S TRATEGY FOR

E MBEDDED M EMORY
The basic philosophy behind the register based test strategy
is to make the memory look like a single register during testing
mode and force writing to occur before any read operation in
this single register. This modification is done during the design
phase itself. The only requirement is to use a small number
of gates to constrain the address and X masking logic. The
next two sections will show the proposed methodology for
two types of memories: multi-port single cycle, and traditional
SRAM 6T cell based memory.

Memory model - 2
32bit data set

Memory model - 3
32bit data set

A. Memory that can Write and Read at the Same Cycle

Fig. 3.

RdData2
RdData3
rAddr3
(5'b00010)

RdData4
RdData5
rAddr5
(5'b00100)
rAddr6
(5'b01000)

Write Data
port 3

wAddr3
(5'b01000)

rAddr1
(5'b00000)

rAddr4
(5'b00100)

Write Data
port 2
wAddr2
(5'b00100)

RdData1

rAddr2
(5'b00010)

Write Data
port 1
wAddr1
(5'b00010)

Like high performance multi-port register files, some memories can write the data at the rising edge and read the data at the
falling edge. The benefit from this behavior with constrained
address values is that scan patterns require only two capture
pulses for stuck-at-fault detection during write through, The
first pulse is for write and read into the memory. The second
one is for capture from scanable flip-flops. The register file is
handling high timing critical path which is not allowed to use
the bypass method (Section III) which requires MUXs in the
memory output path. Usually accessing memory data through
a read operation is a timing critical. It is important not to
insert additional delay into this path. Figure 3 shows a multiported register file which has 4 write and 8 read ports. During
ATPG mode, all write and read address ports are constrained
and allow to write and read into memory at the same cycle.
To allow accessing memory locations per wordline simultaneously, different write addresses (wAddr0, wAddr1, wAddr2,
wAddr3) and read addresses (rAddr0, rAddr1, rAddr2, rAddr3,
rAddr4, rAddr5, rAddr6, rAddr7) are applied to each memory
during ATPG mode. 32 bit data memory cells are modeled as
32 flip flops. It is worth to mention that the address paths are
tested by MBIST and the primary concern is the data path.
The modeling og memory as flip-flops has the following
advantages:
1) For transition delay testing, it requires only three cycles
for capturing. For example, Write 0, Read0 and
capture (W0R0, W1R1, Capture) are needed rather than
five cycles for capturing (W0A1, W1A2, R0A1, R1A2,
Capture). this reduces the sequential depth for ATPG.
2) It does not need complicated memory modeling and
RAM-sequential ATPG.
3) It does not need time-consuming fault coverage management to know which paths are not covered by MBIST

rAddr0
(5'b00000)

Write Data
port 0

Memory model - 4
32bit data set

RdData6
RdData7
rAddr7
(5'b01000)

The Register Based Testing for a Multi-ported Register File

because the proposed method is the scan-based single

solution.
B. Register Based-ATPG for 6T Cell Based Memory Testing
Typical 6T cell based memory array dont support read and
write operation at the same cycle during functional mode, but
with minimal modification, a register based test strategy can be
applied with changing of sensing data on the sense amplifier
during ATPG test mode.
Figure 4(a) and 4(b) show a typical memory cell and
waveform for major signals on a 6T-cell based memory. The
access starts by asserting the word line based on the row
address and then the read or write signals assert write enable
or read enable. In the case of a write operation one side of the
column will be pulled low and the other side stays high (logic
1) based on the write data. During normal read operation when
the cell word line asserted a current flows from BL or BLB
based on the stored data and a voltage difference get developed
between BL and BLB.
The sense amplifier signal (sense en) is asserted to evaluate
the read data. It is desirable to do read and write in the same
cycle so there will be no issue in doing so if the read and write
uses the same address as the bitlines are shared and the write
operation already is pulling one side of the bitline low so the
sense amplifier will be able to detect the data to be written.
Even though the cell is not used to read, for testing purposes
there is full controllability and observability of all the signals
(output data bus) coming out of the array.

160

Shift
Shift
Si
ATPG_mode

Xmask

So

CLK

Phi2
Latch

CLK

Functional enable
Clock
Clk

Shift
C1

C2

C3

Clk
Xmask

Clock

Fig. 5.

X Masking Logic

(a)
Read cycle

Write cycle

conditional clock and does not require any gate in the data
path, timing impact to critical path is minimal. Note that this
approach is compatible with any commercial ATPG tool.

cllk

precharge

V. X P REVENTION ATPG M ETHOD FOR C USTOM

E MBEDDED M EMORY

WL

In this section, an ATPG method is introduced to avoid

generating Xs from the memory. This method can be applied
when the memory is customized and the ATPG tool has
difficulty to understand the write and read enable of memory.
This method may be used when the memory can do write and
read in the same cycle.

wren

rden

Bitline
development

BL/BLB

Td

Sense_en

A. Virtual X Prevention Logic for ATPG

Ta

dataout

(b)
Fig. 4.

(a) 6T Based Memory Array (b) Major Signal Waveforms

C. X Masking Logic for Scanable Flip-Flops to Output Data

Paths
As pointed out in Section III, Xs from memory can propagate to the test compressor. Even with a register based test
strategy, Xs can be generated from the register which is a nonscanable cell. This happens when the first writing occurrs. To
prevent the Xs during the first capture cycle (C1), Figure 5
shows how proposed X masking logic can prevent Xs. The
final output (clock) will be input clock of scanable the flipflops which are located on output data paths. Note that only
the first cycle of capture is masked and other capture cycles are
allowed to observe data from memory. ATPG mode is asserted
during ATPG. Expected clock behavior (clock) is shown in the
waveform. Because scan able FFs are controlled through this

Figure 6 provides an overview of how X prevention logic

will produce non-X patterns using ATPG.
The virtual memory is used to keep the status of each
memory cell. Figure 7 shows how virtual memory addresses
are initialized and updated. The virtual memory has same
address size as the actual memory. During the ATPG pattern
generation step, if a real memory address location is written
in first the matched virtual address is updated as 1. If the
memory address was read without being written, initialized
bit value 0 on the virtual memory address indicates that the
address has not been written and it is expected to generate Xs
from the memory. Dummy bus contention logic generates the
contention based on checked address. ATPG BUS contention
detection algorithm will reject the pattern and regenerate the
new pattern.
Bus contention checking can be done through clock-on
cycle, which occurs at the instant the clock is asserted, but
prior to the changes which would occur from propagating
sequential gate inputs to their outputs. Figure 8 shows the
different portions of a typical capture clock cycle and where
bus contention checking occurs. Clock-on contention checking

161

Memory Address
initalization

module check_pattern_valid (wclk, rclk, a, scan_n);

input wclk;
input rclk;
input [7:0] a;
input scan_n;
reg valid_pattern_1;
Update address

wire [1:0] dummy_bus;

write enable

reg check_addr [0:255] ;

event WRITE_OP;
always @(wclk or a) if (wclk) begin
0
Read enable

check_addr [a] = wclk;

invalid pattern

#0; ->WRITE_OP;

Dummy_bus
contention

Check address

end
always @(rclk or a or WRITE_OP)

if (rclk) begin
valid_pattern_1 = check_addr[a];

valid pattern
ATPG Capture clock Bus
contention checking
Rejected patterns

Dummy_bus
Non-contention

end
wire iclk, iwclk, wi_clk, i_clk;
wire [1:0] drv;

wire [1:0] hitor;

and scan_rclk (iclk, rclk, scan_n);
and ud0(drv[0], iclk, 1'b1);
ATPG Capture clock Bus
contention checking
Accpeted patterns

and ud1(drv[1], iclk, iwclk);

and ud2(iwclk, ~valid_pattern, ~wclk);
or uor_0(hitor[0], drv[1], drv[0]);

Fig. 6.

or uor_1(hitor[1], drv[0], drv[1]);

Block Diagram of X Prevention Logic Behavior

bufif1 ub0_0(dummy_bus[0], 1'b1, hitor[0]);

bufif1 ub0_1(dummy_bus[0], 1'b1, drv[0]);

check_addr[0:255]

check_addr[0:255]

00000000

00000001

00000010

00000011
.
.
.
.

0
.
.
.
.
0

0
.
.
.
.
0

Address initalization

Update address

11111111

bufif1 ub1_0(dummy_bus[1], 1'b1, hitor[1]);

Read address
00000000

bufif1 ub1_1(dummy_bus[1], 1'b0, drv[1]);

Dummy_bus
contention

initial $readmemh ("./ram1.data",check_addr);

0
Write address
00000010

Read address
00000010

endmodule

Dummy_bus noncontention

Fig. 9.

Verilog Code for 256X8 Memory of X Prevention Logic

shown in Figure 9.
B. Two-Step ATPG Pattern Generation

Fig. 7.

Address Initialization and Updated Address

identifies invalid read enable signals. If any pattern has this

type of contention, it is discarded and other patterns are
attempted. Bus contention checking can be done through two
ways which are contention checking after pattern generation
and contention checking before pattern generation (ATPG
methods). Use of ATPG methods is more CPU intensive [6].
Figure 8 shows valid pattern 1 which is deasserted when
an invalid read enable signal is detected. The equations for
valid pattern 1 is described below. WE is a writing event and
RE is a reading event into the memory location.
valid pattern 1 = valid1 [addr] & RE
valid1 [addr] = reset & WE
A bus with three-state buffers is used to generate dummy
bus contention. The Verilog code to implement this logic is
shift_n

Clock on
Pre-clock

Clock on
Post-clock

rclk

vaild_pattern_1

Fig. 8.

Contention Checking Method

To reduce the pattern generation complexity two modes

(regular ATPG mode and write through mode) were applied
one by one. The regular mode usually means scan-based
memory bypass mode. It is noted that the bypass method is
still useful in cases where the memory surrounding logic is
well covered by the bypass. If the path through memories has
room to put Bypass MUXs on data path this mode can be still
be applied, but the write through mode needs to be applied
if the design has uncovered faults in the surrounding logics.
Below is a sample of the steps of generating ATPG patterns
with embedded memory:
1) Set to regular mode (Bypass mode)
2) Run regular ATPG - Patterns set 1
3) Write fault list
4) Remove regular mode constraints and apply write
through mode constraints
5) Read fault list which comes from step 3
6) Run sequential ATPG - Patterns set 2
C. Verification of X Prevention Logic
X prevention logic is no-faulted during ATPG pattern generation and does not affect functional and other test mode.
ATPG models with X prevention logic must be robustly and
effectively verified that the patterns generated by the ATPG
tools based on the gate level models do indeed represent the
schematic therefore the silicon. The scan equivalency between

162

TABLE II
T HE E FFECT OF R EGISTER BASED T ESTING AND
P REVENTION ATPG M ETHOD

Design
A
B
C

Regular
Mode
49.63%
67.57%
97.80%

compressor logic was efficiently utilized by preventing Xs

from memory. Experiments with industry applications were
performed for performance evaluation and verification of the
proposed logic.

(A)
Regular Mode + Write through Mode (2 steps)
Coverage % of Xs
Pattern Count - Basic(Seq)
91.59%
34.71%
17(316)
93.11%
36.83%
10(173)
97.85%
34%
1091(345)

ACKNOWLEDGMENT
The Authors would like to thank the engineers at Qualcomm. We thank Paul Basset and Willie Anderson for their
absolutely exceptional support. Special thanks also to the
fantastic team at Austin.
R EFERENCES

Design
(B)

A
B
C

Coverage
97.21%
98.02%
98.51%

Register Based Testing

% of Xs
Pattern Count - Basic(Seq)
0%
16(299)
0%
9(156)
0%
1063(142)

these gate and transistor level models were verified using

industry standard RC Verilog switch level simulator [7].
VI. E XPERIMENTAL R ESULT
The proposed methods were implemented in a 28nm Qualcomm DSP core design project. Table II-(A) shows the coverage, percentage of Xs from scan chain and pattern count
of design before applying proposed schemes. Table II-(B)
shows effectiveness of proposed schemes. The test coverage is
increased compared to regular mode and write through mode.
The number of patterns is reduced compared to write through
mode. Design A is a register file which has multi-port read
and write ports. Design B is L2 data which uses 6T Cells.
Design C contains designs A, B and more custom embedded
memories. The regular mode means bypass mode (Design B)
or non-bypass mode (Design A). The reason with non-bypass
mode of design A is due to a timing critical path through
the memory. So it has constrained memory data outputs for
regular test mode. Original designs A and B are modified to
apply register based testing. Bypass MUXs (2 gate delays) are
removed from Design B, and AND/OR gates (1 gate delay)
are applied to constrain the address ports for register based on
testing. X masking logic is also introduced to design A and
B for each data output scan cells clock. For other memories
(except design A and B) X prevention ATPG method is used
to eliminate Xs when memory address locations are read in
first before being written. Design C is simulated with the
test compressor. Non-X values on the scan chains make the
compressor more effective.

[1] P. Wohl and J. Waicukauski, USING VERILOG SIMULATION LIBRARIES FOR ATPG, in Proc. of International Test Conference, 1999,
pp. 10111020.
[2] S. Yadavalli and S. Sengupta, Impact and Cost of Modeling Memories
for ATPG for Partial Scan Designs, in Proc. of International Test
Conference, 1997, pp. 274278.
[3] N.A.Touba, Survey of test vector compression techniques, Design Test
of Computers, IEEE, vol. 23, no. 4, pp. 294 303, Apr 2006.
[4] S. Mitra, S. Lumetta, and M. Mitzenmacher, X-tolerant signature analysis, in Proc. of International Test Conference, Oct. 2004, pp. 432
441.
[5] E. K. Vida-Torku and G. Joos, Designing for scan test of high performance embedded memories, in Proc. of International Test Conference,
Oct 1998, pp. 101 108.
[6] TetraMAX, Version E-2010.12-SP2, in Synopsys Inc., 2010.
[7] G. Seok, B. Mohammad, H. Kim, and P. Bassett, Verification of gate
level model for custom design in scan mode, in Microprocessor Test and
Verification, 2007.

VII. C ONCLUSION
This paper addressed the issue of Xs propagating to the
test compressor. When an SOC design uses custom embedded
memories, the ATPG tool could not control write and enable
ports properly during the write through mode. A register based
test strategy and X prevention memory model is presented
for ATPG, which increases the overall test coverage. The test
163