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Standard Cell Characterization

Standard cell characterization is the process of simulating standard cells to extract timing, power, and leakage information. This is done for different process corners representing best, worst, and typical transistor behavior. Characterization provides simple models of delay, function, power constraints for each cell to enable faster simulation compared to using complex GDSII layouts. The characterization flow involves extracting SPICE netlists from layouts, simulating at different process corners to determine timing arcs like setup/hold times and power metrics like dynamic, short-circuit, leakage and switching power.

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668 views

Standard Cell Characterization

Standard cell characterization is the process of simulating standard cells to extract timing, power, and leakage information. This is done for different process corners representing best, worst, and typical transistor behavior. Characterization provides simple models of delay, function, power constraints for each cell to enable faster simulation compared to using complex GDSII layouts. The characterization flow involves extracting SPICE netlists from layouts, simulating at different process corners to determine timing arcs like setup/hold times and power metrics like dynamic, short-circuit, leakage and switching power.

Uploaded by

Lakshman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Standard Cell

Characterization

Basics
A standard cell is a group of transistors and interconnect
structures that provides a boolean logic function (e.g. AND, NAND,
XOR, XNOR, inverters) or a storage function (flipflop or latch).
The Standard cell library describes a list of cells that a synthesizer
may use to implement the error free designs.
Cell Characterization is the process of simulating a standard cell
with an analog simulator or an automated characterization tool to
extract the timing,power and leakage information.

Process Corner definitions


All the standard cells are in general characterized for 3 sets of
conditions: best case, worst case and the typical case.
The best case is when both the PMOS and NMOS transistors run
faster than usual, with a higher power supply (+10% more than
nominal) and at the lowest operating temperature.
The worst case is when both transistors are slow, at the higher
expected temperature and lower supply voltage (-10% usually).
Typical case is at the room temperature when both the transistors
are typical and the nominal VDD.
Worst PVT : P-SS V-min Temp-high
Best PVT : P-FF V-max Temp-low
Worst Cold PVT : P-SS V-min Temp-low
Best Hot PVT : P-FF V-max Temp-high

Need for Characterization?


Problems of Standard Cells in polygon level format (GDSII)
Extraction of functionality is complicated and unnecessary
Functional/Delay simulation takes way too long
Power extraction for a whole chip takes too long
Automatic detection of timing constraints (e.g. Setup time) is
difficult
Solution
A simple model for delay, function, constraints and power on
cell/gate level => cell characterization

Inputs for Characterization


The cell library information required for characterization are:
cdl ang gds for extracting netlist
Spice models
Extracted netlist --Transistors, resistances and capacitances are
extracted with special tools and saved as SPICE netlist
LEF -- Abstracted views information is present in this file. The
abstract view of a cell contains the area of the cell, routing
obstructions and pin locations.
Library-wise parameters have to be specified in a file. e.g. max
transition time, PVT-corners, templates etc.
Verilog/VHDL models for all the cells.

Characterization Flow

Timing arcs
Cell Rise: It is the time taken for the output to rise by 50% with
reference to the input change by 50%
Cell Fall: It is the time taken for the output to fall by 50% with
reference to the input change by 50%
Rise Transition: It is the time taken for the output voltage to rise
from +10 % VDD voltage to the +90 % VDD voltage level.
Fall Transition: It is the time taken for the output voltage to fall from
+90 % VDD voltage to the +10 % VDD voltage level.
Propagation Delay: It is the time required for a signal on the input to
arrive as a resulting signal on the output. The distance between the
two signals is measured at +50 % VDD voltage level.

cont..
Setup Time : It is the minimum amount of time the data signal should
be held stable before the clock signal so that the data is reliably
sampled by the clock.
Hold Time : It is the minimum amount of time the data signal should be
held stable after the clock signal so that the data is reliably sampled.
Recovery time : It is the minimum amount of time between the
asynchronous signal going inactive and the next active clock edge.
Removal Time : It is the minimum amount of time between an active
clock edge and the asynchronous signal going inactive.

cont..

Figure : Setup and Hold times


Figure : Recovery and removal times

Capacitance
The capacitance considered in delay evaluation in the circuit consists of
two parts.
1. Interconnect parasitic capacitance : The capacitance between one
metal layer and the substrate.
2. Input pin capacitance : The capacitance on the input pin that is
located between the gate and the substrate of the cell.

Power
Static Power : Power dissipated when input isnt switching
Dynamic Power : Power dissipated due to charging and
discharging of the load capacitance.
Short-Circuit Power : Power dissipated due to direct current from
VDD to GND when both transistors are on.
Leakage Power : Power dissipated due to off transistors.
Rise Power : Power dissipated when output is switching from low to
high.
Fall Power : Power dissipated when output is switching from high to
low.

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