DANANG UNIVERSITY OF TECHNOLOGY

CENTER OF EXCELLENCE

EE271
LABORATORY REPORT:
LAB 01
An Introduction to Modeling, Verilog,
and Real World Digital Parts

Group 06:

L Vng Thi
Trn Quc Trung
Trn Bo Tin

Class:

12ECE

Part 1:
-Source code:
+ testBench.v

module testBench;
// wires connect things together
wire
lesseq, a, b, c, d;
Comparator
TestModule

myComp (lesseq, a, b, c, d);

myTester (a,b,c,d, lesseq);

endmodule

+ Comparator.v
module Comparator(lesseq, a, b, c, d);

parameter
output
input

delay = 10
lesseq;
a, b ,c, d;

// Ouputs: lesseq
// Inputs: to compare, ab and

cd

and
and
and
and
and

#delay
#delay
#delay
#delay
#delay

and1(term0,
and2(term1,
and3(term2,
and4(term3,
and5(term4,

not
not

#delay
#delay

inv0(notC, c);
inv1(notD,d);

or

#delay

or1(lesseq, term0, term1, term2, term3, term4);

endmodule

notC, notD);
a,b);
a, c, notD);
b, notC);
a, notC);

//close Comparator module

+ TestModule.v
module TestModule (a,b,c,d, lesseq);
// Declare variables:
input
output
parameter
stimuli
reg
for checking outputs

// declare test module

lesseq;
a, b, c, d;
stimDelay = 15;

// Module inputs
// Module outputs
// Delay between generating

a, b, c, d;

// regs for setting values

// a variable must be of type

reg in order to
// assign a value to it
initial
initializing
begin
variables
a =
b =
c =
d =
end

// this initial block assigns

// values to the designated
0;
0;
0;
0;

initial
apply the test vectors

// this initial block will

begin

// begin initial loop

$display("CLOCK\t\t INPUTS \t\t

OUTPUT\t\tTIME");
$display("--a-- \t --b--\t --c--\t--d--\t
--lesseq--\t\t------");
$monitor(" %b
\t %b
\t %b \t %b
\t\t %b"
,a,b,c,d,lesseq,$time);
//

The following is our test code or test vectors.

//

begin a second block to perform the simulation

repeat (2)
twice for illustration

// repeat this process

begin

// begin REPEAT loop

// we write in decimal and the compiler translates to binary
#stimDelay {a,b,c,d} = 0;
// a=0, b=0, c=0, d=0
#stimDelay {a,b,c,d} = 1;
// a=0, b=0, c=0, d=1
#stimDelay {a,b,c,d} = 2;
// a=0, b=0, c=1,

d=0
#stimDelay {a,b,c,d} = 3;

// a=0, b=0, c=1, d=1

#stimDelay
#stimDelay
#stimDelay
#stimDelay

{a,b,c,d}
{a,b,c,d}
{a,b,c,d}
{a,b,c,d}

=
=
=
=

4;
5;
6;
7;

//
//
//
//

a=0,
a=0,
a=0,
a=0,

b=1,
b=1,
b=1,
b=1,

c=0,
c=0,
c=1,
c=1,

d=0
d=1
d=0
d=1

#stimDelay
#stimDelay
#stimDelay
#stimDelay

{a,b,c,d}
{a,b,c,d}
{a,b,c,d}
{a,b,c,d}

=
=
=
=

8;
9;
10;
11;

//
//
//
//

a=1,
a=1,
a=1,
a=1,

b=0,
b=0,
b=0,
b=0,

c=0,
c=0,
c=1,
c=1,

d=0
d=1
d=0
d=1

#stimDelay
#stimDelay
#stimDelay
#stimDelay

{a,b,c,d}
{a,b,c,d}
{a,b,c,d}
{a,b,c,d}

=
=
=
=

12;
13;
14;
15;

//
//
//
//

a=1,
a=1,
a=1,
a=1,

b=1,
b=1,
b=1,
b=1,

c=0,
c=0,
c=1,
c=1,

d=0
d=1
d=0
d=1

end

// close the REPEAT loop

// the following code illustrates how we can test for aberrant conditions
// we use the specific SEQUENCE of events to cause a glitch - were there
others
begin
$display("Producing Glitch");
#stimDelay {a,b,c,d} = 0;
#stimDelay {a,b,c,d} = 10;
end
#(2*stimDelay);
simulation
$stop;
simulation

// a=0, b=0, c=0, d=0

// a=1, b=0, c=1, d=0
// needed to see END of
// temporarily stops
// goto Verilog interactive

mode
// need to type 1.1 or
'$finish;'
$finish;

// finish simulation

end
endmodule

// close second initial loop

// close test-module

+ Questions:
1. Draw a logic diagram using the logic gates that were used to build the digital circuit in the
Verilog source code. Use the same signal names indicated in the source code. Use AND, OR, and
NOT gates.

2. Draw the truth table for this circuit. Looking at the waveform from your simulation may help.
A truth table for a logic circuit has an input side and an output side. The input side lists all of the
possible input combinations to the circuit and the output side lists the value(s) of the output(s) for
each input combination. Figure 4 below shows the logic symbol and associated truth table for an
AND gate. The left hand side of the truth table elaborates all 4 possible input combinations and
the right hand side gives the corresponding output.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Term1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0

Term2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

Term3
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0

Term4
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0

Term5
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0

lesseq
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1

3. When you run the simulation. Does the output of the Verilog program agree or disagree with
your truth table?
The output of the Verilog program disagrees with my truth table.
Because there are delay time in process. Delay = 10 time unit (initial) and stimdelay = 15 time
unit.

4. Please explain the apparently incorrect order in which the results in the output log are printed;
specifically when the output line Producing Glitch prints.
Because the time delay, the value of output lesseq is X when (A=0,B=0,C=0,D=0) and lesseq is
different from truth table when the values of A,B,C,D increasing.

Specifically, when the output line Producing Glitch prints, the value of lesseq is set to 1 when
(A=0,B=0,C=0,D=0).And after that when (A=0,B=1,C=0,D=1) the value of lesseq change repeatly
(from 0 to 1).

5. Change the value of the delay in the program from 10 to 0. Rerun the simulation. Does the
output of the Verilog program agree or disagree with your truth table? Please explain any
differences.
When the delay time is 0, the output of Verilog program agree with my truth table.
When the output line Producing Glitch prints, there are just 3 values display, and it is the same with
truth table

Another different points is when the delay time is 0, the output change there status from 0 to 1 very
quickly and almost immediately.

Line lesseq change from 1 to 0 and 0 to 1 very fast

6. Change the delay in the program back to 10 time units. Change the stimDelay in the test
module to 5 time units. What affect does this change have on the outputs of your simulation?
The outputs will delay for a long time

7. What advantages are there to using a program like Verilog? Name three or more.
- Free
- Good user interface
- Powerful simulation
+ Waveform of the output Verilog with time delay = 0

+ Waveform of the output Verilog with time delay = 10

+ Waveform of the output Verilog with time delay = 10 and stimDelay = 5

Part 2:
1. A copy the Verilog source code for the MultiFunction Logic Block, the testbench,
and the tester.
+ The tester
module TestModule (SEL1,SEL2,A,B, RESULT);
// Declare variables:
input
output
parameter
reg

RESULT;
SEL1, SEL2, A, B;
stimDelay = 15;
SEL1, SEL2, A,B;

initial
begin
SEL1 = 0;
SEL2 = 0;
A = 0;
B = 0;
end

// declare test module

// Module inputs
// Module outputs
// Delay between generating stimuli
// regs for setting values for checking outputs
// a variable must be of type reg in order to
// assign a value to it
// this initial block assigns initializing
// values to the designated variables

initial

// this initial block will apply the test vectors

begin

// begin initial loop

$display("CLOCK\t\t INPUTS \t\t

OUTPUT\t\tTIME");
$display("--a-- \t --b--\t --c--\t--d--\t
--lesseq--\t\t------");
$monitor(" %b
\t %b
\t %b \t %b
\t\t %b" ,SEL1,SEL2,A,B,RESULT,
$time);
//

The following is our test code or test vectors.

//

begin a second block to perform the simulation

repeat (2)

// repeat this process twice for illustration

begin

// begin REPEAT loop

// we write in decimal and the compiler translates to binary
#stimDelay {SEL1,SEL2,A,B} = 0;
#stimDelay {SEL1,SEL2,A,B} = 1;
#stimDelay {SEL1,SEL2,A,B} = 2;
#stimDelay {SEL1,SEL2,A,B} = 3;

end

#stimDelay
#stimDelay
#stimDelay
#stimDelay

{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}

=
=
=
=

4;
5;
6;
7;

#stimDelay
#stimDelay
#stimDelay
#stimDelay

{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}

=
=
=
=

8;
9;
10;
11;

#stimDelay
#stimDelay
#stimDelay
#stimDelay

{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}
{SEL1,SEL2,A,B}

=
=
=
=

12;
13;
14;
15;

// close the REPEAT loop

// the following code illustrates how we can test for aberrant conditions

// we use the specific SEQUENCE of events to cause a glitch - were there others
begin
$display("Producing Glitch");
#stimDelay {SEL1,SEL2,A,B} = 0;
#stimDelay {SEL1,SEL2,A,B} = 10;
end
#(2*stimDelay);
$stop;

// a=0, b=0, c=0, d=0

// a=1, b=0, c=1, d=0
//
//
//
//
//

$finish;
end

needed to see END of simulation

temporarily stops simulation
goto Verilog interactive mode
need to type 1.1 or '$finish;'
finish simulation

// close second initial loop

endmodule

// close test-module

+ testBench
module testBench;
// wires connect things together
wire
RESULT,SEL1,SEL2,A,B;
Comparator
TestModule

myComp (RESULT,SEL1,SEL2,A,B);
myTester (SEL1,SEL2,A,B,RESULT);

endmodule

+ Comparator
module Comparator(RESULT,SEL1,SEL2,A,B);
parameter
output
input

delay = 0;
RESULT;
SEL1,SEL2,A,B;

not
not

#delay
#delay

and
or
xor

#delay
and2(term0,A,B);
#delay
or1(term1,A,B);
#delay
xor1(term2,A,B);

and
and
and
or

#delay
#delay
#delay
#delay

not1(notSEL1,SEL1);
not2(notSEL2,SEL2);

and3(term3,notSEL1,term0,notSEL2);
and4(term4,notSEL1,term1,SEL2);
and5(term5,SEL1,term2,notSEL2);
or2(RESULT,term3,term4,term5);

endmodule

2. A copy of the simulation results.