Modeling and Simulation of Reverse Power
Modeling and Simulation of Reverse Power
I. INTRODUCTION
1
Muhammad Mohsin Aman, Ghauth Bin Jasmon and Ab. Halim Bin Abu
Bakar are working with University of Malaya, Malaysia. They can be reached
at [email protected], [email protected], [email protected]
respectively.
2
Muhammad Qadeer Ahmed Khan is working with ENI Corporate
University, Italy. He can be reached at [email protected].
3
Jasrul Jamian Jamian is working with Universiti Teknologi Malaysia. He
can be reached at [email protected].
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TABLE I
MOTORING REVERSE POWER REQUIREMENTS AND
REVERSE POWER POSSIBLE DAMAGES [6]
Prime
Mover
Motoring Power
(% of rated)
5-25
Diesel
Engine
Gas Turbine
Hydro
Steam
Turbine
10-15
(Split Shaft)
>50%
(Single Shaft)
0.2-2
(blades of water)
>2
(blades of water)
0.5-6
Possible Damage
Protection
Setting
Fire/Explosion due
to un-burnt fuel
Mechanical
Damage to
gearbox/shafts
Gear box damage
50 % of
motoring
2012 IEEE International Power Engineering and Optimization Conference (PEOCO2012), Melaka, Malaysia: 6-7 June 2012
(a)
(b)
Figure 1. (a) Phasor Representation (b) Block Representation of Current
and Voltages under Reverse Power Flow
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2012 IEEE International Power Engineering and Optimization Conference (PEOCO2012), Melaka, Malaysia: 6-7 June 2012
multiplied to give an output 1 during the overlapping and 1 for the non-overlapping interval. The product is then
integrated from 0 to -L. The upper limit of the integrator is
set at 0 value so that under normal load flow conditions the
integral always remains less than 0. However, under reversed
power flow conditions the integral output tends to fall until it
reaches the threshold value L. In present case L is set at 0.01,
however any value could be selected depending on the amount
of reverse power. The block diagram for implementing the
directional element is shown in Fig. 5 and its implementation
on Simulink is shown in Fig. 6.
Figure 3a. Angle between Voltage and Current Waveforms under Normal
Conditions
Figure 3b. Angle between Voltage and Current Waveforms under Fault
Conditions
A. Directional Element
In the directional element, low voltage and current signals
from CT and PT signals are converted to a perfect square
wave form with 1 values. The two level signals are then
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2012 IEEE International Power Engineering and Optimization Conference (PEOCO2012), Melaka, Malaysia: 6-7 June 2012
B. Delay Element
The purpose of the delay element is to prevent the relay
from sending a false trip signal to the CB during transient
or a temporary fault conditions. The logic for implementing
delay element is represented Fig. 7 (left side).
The output of the directional element (input of delay
element) is sent to a decision block (switch4) whose output
is 0 in case of normal and 1 in case of abnormal (reverse
power) conditions. This output in turn is integrated. The
value of the integral is compared with the threshold level
T, whose value is set equal to the amount of delay time
desired. When the value of the integral is less than the level
T, the output of the delay element will be 1, indicating
normal condition.
Under stable condition, since the input received at the
integrator is 0. Hence the value of the integrator will
always be 0 (less than value T), therefore the output of
the delay element will correspondingly be 1. However
under permanent abnormal condition, the input to the
integrator will be 1 and after T seconds, the integral
value will exceed T, causing the delay element to produce
C. Hold Block
The purpose of the hold block is to keep the state of the
relay stable after the relay has tripped. This is because once
the CB has opened, the fault will cease to exist, indicating a
normal condition and tempting the relay to again send a 1
signal to the CB, causing it to again close.
The logic for implementing the hold block is shown in
Fig. 7 (right side). The 0 value from the delay block is
first inverted and then integrated. As soon as the value of
the integral exceeds 0 value, the o/p of the hold block will
change from 1 to 0. However here integrator cannot
reset therefore once the integral exceeds its threshold of 0
it will never come back to that value and hence the output
of the hold block will always be 0 value.
The switch block, between delay and hold element is
used only to prevent the relay from false tripping during
starting transients period.
A. Case 1:
This is a normal case in which the mechanical input to
the generator changes from 0.2pu to 0.8pu at 20 sec. The
input/output power and relay status observed is shown in
Fig. 9. In this case, relay does not trip, however output
power oscillate initially about the equilibrium point.
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2012 IEEE International Power Engineering and Optimization Conference (PEOCO2012), Melaka, Malaysia: 6-7 June 2012
C. Case 3:
In third case, the mechanical input to the generator
changes from 0.5pu to -0.1pu at 90 sec. The input/output
power and relay status observed is shown in Fig. 12.
B. Case 2:
In second case, the mechanical input to the generator
changes from 0.5pu to 0.1pu at 90 sec. The input/output
power and relay status observed, shown in Fig. 10.
Figure 12. Relay performance (a) Input/Output Power (b) Relay Status
Figure 10. Relay performance (a) Input/Output Power (b) Relay Status
D. Case 4:
Case 4 is a cumulative case to show the performance of
the reverse power relay under different conditions. The
mechanical input changes to the generator changes several
times from 0 to 140 sec.
From Fig. 14, it could be observed that the system
operates safely during all mechanical transients and safely
isolated the generator at 107sec, when mechanical input
loss occurred.
Figure 11. Integrator Input (From Switch2 in directional element)
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2012 IEEE International Power Engineering and Optimization Conference (PEOCO2012), Melaka, Malaysia: 6-7 June 2012
Figure 14. Relay performance (a) Input/Output Power (b) Relay Status
S=210MVA
VIII. ACKNOWLEDGMENT
The first author gratefully acknowledges the financial
support given by the University of Malaya, under Bright
Spark Programme (BSP) for the PhD work in this area.
IX. REFERENCES
[1]
(a)
(b)
Figure 15. (a) Delay Time Integral Output (b) Relational Element
Output
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