Code No: 26027 RR Set No.

2
III B.Tech II Semester Supplimentary Examinations,February 2010
ADVANCED COMPUTER ARCHITECTURE
Common to Information Technology, Computer Science And Engineering,
Computer Science And Systems Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain hierarchical structured multiprocessor system .

(b) Describe processor characteristics for multiprocessing systems.

2. (a) Give architecture of the front-end system interface with Cray-1 memory and
functions sections.
(b) Briefly explain the architecture of Cyber-205.

3. Explain different basic architectural features of parallel computers.

4. (a) List the major characteristics, advantages and shortcomings of three types of
multiprocessor operating systems.
(b) List the four main sources of performance degradation of the dynamic coher-
ence check algorithm.

5. Discuss sorting patterns with respect to three ways of indexing theP E 0 s

6. (a) The inner loop of a certain program is completed to perform the following op-
erations in a Sequence. Deduce Macro instruction after applying the Internal
and give the simplified data flow graph forwarding technique.
i. R0 ← (M1 )
ii. R0 ← (R0 ) + (M2 )
iii. R0 ← (R0 ) ∗ (M3 )
iv. M4 ← R0
(b) Explain the effect of Interrupt Signals on pipeline processing.

7. (a) Explain a square systolic array for L-U decomposition.

(b) Describe a matrix Arithmetic architecture processor.

8. (a) Classify the various multistage SIMD interconnection N/W according to the
3 distinct features blocking , rearrangeable and non-blocking
(b) The Omega N/W is capable of performing broadcasting. .If the number of
destination P E 0 s is a power of two , give a simple routing algorithm to achieve
this capability

?????

1
Code No: 26027 RR Set No. 4
III B.Tech II Semester Supplimentary Examinations,February 2010
ADVANCED COMPUTER ARCHITECTURE
Common to Information Technology, Computer Science And Engineering,
Computer Science And Systems Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) The inner loop of a certain program is completed to perform the following op-
erations in a Sequence. Deduce Macro instruction after applying the Internal
and give the simplified data flow graph forwarding technique.
i. R0 ← (M1 )
ii. R0 ← (R0 ) + (M2 )
iii. R0 ← (R0 ) ∗ (M3 )
iv. M4 ← R0
(b) Explain the effect of Interrupt Signals on pipeline processing.

2. (a) Classify the various multistage SIMD interconnection N/W according to the
3 distinct features blocking , rearrangeable and non-blocking
(b) The Omega N/W is capable of performing broadcasting. .If the number of
destination P E 0 s is a power of two , give a simple routing algorithm to achieve
this capability

3. (a) List the major characteristics, advantages and shortcomings of three types of
multiprocessor operating systems.
(b) List the four main sources of performance degradation of the dynamic coher-
ence check algorithm.

4. (a) Explain hierarchical structured multiprocessor system .

(b) Describe processor characteristics for multiprocessing systems.

5. Discuss sorting patterns with respect to three ways of indexing theP E 0 s

6. (a) Give architecture of the front-end system interface with Cray-1 memory and
functions sections.
(b) Briefly explain the architecture of Cyber-205.

7. (a) Explain a square systolic array for L-U decomposition.

(b) Describe a matrix Arithmetic architecture processor.

8. Explain different basic architectural features of parallel computers.

?????

2
Code No: 26027 RR Set No. 1
III B.Tech II Semester Supplimentary Examinations,February 2010
ADVANCED COMPUTER ARCHITECTURE
Common to Information Technology, Computer Science And Engineering,
Computer Science And Systems Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) The inner loop of a certain program is completed to perform the following op-
erations in a Sequence. Deduce Macro instruction after applying the Internal
and give the simplified data flow graph forwarding technique.
i. R0 ← (M1 )
ii. R0 ← (R0 ) + (M2 )
iii. R0 ← (R0 ) ∗ (M3 )
iv. M4 ← R0
(b) Explain the effect of Interrupt Signals on pipeline processing.

2. (a) Explain a square systolic array for L-U decomposition.

(b) Describe a matrix Arithmetic architecture processor.

3. (a) Explain hierarchical structured multiprocessor system .

(b) Describe processor characteristics for multiprocessing systems.

4. Explain different basic architectural features of parallel computers.

5. (a) Give architecture of the front-end system interface with Cray-1 memory and
functions sections.
(b) Briefly explain the architecture of Cyber-205.

6. (a) Classify the various multistage SIMD interconnection N/W according to the
3 distinct features blocking , rearrangeable and non-blocking
(b) The Omega N/W is capable of performing broadcasting. .If the number of
destination P E 0 s is a power of two , give a simple routing algorithm to achieve
this capability

7. (a) List the major characteristics, advantages and shortcomings of three types of
multiprocessor operating systems.
(b) List the four main sources of performance degradation of the dynamic coher-
ence check algorithm.

8. Discuss sorting patterns with respect to three ways of indexing theP E 0 s

?????

3
Code No: 26027 RR Set No. 3
III B.Tech II Semester Supplimentary Examinations,February 2010
ADVANCED COMPUTER ARCHITECTURE
Common to Information Technology, Computer Science And Engineering,
Computer Science And Systems Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain hierarchical structured multiprocessor system .

(b) Describe processor characteristics for multiprocessing systems.

2. (a) Give architecture of the front-end system interface with Cray-1 memory and
functions sections.
(b) Briefly explain the architecture of Cyber-205.

3. Discuss sorting patterns with respect to three ways of indexing theP E 0 s

4. Explain different basic architectural features of parallel computers.

5. (a) Explain a square systolic array for L-U decomposition.

(b) Describe a matrix Arithmetic architecture processor.

6. (a) The inner loop of a certain program is completed to perform the following op-
erations in a Sequence. Deduce Macro instruction after applying the Internal
and give the simplified data flow graph forwarding technique.
i. R0 ← (M1 )
ii. R0 ← (R0 ) + (M2 )
iii. R0 ← (R0 ) ∗ (M3 )
iv. M4 ← R0
(b) Explain the effect of Interrupt Signals on pipeline processing.

7. (a) List the major characteristics, advantages and shortcomings of three types of
multiprocessor operating systems.
(b) List the four main sources of performance degradation of the dynamic coher-
ence check algorithm.

8. (a) Classify the various multistage SIMD interconnection N/W according to the
3 distinct features blocking , rearrangeable and non-blocking
(b) The Omega N/W is capable of performing broadcasting. .If the number of
destination P E 0 s is a power of two , give a simple routing algorithm to achieve
this capability

?????