IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)

e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 4, Ver. I (Jul - Aug .2015), PP 46-51
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Implementation of Optimized Floating Point Adder on FPGA

Deepak Mishra

Vipul Agrawal

Research Scholar
Dept. of Electronics and Communication Engineering,
Trinity Institute of Science & Research, Bhopal,
[email protected]

Assist. Prof.
Dept. of Electronics and Communication Engineering
Trinity Institute of Science & Research, Bhopal,
[email protected]

Abstract: This paper presents the FPGA implementation of a Decimal Floating Point (DFP) adder. The design
performs addition on 64-bit operands that use the IEEE 754-2008 DPD encoding of DFP numbers. The design
uses an equal bypass adder, this adder reduces the power consumption and it also reduces the delay by
reducing the gate count. The design also uses barrel shifter instead of sequential shifter. The design has a
maximum combinational delay of 45ns on a Virtex-5 with a latency of 1 cycle. The proposed DFP adder
supports operations on the decimal64 format and it is easily extendable for the decimal128 format.
Keywords: Floating point adder, FPGA, Delay, Area overhead

I.

Introduction

The binary floating point (BFP) arithmetic has certain flaws namely; it cannot provide correct decimal
rounding and cannot precisely represent some decimal fractions such as 0.001, 0.0475 etc [1]. There are many
applications where a precision is required such as billing, insurance, currency conversion, banking and some
scientific applications. European Union requires that currency conversion to and from EURO is to be calculated
to six decimal digits [2]. One study estimates that errors generating from BFP arithmetic can sum up to a yearly
billing of over dollar 5 million for a large billing organization [3]. Therefore decimal floating point (DFP)
arithmetic becomes very important in many current and future applications as it has ability to represent decimal
fractions precisely. DFP arithmetic also has the ability to provide correct decimal rounding that will mimic the
manual rounding.
Applications which cannot tolerate errors generating from BFP arithmetic, these application use
software platforms to perform DFP arithmetic [1]. There are many software packages which are available for
example: the java BigDecimal library [5] and IBMs decNumber library [4]. Also Intel published results for a
decimal arithmetic library which uses Binary integer decimal (BID) encoding. These software packages are
good enough for current applications, but trends towards globalization and e-commerce are increasing, so faster
response of these systems is required. Software designs to these systems may be inadequate with the increasing
performance demands of future systems. So hardware implementation of these systems is the need of the hour.
In 2008, the IEEE 754-1985 floating point standard has been revised and the new standard called the
IEEE 754-2008 floating point standard was setup [6], which includes specifications for DFP formats, encoding
and operations. The IEEE 754-2008 standard includes an encoding format for DFP numbers in which the
significand and the exponent (and the payloads of NaNs) can be encoded in two ways namely; binary encoding
and decimal encoding. [7]
Both the encoding formats break a number into a sign bit s, an exponent E, and a p-digit significand c.
The value encoded is (1)s 10E c. In both formats the range of possible values is identical, but the
significand c is encoded differently. In the decimal encoding, it is encoded as a series of p decimal digits using
the densely packed decimal encoding (DPD). In the binary encoding also known as binary integer decimal
(BID) encoding, it is encoded as a binary number.
In this paper a floating point adder unit is proposed. This floating point adder unit is IEEE P754 2008
complaint and based on densely packed decimal (DPD) encoding for DFP arithmetic. The proposed floating
point adder unit uses low power equal bypass adder to reduce the power consumption of the design.

II.

Decimal Floating Point Representation

In IEEE 754-2008, the value of a finite DFP number with an integer significand is
v= (1)s 10q c
where S is the sign, q is the unbiased exponent, and C is the significand. The precision or the length of the
significand is denoted as p, which is equal to 7, l6, or 34 digits, for decimal32, decimal64, or decimall28,
respectively. Figure 1.1 shows the double precision decimal64 Decimal Floating Point format.

DOI: 10.9790/2834-10414651

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Implementation of Optimized Floating Point Adder on FPGA

Sign
Combination (w + 5)
Trailing Significand (c)
Figure 1.1: Decimal 64 Decimal floating
(s)
point format DPD encoded
The l-bit Sign Field, S indicates the sign of a
1 Bit
13 bits
50 bits
number. The (w+5)-bit Combination Field, G
provides the most significand digit (MSD) of the significand and a non-negative biased exponent, E such that E
= q + bias. The exponent is almost always encoded in binary. The G Field also indicates special values, such as
Not-a-Number (NaN) and infinity (00). The remaining digits of the significand are specified in the t-bit Trailing
Significand Field, T. Table 1 shows the combination field. [DPD Paper]
Table 1: Combination field
Number type
finite
finite
infinite
NaN

Combination
field
abcde
11 a b c
11110
11111

Exponents
Bits
ab
ab
..
..

Significand
MSD
0cde
100e
....
....

Decimal Floating Point Addition Algorithm

Figure 1.2 shows the algorithm for adding two decimal floating point numbers encoded in DPD dec64 format.

Figure 1.2: Floating Point Addition Algorithm

Decimal Floating Point Adder - Implementation

Figure 1.3: Floating point adder: Architecture

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Implementation of Optimized Floating Point Adder on FPGA

This architecture of floating point adder is proposed for IEEE 754-2008 decimal64 format and it can
easily be extended to 128 bit format.
Arrows shows the direction of data flow. The adder is designed as follows: the decoder unit decodes
the decimal 64 bit number and extracts sign (As, Bs), exponent (Aexp, Bexp) and mantissa (Amant, Bmant)
information. The effective operation (EOP) logic defines the actual operation by xoring the two signs As and Bs.
If both number are either positive or negative then the EOP is addition and if one of them is negative then the
EOP is subtraction. We have two channels in our design Channel A and channel B, channel A is for large
number and channel B is for smaller number. So next the two exponents are compared, if Ae is smaller than Be
then numbers are swapped, the larger of two number is assigned to channel A and the smaller one is assigned to
channel B using a swapping logic. Here the difference between two exponents is also computed and assigned to
variable d. Next the mantissa Bm (smaller of two mantissas) is shifted right by amount d by barrel shifter.
Now the two numbers are aligned for addition/subtraction. The effective operation is performed using a low
power BCD adder. The effective operation is determined earlier using EOP. Next the rounding logic rounds the
resultant mantissa. The sign, exponent and mantissa of resultant are encoded in IEEE P754-2008 decimal64
format.

III.

Low Power Adder Design

The floating point adder shown in figure 1.3 uses a 16 digit BCD adder for the addition of mantissa Am
and Bm. Figure 1.4 shows the 4 bit BCD adder, this BCD adder uses two 4 bit ripple carry adder, these 4 bit
ripple carry adder uses conventional full adder.

Figure 1.4: BCD adder

Figure 1.5 shows the conventional full adder. All the logic gates in this design are applied with inputs
all the time and this consumes power at all times, also the gate count for sum is two and the gate count for carry
is three. We are replacing the conventional full adder by equal bypassing full adder. Figure 1.5 shows the low
power low delay equal bypassed full adder.

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Implementation of Optimized Floating Point Adder on FPGA

Figure 1.5: Conventional full adder

Figure 1.6: Low power low delay full adder

In this full adder when input A and input B are equal then the output of XOR gate is 0, this makes
the control input of tri-state buffer 0, now the output of tri-state inverter is high impedance Z, this blocks one
channel of the multiplexer and reduces the power consumption. And if the two inputs A and B are different
then the output of the XOR gate is 1 and control input of tri-state inverter is also 1, the input C is
complemented.
Also at all times the gate count of Cout is reduces to 1, this is 2 less than the conventional full adder.
So the power consumption and delay of the BCD adder is reduced. [Low power adder]

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Implementation of Optimized Floating Point Adder on FPGA

IV.

Implementation & Results

All logics were described in VHDL. The design has been implemented on Xilinx Virtex-5 device XC5VLX30FF324-3. Resource utilization is shown in table 2. Design statics are shown in table 3.
Table 2: Device Utilization Summary
S.No.
1
2

Resource
Number of slice registers
Number of slice LUTs

Utilization
5/19200
803/19200

Table 3: Design Statistics

S.No.
1
1a
1b
1c
1d
1e
1f
1g
2
2a
2b
3
3a
3b

Cell
BELS
GND
LUT2
LUT3
LUT4
LUT5
LUT6
MUXF7
FLIP FLOPS/LACTHES
LD
LDCP
IO Buffers
IBUF
OBUF

Usage
840
1
9
101
82
180
431
36
7
5
2
193
129
64

Table 4: Power Consumption

S.no
1
2
3
4

Frequency
10 Mhz
50 Mhz
100 Mhz
200 Mhz

Static
379 mw
380 mw
382 mw
385 mw

Dynamic
24 mw
118 mw
235 mw
471 mw

Total
403mw
498 mw
617 mw
856 mw

V.
Conclusion
IEEE P754 compliant decimal floating point adder is successfully implemented on Virtex-5 device.
The design was tested with several test vectors and no errors are found, so the design is behaving correctly. We
have replaced the full adder of the BCD adder by a low power low delay full adder to reduce the power
consumption and the delay of the design. The design has a maximum combinational delay of 45 ns with the
latency of 1 clock cycle.
The low power low delay adder can be further used in the implementation of multiplier and divider
circuit and the complete floating point arithmetic and logic unit can be implemented on FPGA. This will reduce
the power consumption of the complete design. Further clock gating techniques can be used to reduce the clock
power.

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