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IC616Basics
OpenLibraryManager
ClickonTools>LibraryManager,tobringuptheLibrarymanagerwindow.
IntheLibrarymanagerwindow,youcanviewalistoflibrariesontheleft.
Clickonanyofthemtoviewthelistofcellsthatparticularlibrarycontains.
Thislistshowsupinthe'Cell'pane.
Eachoftheecellsmayalsohavemultipleviewssuchas'schematic','symboletc
Animageofthe'LibraryManager'windowisshowninthescreenshot

CreateNewLibrary
ClickonFile>NewLibrary..
Typeinthenameofthethelibrary(test123inthefigure).
Doubleclickthelibsfoldertoensurethatthenewlibraryisstoredinthe/home/username/work_cad_65nm/libs/folder
(thismakesforbetterorganization)
Youwillthengetawindow"TechnologyFilefornewlibrary".
Choose"Attachtoanexistingtechnologylibrary"asshowninthescreenshot
Clickon"OK"
Choose"umc65ll"asthetechnologylibraryinthenextwindow("Attachlibrarytotechnologylibrary")thatshowsup
Clickon"OK"

CreateSchematic
Nowwecancreatenewcellsinthislibrarywehavejustcreated.Wewillfirstmakeaninverterasourfirstcell.
GototheLibraryManagerwindow.
Ensurethatthelibraryyouhavecreatedishighlightedinthe"Library"paneontheleft.
ClickonFile>New>"CellView".Youwillgetawindowasshowninthefigure.
Ensurethatthelibrayynameiscorrect,andtheviewis"Schematic".
Enteracellnameofyourchoice.Herewehavecalledit"inv_65".

NOTEThiswillbringupasmallwindow(whendonefirsttime)askingifyouliketouseanalternativelicense.
ClickonAlways
Ifyouclickon"Never"bymistake,pleaserefertotheFAQbelowtofixtheissue

Thiswillbringuptheschematiceditorwindow.

Press'i'onthekeyboardtoinstantiateacell.
HerewewillfirstneedtoinstantiatetheNMOS,andPMOStransistors.
"AddInstance"windowpopsup.Browsetoselectthelibraryas"umc65ll".
ChoosetheNMOStransistortobe"N_12_LLHVT".EnsurethattheViewissetto"symbol".
Placethetransistorontheschematiceditorwindow.
Press'i'againtoinstantiatethePMOStransistor"P_12_LLHVT".
Press'w'toactivatethewiretool
Clickstartandendpointstodrawwirebetweenthem
Press'p'toaddaport
Addport"In"ofDirectionInput
Addport"Out"ofDirectionOutput
Addport"VDD"ofDirectionInputOutput
Addport"GND"ofDirectionInputOutput
Hit"Shift+x"toCheckandSavetheschematic
YoushouldNOTgetanyerrorsorwarnings
Asnapshotofthisinstantiationwindowisshownhere

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CreateSymbol
ClickonCreate>Cellview>FromCellview...
Ensurethat'ToViewName'is'Symbol'
Ensurethat'Tool/DataType'isSchematicSymbol'
ClickonOK

Thisopensthe'SymbolGenerationOptions'window
Movethe"GND"toBottomPins
ClickonOK

Usetoolbar(highlightedinthefigure)tocreateaneatsymbolofaninverter
Hit"Shift+x"toCheckandSavetheschematic
Againnoerrorsorwarningsareexpectedhere!
Asnapshotofthisisshownhere

CreateaTestbench
CreateaNewschematicinthecurrentlibrary(inv_65_tb)
Press"i"andinstantiatetheinverteryoujustcreated
Thisisdonebychoosingthelibrary(test123),Cell(inv_65)andView(Symbol)
Instantiateadcvoltagesource
library(analogLib),Cell(vdc)andView(Symbol)
Edititspropertiesbyselectingthedcvoltagesourceandpressing"q"
Setthefield"DCVoltage"to1V
LeavetheotherfieldsattheirdefaultvalueandClickOK
Instantiateapulsevoltagesource
library(analogLib),Cell(vpulse)andView(Symbol)
Edititspropertiesbyselectingthedcvoltagesourceandpressing"q"
Setthefields"Voltage1"to0V,"Voltage2"to1V,"Period"to10n,"Delaytime"to1n,"Risetime"to
100p,"Falltime"to100pand"Pulsewidth"to5n
LeavetheotherfieldsattheirdefaultvalueandClickOK
Instantiate"gnd"
library(analogLib),Cell(gnd)andView(Symbol)
Instantiate"NoConnection"
library(basic),Cell(noConn)andView(Symbol)
Maketheconnectionsasshowninthefigure
Labelnetsbypressing"l"asshowninthefigure
Hit"Shift+x"toCheckandSavetheschematic
Againnoerrorsorwarningsareexpectedhere!

Simulatingyourdesign
ClickonLaunch>ADEL
NOTEThiswillbringupasmallwindow(whendonefirsttime)askingifyouliketouseanalternativelicense.
ClickonAlways
Ifyouclickon"Never"bymistake,pleaserefertotheFAQbelowtofixtheissue
Inthe"ADEL"window,ClickonAnalyses>Choose...
Inthe"ChoosingAnalyses"window,Selectthe"tran"radiobutton(thisisselectedbydefault)
Set"StopTime"as100n
Select"Conservative"
ClickonOK
Inthe"ADEL"window,ClickonOutputs>ToBePlotted>SelectOnDesign
Thiswillcausetheschematiceditingwindow(ADEL)tobecomehighlighted
Clickonthenetstobeplotted(INandOUTinthiscase)
Inthe"ADEL"window,ClickonSimulation>NetlistandRun
Thiswillcausetheoutputwaveformstobeplottedasshowninthefigure

FirstAssignment
Pleasecreatea2pagereportofyouwork.
Submissionprocedurewillbeupdatedshortly!
1. CreateaInverterSchematicandSymbolasexplainedaboveandmeasurethedelaybetweeninputandoutput
Spendsometimeexploringthetool,thiswillhelpyouinfutureassignments.
2. CreateaChainof11invertersandmeasuredelaybetweeninputandoutput.
3. (Optional)Createaringoscillatorusingtheabovechainof11inverters.
Canyoumakethemoscillate?
Whatisthefrequencyofoscillation?
Canyoumeasurethepowerconsumption?

VirtualBox
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Downloadthevirtualboxfilehere

DVLSIAug2014FirstLabInstructionsMicrowiki
(accessiblewithincampusonly)!

LayoutSetup
FollowtheseinstructionstosetuplayouteditorandCalibreDRC,LVSandPEXflows
CopytherequiredfilesforthesmartloginofyourPC(testforDESELab)
cpr/home/smart/work_cad_65nm/Runsets~/work_cad_65nm/
cpr/home/smart/work_cad_65nm/.cdsinit~/work_cad_65nm/
cpr/home/smart/work_cad_65nm/.cdsenv~/work_cad_65nm/
cpr/home/smart/work_cad_65nm/calview.cellmap~/work_cad_65nm/

VirtualBoxuserssetup
[email protected]/folderstothecorrespondingdirectories
Passwordissameasusername"smart"
Tip:Youavoidtypingthepasswordrepeatedlybyinstallingsshpass"yuminstallsshpass"
[email protected]:work_cad_65nm/Runsets~/work_cad_65nm/
[email protected]:work_cad_65nm/.cdsinit~/work_cad_65nm/
[email protected]:work_cad_65nm/.cdsenv~/work_cad_65nm/
[email protected]:work_cad_65nm/calview.cellmap~/work_cad_65nm/
Becomerootonyourvirtualmachinebytypingthecommand"su"
Passwordwillbementionedinclass.
Thenexecutethefollowing4linesasroot
Youwillbepromptedforthepasswordsmartinthelast3lines

cd/opt/umc65nmll/G9FDLOGIC_MIXED_MODE65NLL_LOW_K_UMK65FDKLLC00000OAFDKVer.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC00000OA_B10/RuleDecks/Calib
[email protected]:/opt/umc65nmll/G9FDLOGIC_MIXED_MODE65NLL_LOW_K_UMK65FDKLLC00000OAFDKVer.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC00000OA_
[email protected]:/opt/umc65nmll/G9FDLOGIC_MIXED_MODE65NLL_LOW_K_UMK65FDKLLC00000OAFDKVer.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC00000OA_
[email protected]:/opt/umc65nmll/Documents/opt/umc65nmll/

VideoTutorialLinks
AVideotutorialisavailableinthreepartsat
Part1Transistorbasicviews 5:43
Part2LayoutofInverter,DRC,LVS,andPEX

31:59

RunDRCat18:00
RunLVSat24:34
RunPEXat28:34
Part3SimulatingwithPEX(Calibre)Netlist

2:29

Layouteditor(brief)BeginnerGuide(Notes)
Note:ToensurethattherearenowarningsafterPEXextraction,usecapitallettersforallport/pinnames(thereissomeissuewithourCalibrePEXextractionfloworthetoolitself).
Launch>LayoutXL
ReadthemessageandclickOK(twice)
Connectivity>generate>Allfromsource
SelectonlyInstances(Deselect"IOPins"and"PRBoundary")andClickOK
Hit"Shift+F"todisplayalllayers
Options>Display
Minimumgridspacingis5nm(looselyspeaking),sochangethesettingsaccordingly
Minorspacing0.005
Majorspacing0.05
XSnapSpacing0.005
YSnapSpacing0.005
PolylayeriscalledPO1
PMOStransistorsrequireaNTAP
useM1NWELLcontact
NMOStransistorsrequireaPTAP
useeitherM1PSUBorM1PACTIVEcontact
DuringPEXextractionatthe"CalibreViewSetup",selecttheradiobuttonsCalibreViewType:schematicCreateTerminals:CreateallterminalsDevicePlacement:Arrayed

QuickShortcuts
FitScreen

Viewlayersofinstances

Shift+f

Don'tshowlayersinsideinstances Ctrl+f
DrawRectangle

DrawVia/Contact

Drawlabel

l(Select_CADTEXlayer)

MoveObject

CopyObject

ScaleObject

Zoomin

Zoomout

Shift+z

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Ruler

k(rightclicktoeditpropertiesremovesnaptoedges)

ClearRuler

Shift+k

Pathtool

porShift+p(dependsonyourconfiguration)

Gravity

g(togglesONandOFF)

Documentation
Somehelpfuldocumentationcanbefoundinthefollowingfile(includingscreenshots)
Notethatourownsetupdiffersslightlyfromtheonedescribedinthedocumentsbelow:
UserGuide
/opt/umc65nmll/G9FDLOGIC_MIXED_MODE65NLL_LOW_K_UMK65FDKLLC00000OAFDKVer.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/doc/FDK_OA_User_Guide_V1_2.pdf
DRCRulesfile
/opt/umc65nmll/Documents/TLR/G03LOGIC_MIXED_MODE65NLLTLRVer.1.18_P1.pdf
Layerinformation
/opt/umc65nmll/Documents/Intercap/G04LOGIC_MIXED_MODE65NLOW_KINTERCAPVer.1.2_P1.pdf

RTLtoGDSflow
ThissectionwouldcoverthebasicsetofcommandsandthebackendtoolflowrequiredtosynthesizetheRTLandthentakeitthroughPnRtoarriveataGDS.

LogicSynthesis
SynthesisistheprocessbywhichabehaviouralRTLcodeisconvertedtoastructuralnetlist,withthespecifiedarea,powerandperformanceconstraints.Theinputstothesynthesisflow
aretheRTL,theconstraints(.sdcfile)andthetiminglibraries(.libfiles).WewouldbeusingCadenceRTLCompiler(RC)asoursynthesistool.
Firstly,ensurethatyou'reworkingincshell
tcsh
Createyourworkingdirectory.Forthisexample,wewillassumethatyourdesignnameis"counter"
mkdir~/counter_synthesis
cd~/counter_synthesis
Replacecounterwith<your_design_name>
Copytherequiredsetupfilesandscriptstoyourworkingdirectory
cprf~/synthesis_setup_files/*.
CreateadirectoryfortheRTLfiles
mkdirrtl
CopyyourRTLfile/filestothisdirectory
cp<pointertoyourrtlfile(s)>./rtl
Nowalltherequiredfilesarepresentinthecounter_synthesisdirectory.Let'sseewhatfilesarepresent
lsltr
Youshouldseethefollowingfilesanddirectories:setup.g,constraints_top.g,template.tcl,library,rtl
Setup.gisthebasicsetupfilewhichinitializesfewvariables.Weneedtoeditthisfile.We'llusevimeditortoeditfiles.Forverybasicvimcommands,pleaseseetheendofthissection.
Pleasesearchonlineifyouneedmorecommands.
vimsetup.g
Onlinenumber11,pleasespecifyyourrtlfiles.Thesefilesshouldbepresentinyourrtldirectory.Bydefault,thelinewouldlooklikethis
setFILE_LIST{mem.vtop.vmux_2to1.vphase_inc.v}
Changeitto
setFILE_LIST{<your_rtl_file_1.v><your_rtl_file_2.v>,etc..}
Onlinenumber16,youneedtospecifyyourtopmodulename.Bydefault,thelinewouldlooklikethis
setDESIGNtop

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Changeitto
setDESIGN<your_top_module_name>
Closethefilesetup.g
Next,openconstraints_top.g
vimconstraints_top.g
Thisfilecontainsthetimingconstraints.Line1specifiestheclock.Thedeafulttimeunitis1ns.Line1thusspecifiesaclockof100MHzwithadutycycleof50%.Wewouldbe
synthesizingthisdesignat100MHz.Lines3to5specifytheclocktransitionsandclockuncertainties.We'llkeepthemat1%and10%respectivelyforthisexample.Lines7to12specify
theinputtransitiontimesandline14specifiestheoutputtransitiontimes.We'llkeeptheseat10%forthisexample.
Thefollowingchangesneedtobedonetothisfile.
Changeline1as:
create_clocknameclkperiod10waveform{05}[get_ports"clk"]
Changeto
create_clocknameclkperiod10waveform{05}[get_ports"<your_clock_port_name>"]
Modifylines7to12as(addordeletelineswherevernecessary)
[get_ports"<your_input_port_names>"]
Modifyline14as(addordeletelineswherevernecessary)
[get_ports"<your_output_port_names>"]
Closeconstraints_top.g.Yoursetupisreadynow.
Next,wehavetoinitializeafewvariablesrelatedtocadencetools.Runthefollowingcommand.
source/home/smart/word_cad_65nm/cadence.cshrc
Next,invokeRTLCompiler
rcgui
Minimizetheguiandsourcethefollowingfilesintheterminal(rcshell)
rc:/>sourcesetup.g
rc:/>sourcetemplate.tcl(Thisisyourmainsynthesisscript)
Yourdesignshouldgetsynthesizedafterthisstepifeverythingwasdoneright.
Ifyouwanttoviewitonthegui,doubleclickonyourtopmodulename.YoucanexitRTLcompilernow
rc:/>exit
You'llfindthatthereareafewdirectorieswrittenoutinyourworkdirectory.Oneofthem,calledreports_<timestamp>,willhaveyoursynthesisreports.Youcangothroughthereportsto
seeafewmetricsofyourdesign,egtimingcharacteristics,area,power,gatecount.Alternately,youcanentercommandsinthercshellaftersynthesistoviewdetailedinformationabout
yourdesign.
Thedirectorycalledoutputs_<timestamp>,wouldhavetheoutputfilesaftersynthesis.<your_top_module_name.v>isthesynthesizednetlist.Youshouldhavealookatthisfile.Thisis
thenetlistthatwouldbetakenforwardforPnR.

PhysicalDesign
Theprocessofconvertinganetlistintomanufacturablegeometricalstructureshavingthedesiredfunctionalityandsatisfyingthevarioustiminganddesignruleconstraintscanbroadlybe
calledastheactivityofphysicaldesign.
Forthepurposesofthislab,wewouldgothroughtheverybasicvanillaflowtoconvertournetlisttoaGDS.Wewouldnotbedoinganytimingorphysicalverificationchecks.
PhysicalDesigncanbroadlybedividedintothefollowingsubtasks,whichare,inorder
Partitioning
Floorplanning
PowerPlanning
Placement
ClockTreeSynthesis(CTS)
Routing
PhysicalVerification
ParasiticExtractionandBackAnnotation
TimingAnalysis&Closure
DFM,DFYandTapeout
Wewouldgothroughthetoolflowofeachofthesestepswithoutgettingintotheoreticaldetails.PhysicalVerification,extractionandtiminganalysisisbeyondthescopeofthislab.

InitialSetup
Again,we'llassumethatthedesignnameiscounter.Createyourworkareaas:
mkdir~/counter_pd
cd~/counter_pd
Copytherequiredsetupfilesandthegeneratednetlistandsdcfromyoursynthesisworkarea
cprf~/pd_setup_files/*.

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cp~/counter_synthesis/outputs_<timestamp>/*.v.
cp~/counter_synthesis/outputs_<timestamp>/*.sdc.
Pleasechangetheabovetocopyfromyoursynthesisoutputdirectory
Yourworkdirectorywillnowhave5items:design.view,lib,lef,<your_design_name>.v,<your_design_name>.sdc
Opendesign.view
vimdesign.view
editline5tochangetop.sdcto<your_design_name>.sdc
Closethefile.
NowwearereadytolaunchourPnRtool,CadenceSoCEncounter.Butbeforethat,sourcethecadencecshrcfile.
source/home/smart/work_cad_65nm/cadence.cshrc
Invokeencounter
encounter
Wefirstneedtoloadtherequiredfiles
GotoFile>ImportDesign
Underthe"Verilog"tab,under"Files",enterthenameofyournetlist,<your_design_name>.v(orbrowseandselectthefile&clickadd)
Changethe"TopCell"to"Autoassign"
Underthe"Technology/PhysicalLibraries"tab,select"LEFFiles"
Browsetothelef/all.leffileandclickadd
Under"Power",enterVDDasthepowernetandVSSasthegroundnet
Under"AnalysisConfiguration",addthedesign.viewfileintheMMMCViewDefinitionFilesection.
ClickOK
YourDesignshouldgetinitializednow.
ClickontheFloorplanViewbutton,nexttoonlinehelp,onthetoprightcornerofthescreen.
Pressftofiteverythingonscreen.
Youshouldnowseeyourinitialsetupreadywiththestandardcellsshadedontheleftoftheestimatedfloorplan.

Floorplanning
ClickonFloorplan>Specifyfloorplan
ChangetheRatioto1
Changecoreutilizationto0.6
ChangeCoretoleft,coretoright,etc..(all4)to10
ClickOK
Youshouldnowseethesquarefloorplanwiththeareaassignedforpowerringsonyourscreen.

PowerPlanning
ClickonPower>Powerplanning>addring
Undernets,browseandselectbothVDDandVSS,clickadd,andclickOK.
Under"RingConfiguration",changeTopandBottomtoMetal5Horizontal;andLeftandRighttoMetal6Vertical
Changewidthandspacingto2undereachcolumn.
Under"offset",clickon"centreinchannel"
ClickOK
Youshouldnowseethepowerringsaroundthecorearea.
Next,weneedtoaddthepowerstripes.
ClickonPower>powerplanning>addstripe
SelectbothVDDandVSSundernets.
ChangethelayertoMetal6,anddirectiontoVertical.
Changewidthandspacingto2
Changesettosetdistanceto20
ClickOK.
Youshouldnowseetheverticalmetalstripesonyourscreen.
Wenowneedtoprovidepowertothestandardcellrailsbydroppingvias.
ClickonRoute>Specialroute
SelectVDDandVSSasnets
ClickOK

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ThestandardcellrailshavenowbeenprovidedwithVDDandVSS

Placement
ClickonPlace>Placestandardcell
ClickOK
Aftertheplacementruniscomplete,clickonPhysicalViewbuttonnextto"onlinehelp"onthetoprightcorner.
Yousouldnowseethestandardcellsplacedinyourdesign.

ClockTreeSynthesis
ClickOnClock>Synthesizeclocktree
Clickongenspec,andselectalltheclockbuffersandclockinvertersavailableinthelibrary.
(ieallcellsstartingwithCLK*)andclickADDandOK
ClickOK
Yourclocktreeshouldgetsynthesizedafterthisstep.

Routing
Clickonroute>nanoroute>route
ClickOK,leavingalloptionsasdefault
Thisshouldcompleteavanilladetailedrouterun.

FinalSteps
AddingfillercellsAnyunusedareainyourfloorplanmustbefilledupwithfillerstoensurewellcontinuityamongotherthings.Dothefollowingtoaddfillercells
Place>PhysicalCell>Addfiller
Selectallavailablefillercells
ClickOK
TimingcheckLetusseehowoursetupcheckslook.
Timing>reporttiming
Choosepostrouteunderdesignstage
Choose"setup"underanalysistype.
ClickOK
Checkthereportsontheterminal(ordetailedreportsinyourworkdirectory).Aswetargettedthedesignfor100MHz,whichisveryconservativeinthe180nmprocess,yourdesignshould
haveeasilymettiming.Inyourreports,thenumberofviolatingpaths(FEPs)andtheTNSshouldbezero.
TosaveyourpostPnRnetlist,dothefollowing
File>Save>Netlist
Nameyourfileas<your_design_name>_post_pnr.v
ToexporttheGDS,dothefollwoing
File>Save>GDS/OASIS
SelectGDSIIastheformat
Namethefileas<your_design_name>.gds
ClickOK
TheGDSshouldgetwrittenoutinyourworkingdirectory.
Youcantryoutotheroptions/commandswithencounter.
Finally,closeencounter
encounter1>exit

Acronyms
RTLRegisterTransferLogic
GDSGraphicalDatabaseSystem
PnRPlaceandRoute
SDCSynopsysDesignConstraints
libLibertyformat
RCCadenceRTLCompiler
CTSClockTreeSynthesis
DFMDesignforManufacturability
DFYDesignforyield
LEFLibraryExchangeFormat
FEPFailingEndPoints
WNSWorstNegativeSlack
TNSTotalNegativeSlack

Basicvimcommands
Openingafile
vim<filename>

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Vimhas2modes,commandmodeandinsertmode.Commandmodeiswhereyouentervimcommandsandinsertmodeiswhereyoutype.Bydefault,vimenterscommandmodeon
launch.Toenterinsertmode,pressi
i
Toreturntocommandmode,pressESC
ESC
Tosaveafile,incommandmode,type
:w!
Toquitwithoutsaving,incommandmode,type
:q!
Tosaveandquit,incommandmode,type
:wq!
Toviewlinenumbers,incommandmode,type
:senu

MonteCarloSimulations
Herearesomebasicpointerstorunningmontecarlosimulationsthatisusedtostudytheeffectofvariations.

ADEXLevironment
AsADELdoesnotsupportrunningMonteCarlosimulations,youwillhavetouseADEXL.
FirstgetacquiantedwiththeADEXLbyrunningasimpletransientsimulation
LaunchADEXLfromtheschematiceditingwindow
Launch>ADEXL
Select"CreateNewView"andclick"OK"
Selectappropriateoptionsinthenextwindow(defaultwilldo)andclick"OK"
Create>Test>setuptransientsimulationinADELasusual
"Outputssetup"tabselectonnotepad+penciliconto"setupplottingoptions"
PlottingoptionselectAutotoautomaticallyplotoutputs
Runthetransientsimulationbyhittinggreenarrowrunbutton

MonteCarlosimulation
ForMonteCarlo,select"MonteCarlosampling"inpulldownoptionswhichis"SingleRun,SweepandCorners"bydefault
GotoADELandselectthenewmodelandaddtheappropriatesectionnumber
Setup>ModelLibraries
Deleteexistinglines
Addthefile"/opt/umc65nmll/G9FDLOGIC_MIXED_MODE65NLL_LOW_K_UMK65FDKLLC00000OAFDK
Ver.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC00000OA_B10/Models/Spectre/Monte_Carlo/l65ll_v171_mc.lib.scs"withthesections"mc_ll_rvt12",
"mc_ll_lvt12",and"mc_ll_hvt12"asdemonstratedinlab.
Sothereshouldnowbe3linesinthelistwhichareenabled(haveatickmarkagainsttheirline).
InDataviewsubwindow,select"globalvariables">"clicktoaddvariable">addavariablecalled"sigma"withavalueof3thisisasrecommendedbyourfoundry
Selectsimulationoptionsnexttopulldownmenuandsetappropriatemontecarlooptions
Tick"Savedatatoallowfamilyplots"
Runusinggreenarrowbuttonandseethefamilyofcurves
Agoodtutorialwithscreenshotsisavailablehere .
CadencedocumentationforADEXLmaybefoundat"/opt/cadence/IC616/doc/adexl/adexl.pdf".
Thedocumentationforalltoolsisavailableat"/opt/cadence/IC616/doc/"explorethemtoimproveyourunderstandingofthetools.

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