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Flilop

The document describes a positive edge-triggered D flip-flop and an alternative design. 1) The D flip-flop uses two clock signals C1 and C2 that follow a fixed pattern due to gate delay. It latches the input D value on the positive clock edge when C1 changes from 1 to 0. 2) The alternative design uses an R-S latch. Its next state equations show that the output Q remains unchanged when the clock C is 0, and toggles depending on the input D value when C changes from 0 to 1. 3) Both designs ensure the output Q only changes on the positive clock edge, retaining the previous value at all other times to function as

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Govind Gopal
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© © All Rights Reserved
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137 views

Flilop

The document describes a positive edge-triggered D flip-flop and an alternative design. 1) The D flip-flop uses two clock signals C1 and C2 that follow a fixed pattern due to gate delay. It latches the input D value on the positive clock edge when C1 changes from 1 to 0. 2) The alternative design uses an R-S latch. Its next state equations show that the output Q remains unchanged when the clock C is 0, and toggles depending on the input D value when C changes from 0 to 1. 3) Both designs ensure the output Q only changes on the positive clock edge, retaining the previous value at all other times to function as

Uploaded by

Govind Gopal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

03/28/00

Yu Hen Hu

Positive Edge-Triggered D Flip-Flop Analysis


D

Clock
Q
C1

C2

Figure 1. Positive Edge-Triggered D Flip-flop

Depicted above is a positive edge-triggered D Flip-flop. To understand its operations,


note that the clock signals C1 and C2 will follow a fixed pattern:
C1, C2 = 01 11 10 00 01 11
When C1 changes from 0 to 1, due to the gate delay, C2 will first remain at 1, causing the
pattern of 11, and then will change its value to 0 accordingly, settling to the pattern of 10.
Also, note that the positive clock edge of the clock signal occurs during the transition of
C1, C2 from 10 00 01.
For the D-type clocked latch, whose next state value Y+ can be expressed as:
Y + = C1 D + C1 Y

(1)

For the slave stage clocked SR latch, the next state value Q+ can be expressed as:
Q+ = C 2 Y + C 2 Q

(2)

Now consider the following state transitions. Note that clock signals C1, C2 must follow
the specific patterns due to gate delay.
Clock
0
1
1
1

C1,C2
10
10
00
01

Y+
D1
D1
Y1
Y1

Q+
Q
Q
Q
Y1

0
0

01
11

Y1
D

Y1
Y1

10

Q1

Comments
Y captures D at postive clock edge
D latch off, Y holds steady
Q latch captures new values of Y, clock
remain at 1
trailing clock edge
D latch captures new input, Q latch still
latch on to previous Y
D may vary, but Q latch will not be
affected.

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03/28/00
Yu Hen Hu

Note that while clock = 0, C1,C2=10, the clocked D-latch is transparent to the input.
During the positive clock edge where clock changes from 0 to 1, C1 will change from 1
to 0 first, causing the D latch to latch on the input value at the positive clock edge. After
C1,C2 changes from 10 to 00, the D latch will no longer be affected by its input, so that
Y+ = Y. During all these times, the output Q remain unchanged as indicated by the
fourth column entries Q+ = Q. Next, C2 follows the change of C1 and will cause C1,C2
to change from 00 to 01. Only when this occurs, the latched input value Y will show up
as the output as indicated by Q+ = Y. Note that subsequently, the clock drops from 1 to 0
(a trailing clock edge), the D latch will remain unchanged (Y+ = Y) until C1 changes
back to 1 (C1,C2=11) so that the D-latch is ready to latch on the next input (Y+=D). At
the same time, Q+ = Y until C2 drops to 0 (C1,C2 change from 11 to 10).

Alternative Design of Positive Edge-triggered D Flipflop


A

C
R
Qb

B
D

Figure 2. Alternative design of positive edge-triggered D flipflop


To analyze this flipflop design, we write the (asynchronous) next state equations as
follows:
S + = (C A) = C + A = C + B S = C + ( D + R) S
R+ = S + C + B = S + C + R D
These equations lead to the following flow table where input variables are C, D, R, and S:

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03/28/00
Yu Hen Hu

C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

R
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

S
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

R+
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1

S+
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0

Comments
as long as C = 0, R = S = 1.
For the Rbar-Sbar latch to the right side
of the figure, this implies Q will remain
unchanged as long as clock C = 0.
If input D = 0, the circuit will settle for
a stable state C,D,R,S=0011
If input D = 1, the stable state is 0111
When C changes from 0 to 1, the state
transition may be 0011 1011 1001
or 01111111 1110. The former,
1001 will cause Q+ 0. The latter,
1110 will cause Q+ 1.
Two states, 1000, and 1100 can never be
reached as there are no combinations of
R+,S+ = 00.

Note that when C = 1, regardless D changes from 0 to 1 or 1 to 0, the R and S will remain
at 01 or 10. For example, 1010 1110 1010 all of them are stable states and RS =
10.
At the negative clock edge, that is from a state where C = 1 to a state where C = 0, we see
that R, and S will change to 11 regardless of their previous values or the D input values.

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