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Mixing SystemC and VHDL

This document discusses mixing SystemC and VHDL for simulation purposes. It describes how SystemC modules can be instantiated in VHDL and vice versa by binding ports and generics/parameters between the languages. While the basic concept is simple, properly handling data types, generics, and other language differences requires specific mechanisms. Mixed-language simulation is possible but not fully standardized. Consulting is offered for any SystemC-related needs.

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cristian_chitu
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© © All Rights Reserved
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206 views

Mixing SystemC and VHDL

This document discusses mixing SystemC and VHDL for simulation purposes. It describes how SystemC modules can be instantiated in VHDL and vice versa by binding ports and generics/parameters between the languages. While the basic concept is simple, properly handling data types, generics, and other language differences requires specific mechanisms. Mixed-language simulation is possible but not fully standardized. Consulting is offered for any SystemC-related needs.

Uploaded by

cristian_chitu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

S y s te m C a n d V H D L

Martin Radetzki
[email protected]
www.edacentrum.de

Mechanisms for Mixing Languages


electronic design automation centrum

Foreign Language Interface (FLI)


defined in VHDL, limited use, allows calling C functions
not a mechanism for coupling VHDL & SystemC simulation
Open Model Interface (OMI) IEEE Std. 1499
hardly available, and if available, doesnt work
Programming Language Interface (PLI)
gives access to simulator internals; difficult to use
Proprietary mechanisms, e.g. from verification add-ons
usually works fine, but ties you to that vendor
Mechanism to connect modules from different languages
as easy (?) as simulating VHDL and Verilog together
known as language co-simulation or mixed language simulation

Competence for EDA

SystemC / VHDL Mixed Language Simulation

Definition of Terms
electronic design automation centrum

Mixed Language Kernel

Co-Simulation
SystemC

VHDL

SystemC

.o .so .lib

.o .so .lib

work

SystemC
Kernel

VHDL
Simulator

Multiple simulator kernels


Communication overhead
Competence for EDA

VHDL

work

Mixed-Language
Single Kernel
Simulator

Single simulator kernel


Significantly smaller
overhead

SystemC / VHDL Mixed Language Simulation

Mixing SystemC and VHDL


electronic design automation centrum

SystemC in VHDL

VHDL in SystemC
SystemC Module

VHDL Entity / Architecture

VHDL

SystemC Module

Entity / Architecture
Configuration

Competence for EDA

Typical case
SystemC testbench
VHDL design under test

SystemC model
VHDL RTL not yet avail.
Higher level in VHDL

SystemC / VHDL Mixed Language Simulation

Mixed-Language Fundamentals
electronic design automation centrum

In principle, mixing VHDL and SystemC is easy


Both languages have modules with ports
Simply instantiate a module from one language using the other
languages instantiation syntax
The devil is in the details
The instantiated module is missing when compiling higher level
Languages provide different ports and data types
Parameter (generics) mechanisms are quite different
SystemC modules may use higher-level communication
This presentation shows how it works
Sample simulator: Modelsim 6.0

Competence for EDA

SystemC / VHDL Mixed Language Simulation

SystemC in VHDL

(in)out ports

Parameters

VHDL signals

SystemC Module
in ports

electronic design automation centrum

VHDL Entity / Architecture

Generic map

Competence for EDA

SystemC / VHDL Mixed Language Simulation

SystemC Module To Be Instantiated


electronic design automation centrum

comparator.h

comparator.cpp

SC_MODULE(Comparator)
{
// ports
sc_in<int>
in1, in2;
sc_out<bool> out1;

#include "comparator.h"

// process declaration
void action();
SC_CTOR(Comparator) {
SC_METHOD(action);
sensitive << in1
<< in2;
}
};
Competence for EDA

void Comparator::action()
{
out1 = false;
if (in1 > in2) {
out1 = true;
}
}
SC_MODULE_EXPORT(Comparator);

need to export every top


module of a SystemC
module hierarchy

SystemC / VHDL Mixed Language Simulation

Instantiation in VHDL
electronic design automation centrum

vgencomp Comparator

generates a VHDL component

component Comparator
VHDL stub / socket
port(
in1 : in std_logic_vector(31 downto 0);
in2 : in std_logic_vector(31 downto 0);
out1 : out std_logic
);
end component;
... - instantiation to be written by user
c1 : comparator port map(a, b, a_gt_b);
component
c2 : comparator port map(
instantiation
in1 => b,
in2 => c,
out1 => b_gt_c
);
c3 : comparator port map(c, a, out1 => c_gt_a);

Competence for EDA

SystemC / VHDL Mixed Language Simulation

Binding by Name
electronic design automation centrum

No configuration for instances of component Comparator


Instances are connected to a module
that has the same name as the configuration
that has port names and types matching the components ports
SystemC is case-sensitive
Comparator != comparator
VHDL is case-insensitive
Comparator = comparator
User manual: all names must match exactly (thats safe)
Practice: names match regardless of case
(but maybe not when using other tools)

Competence for EDA

SystemC / VHDL Mixed Language Simulation

Passing Parameters from VHDL to SystemC


electronic design automation centrum

Currently requires use of a workaround flow


Generation of stub entity for the SystemC module
Option 1: Automatic generation
Option 2: Manual generation
SystemC module constructor must obtain generic values
through specific function calls, to be applied in the same
order as the generics appear in VHDL:
int
generic_int = sc_get_int_param("int_generic");
float generic_real = sc_get_real_param("real_generic");
bool generic_bool = sc_get_bool_param("bool_generic");

functions exist for


further types
Competence for EDA

generic names as in
VHDL stub entity

SystemC / VHDL Mixed Language Simulation

10

VHDL in SystemC

(in)out ports

Generics

SystemC signals

VHDL Entity
in ports

electronic design automation centrum

SystemC Module

Constructor call

Competence for EDA

SystemC / VHDL Mixed Language Simulation

11

Foreign Module Declaration


electronic design automation centrum

entity sorter is
port(
a : in std_logic_vector(31 downto
b : in std_logic_vector(31 downto
c : in std_logic_vector(31 downto
biggest : out std_logic_vector(31
end;

VHDL entity to instantiate


0);
0);
0);
downto 0) );

scgenmod sorter

simulator command

class Sorter : public sc_foreign_module


{
public:
sc_in<sc_lv<32> > a;
sc_in<sc_lv<32> > b;
sc_in<sc_lv<32> > c;
sc_out<sc_lv<32> > biggest;

SystemC stub

Sorter(sc_module_name nm, const char* hdl_name)


: sc_foreign_module(nm, hdl_name), a("a"), b("b"), c("c"), ...
{}
};
Competence for EDA

SystemC / VHDL Mixed Language Simulation

12

VHDL in SystemC Instantiation


electronic design automation centrum

#include "sorter.h"
SystemC stub
...
SC_MODULE( testbench )
{
// signals to wire up the device under test
sc_signal<sc_lv<32> > asig, bsig, csig, fsig;
...
instantiation
Sorter dut;
...
SC_CTOR( testbench ) : ...,
initialization with
dut( "dut", "sorter" )
additional parameter
{
...
dut.a(asig);
port / signal
dut.b(bsig);
dut.c(csig);
connection
dut.biggest(fsig);
...

Competence for EDA

SystemC / VHDL Mixed Language Simulation

13

Passing Parameters from SystemC to VHDL


electronic design automation centrum

class Sorter : public sc_foreign_module


{
public:
...
Sorter(sc_module_name nm,
const char* hdl_name,
int num_generics,
const char* generic_list)
: sc_foreign_module(nm, hdl_name,
num_generics, generic_list),
a("a"), b("b"), c("c"), ...
{}

Additional stub
constructor parameters
to pass generic values

Pass values on to
SystemC foreign
module class

Sorter dut; // class member


VHDL generic
Call constructor
...
names
with generic_list;
// in class constructor
requires dynamic
const char *generic_list[3];
instantiation
generic_list[0] = strdup("int_generic=7");
generic_list[1] = strdup("real_generic=1.5");
generic_list[2] = strdup("bool_generic=false");
dut = new Sorter("dut", "sorter", 3, generic_list);
Competence for EDA

SystemC / VHDL Mixed Language Simulation

14

Compatible SystemC and VHDL Ports


electronic design automation centrum

SystemC port

VHDL port

sc_in<T>
sc_out<T>
sc_inout<T>

in
out / buffer
inout

sc_in_resolved
sc_out_resolved
sc_inout_resolved
sc_in_rv<N>
sc_out_rv<N>
sc_inout_rv<N>
sc_in_clk
sc_out_clk
sc_inout_clk

in std_logic
out std_logic
inout std_logic
in std_logic_vector(N-1 downto 0)
out std_logic_vector(N-1 downto 0)
inout std_logic_vector( ... )
in boolean / bit / std_[u]logic
out boolean / bit / std_[u]logic
inout boolean / bit / std_[u]logic

VHDL type depends


on T - see next slide

other port types are not supported on the language boundary


Competence for EDA

SystemC / VHDL Mixed Language Simulation

15

Compatible SystemC and VHDL Data Types


electronic design automation centrum

SystemC type T

VHDL type

bool / sc_bit
sc_logic

boolean / bit / std_[u]logic


std_[u]logic

sc_bv<N>
sc_lv<N>

bit_vector(N-1 downto 0)
std_[u]logic_vector(N-1
downto 0)

sc_[u]int<N>
[unsigned] char
[unsigned] int
[unsigned] long

bit_vector(N-1 downto 0)
std_[u]logic_vector(N-1
downto 0)

other data types are not supported on the language boundary


Competence for EDA

SystemC / VHDL Mixed Language Simulation

16

VHDL to SystemC Logic Value Mapping


electronic design automation centrum

std_logic

sc_logic

sc_bit

bool

0
L

0
0

0
0

false
false

1
H

1
1

1
1

true
true

false

U
W
X
-

X
X
X
X

0
0
0
0

false
false
false
false

no logic values are lost when mapping from SystemC to VHDL


Competence for EDA

SystemC / VHDL Mixed Language Simulation

17

Conclusion
electronic design automation centrum

Mixed-language simulation for SystemC and VHDL ...

works
uses mechanisms similar to mixed VHDL / Verilog simulation
is fairly simple as long as no generics / parameters involved
employs some mechanisms that are not standardized

If you need consulting on whatever aspects of SystemC ...


talk to us today
contact [email protected] later

Competence for EDA

SystemC / VHDL Mixed Language Simulation

18

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