VHDL Tutorial
VHDL Tutorial
1.1 Introduction
The VHSIC Hardware Description Language is an industry standard language used to
describe hardware from the abstract to the concrete level. VHDL resulted from work
done in the '70s and early '80s by the U.S. Department of Defense. VHDL usage has
risen rapidly since its inception and Is used by literally tens of thousands of
engineers around the globe to create sophisticated electronic products, This chapter
will start the process of easing the reader into the complexities of VHDL. VHDL is a
powerful language with numerous language constructs that are capable of
describing, very complex behavior. Learning all the features of VHDL is not a simple
task. In 1986, VHDL was proposed as an IEEEstandard. It went through a number of
revisions and changes until it was adopted as the IEEE 1076 standard in December
1987, Then VHDL 1076-1993 and the latest VHDL 1076-2002. All the examples have
been described in IEEE 1076 VHDL.
Entity D_flip is
Port (D, CLK, S, R : in std_logic;
Q, Qnot : out std_logic);
End D_flip;
1.3.2 Architecture Body
An entity or circuit can be specified in a variety of ways, such as behavioral,
structural, or a combination of both. The architecture body looks as follows:
Architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- Components declarations
-- Signal declarations
-- Constant declarations
-- Type declarations
.
.
Begin
-- Statements
.
.
End architecture_name;
1.3.3 Library & Packages
A library can be considered as a place where the compiler stores information about
a design project, and a VHDL package is a file or module that contains declarations
of commonly used objects, data type, component declarations, signal, procedures
and functions.
To specify the library and package, use the "library" and the "Use" keywords.
For example to include the std_logic_1164 package that exists in the library IEEE
library IEEE;
Use IEEE.std_logic_1164.all;
The .all extension indicates to use the entire ieee.std_logic_1164 package.
Sequential
Entity XNOR2 is
Port (A, B: in std_logic;
Z: out std_logic);
End XNOR2;
Architecture sequential of XNOR2 is
Begin
XNOR2 : Process (A,B)
Begin
If ((A = '0' and B= '0') I (A = '1' and B= '1'))
then
Z<= '1 ;
Else
Z <='0';
End if;
End process xNOR2;
End sequential;
Case Statement
The case statement executes one of several sequences of statements, based on the
value of a single expression, the syntax is as follows:
Case expression is
When choices =>
Sequential statements
When choices =>
Sequential statements
[When others =>
Sequential statements )
End case;
The case statement evaluates the expression and compares the value to each of the
choices, the when clause corresponding to the matching choice will have its
statements executed, there is no two choices can overlap (i.e. each choice can be
covered only once). If the "when others" choice is not present, all possible values of
the expression must be covered by the set of choices.
loop Statements
The loop statements are used to repeatedly execute a sequence of sequential
statements, iteration schemes defined by the VHDL:
Basic-loop
While-Loop
For-Loop
[loop label:] Iteration scheme loop
Wait Statement
Sequential statements
[Next [label] [when condition];
[Exit [label] [when condition];
End loop [loop_label];
This loop has no iteration scheme. It will be executed continuously until it
encounters an exit or next statement, the basic loop (as well as the while-loop) must
have at least one wait statement. The next statement terminates the rest of the
current loop iteration and execution will proceed to the next loop iteration, while
the exit statement skips the rest of the statements, terminating the loop entirely,
and continues with the next statement after the exited loop.
Example
entity COUNT31 is
Port (CLK : in std_logic;
COUNT : out integer);
End COUNT31;
The component name refers to either the name of an entity defined in a library or
an entity explicitly defined in the VHDL file (see example). If the component is
declared in the package, no need to declare it in the architecture.
Component Instantiation
The component instantiation statement initiates an instance of the component
already defined, the syntax is as follows:
Instance name: component name
Port map (signal1, signaI2, ...,signaln);
The instance name is the name of this particular instance. While the component
name is the name of the component declared earlier using the component
declaration statement, and the signal name is the name of the signal to which the
specific port is connected.
The first port in the component declaration corresponds to the first signal (signal1),
the second port to the second signal (signaI2), etc. The signal position must be in the
same order as the declared component's ports.
The order or precedence is the highest [or the operators of class 7, and lowest for class1.
Unless parentheses are used, the operators with the highest precedence are applied
first. Operators of the same class have the same precedence and are applied from left to
right in an expression.
1.8.1 logical Operators
The logic operators (and, or, nand, nor, xor and xnor) are defined for the "bit",
"boolean", "std_logic" and "std_ulogic" types and their vectors. They give a result of the
same type as the operand (Bit or Boolean). These operators can be applied to signals,
variables and constants. Nand and nor operators are not associative. One should use
parentheses to prevent a syntax error:
The relational operators test the relative values of two types and give a result as Boolean
output of "TRUE" or "FALSE", For discrete array types, the comparison is done on an
element-per-element basis, starting from the left towards the right.
1.8.3 Shift Operators
The unary operators "+ and "-" are used to specify the sign of a numeric type.
Examples:
11 rem 4 results in 3
(-11) rem 4 results in -3
9 mod 4 results in 1
7 mod (-4) results in -1(7 - 4*2 = -1).
1.8.7 Miscellaneous Operators
Absolute value and exponentiation operators can be applied to numeric types. Logical
negation (not) results in the inverse polarity but the same type.
Karnaugh Map:
"Sum" Map
Karnaugh Maps:
"J0" Map
"K0" Map
"J1" Map
"K1" Map
"J2" Map
"K2" Map
end process;
q<=q_int;
end behavelikethis
2.2.1.7 VHDL Structural Code of the JK Flip-Flops Counter
library ieee;
use ieee.std_logic_1164.all;
Entity jkcount is
Port (clk: in std_logic;
q0,q1,q2:out std_logic);
end jkcount
Architecture Structural of jkcount is
signal q0int,q1int,q2int,q1i,q2i,j0,k0,j1,k1,j2,k2 : std_logic := '0';
Component invert is
Port (a : in std_logic;
b:out std_logic);
end Component
Component and2i is
Port (a,b : in std_logic;
c:out std_logic);
end Component
Component or2i is
Port (a,b : in std_logic;
c.out std_logic);
end Component
Component jkff is
Port (j,k,clk : in std_logic;
q:out std_logic);
end Component
begin
inv0: invert
port map (q1int,q1i)
inv1 : invert
port map(q2int,q2i)
and0 : and2i
port map(q0int,q1int,j2)
or0: or2i
port map(q1i,q2i,j0)
or1 : or2i
port map(q0int,q2int,k1)
jk0 : jkff
port map(j0,l,clk,q0int)
jk1 : jkff
port map(q0int,k1,clk,q1int)
jk2 : jkff
port map(j2,q1int,cIk,q2int)
q0 <= q0int;
q1 <= q1int;
q2 <= q2int;
end Structural