SECOND EDITION ARM ASSEMBLY | PANE ele ie Fundamentals and arealCRE Press. ‘Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2015 by William Hohl and Christopher Hinds CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed on acid-free paper Version Date: 20140915 International Standard Book Number-13:978-1-4822-2985-1 (Hardback) This book contains information obtained feom authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmit- ted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright. com (http:/www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and, registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. ‘Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used. only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Hohl, William ARM assembly language : fundamentals and techniques / William Hohl and Christopher Hinds. -- Second edition. pages cm Includes bibliographical references and index. ISBN 978-1-4822-2985-1 (hardback) 1, Assembly languages (Electronic computers) 2. Embedded computer systems--Programming, I. Hinds, Christopher. Il. Title. (QA76.73.A8H637 2014 006.2°2--de23 2014024230 Visit the Taylor & Francis Web hetp://www.taylorandfrancis.com and the CRC Press Web site at http:/www.crepress.comContents Preface... Pirate crecessesnrvensnscusnonete Chapter 1 An Overview of Computing Systems... 1.3 14 15 1.6 17 18 Chapter 2. The Programmer's Model ppp bo 2.5 XV oe XXH Introduction .. History of RISC. 1.2.1 ARM Begins... 1.2.2. The Creation of ARM Ltd. 1.2.3 ARM Today 1.2.4 The Cortex Family... ss cae 1.24.1 The Cortex-A and Corte R Families.noun. 10 1.2.4.2 The Cortex-M Family The Computing Device...... Number Systems... Representations of Numbers and Character 1.5.1 Integer Representations 1.5.2. Floating-Point Representations 1.5.3 Character Representations.. Translating Bits to Commands... The Tools. 1.7.1 Open Source Too 1.7.2 Keil (ARM) 1.7.3. Code Composer Studio.... 1.7.4 Useful Documentation. Exercises Introduction Data Types... ARM7TDMI 2.3.1 Processor Modes 2.3.2 Registers... 2.3.3. The Vector Table .. Cortex-M4. _ 2.4.1 Processor Modes... 2.4.2. Registers. 24.3. The Vector Table Exercises... viiviii Chapter 3 Chapter 4 Introduction to Instruction Sets: v4T and v7-M 3.1 3.2 3.3 Assembler Rules and Directives... 4.1 42 43 44 47 Contents Introduction .. ARM, Thumb, and Thumb-2 Instructions Program 1: Shifting Data.. 3.3.1 Running the Code. 3.3.2 Examining Register and Memory Contents.. Program 2: Factorial Calculation Program 3: Swapping Register Contents, Program 4: Playing with Floating-Point Number Program 5: Moving Values between Integer and Floating- Point Registers... Programming Guidelines Exercises.... Introduction .. Structure of Assembly Language Modules Predefined Register Names .... Frequently Used Directives 44.1 Defining a Block of Data or Code 44.1.1 Keil Tools... 2 Code Composer Studio Tool: 4.4.2 Register Name Definition 4.4.2.1 Keil Tools.. 4.4.2.2 Code Composer Studio 4.4.3. Equating a Symbol to a Numeric Constant z 1 Keil Tools... 2 Code Composer Studio 4.4.4 Declaring an Entry Point 4.4.5. Allocating Memory and Specifying Contents 44.5.1 Keil Tools.. 44.5.2 Code Composer Studio 4.4.6 Aligning Data or Code to Appropr 4.4.6.1 Keil Tools.. 4.4.6.2 Code Composer Studio. 44.7 Reserving a Block of Memory Keil Tools... i 4. 4.4.8 Assigning Literal Pool Origins 4.4.9 Ending a Source File Macros... Miscellaneous Assembler Features 4.6.1 Assembler Operators 4.6.2. Math Functions in CCS ExercisesContents Chapter 5 Chapter 6 Chapter 7 Loads, Stores, and Addressing . 5.1 Introduction 5.2. Memory. 5.3 Loads and Stores: The Instructions. 5.4 Operand Addressing... 5.4.1 Pre-Indexed Addressing . 5.4.2 Post-Indexed Addressing 5.5 Endianness. 5.5.1 Changing Endiannes 5.5.2 Defining Memory Areas 5.6 Bit-Banded Memory... 5.7 Memory Considerations 5.8 Exercises Constants and Literal Pools......... 6.1 Introduction 6.2 The ARM Rotation Scheme .. 6.3 Loading Constants into Registers. 6.4 Loading Constants with MOVW, MOVT . 6.5 Loading Addresses into Registers 6.6 Exercises... 9s a 1S 119 Integer Logic and Arithmetic...... 7.1 Introduction ... 7.2 Flags and Their Us 7.2.1 The N Flas 7.2.2 The V Flag 121 723 122 724 123 7.3 Comparison Instructions 7.4 Data Processing Operation: 7.4.1 Boolean Operation: 7.4.2 Shifts and Rotates. 7.4.3. Addition/Subtraction 7.4.4 — Saturated Math Operations 7.4.5 Multiplication... 7.4.6 Multiplication by a Constant. 74.7 _ Division... 7.5 DSP Extensions 76 Bit Manipulation Instructions 7.7 Fractional Notation 7.8 ExercisesChapter 8 Branches and Loops Chapter 9 Contents 8.1 Introduction 8.2 Branching .. 8.2.1 Branching (ARM7TDMI 8.2.2. Version 7-M Branches. 8.3. Looping... 8.3.1 While Loops 8.3.2 For Loops 8.3.3 Do-While Loops. 8.4 Conditional Execution...... 8.4.1 v4T Conditional Execution. 8.4.2. v7-M Conditional Execution: 8.5. Straight-Line Codin; 8.6 Exercises... Introduction to Floating-Point: Basics, Data Types, and Data Transfer... .. 175 175 175 9.1 Introduction .. 9.2 A Brief History of Floating-Point in Computing . 9.3 The Contribution of Floating-Point to the Embedded Processor 178 9.4 Floating-Point Data Types 180 9.5 The Space of Floating-Point Repesenabl Valu .. 183 9.6 Floating-Point Representable Values... 9.6.1 Normal Values... 9.6.2 Subnormal Values 9.6.3 Zeros. 9.6.4 Infinitie: 9.6.5 Not-a-Numbers (NaNs) 9.7 The Floating-Point Register File of the Cortex-M4. 192 9.8 — FPU Control Registers... 193 9.8.1 The Floating-Point Status and Control Register, FPSCR... 193 9.8.1.1 The Control and Mode Bit 194 The Exception Bi 195 9.8.2 The Coprocessor Access Control Register, CPACR 9.9 Loading Data into Floating-Point Registers 9.9.1 Floating-Point Loads and Stores: The Instructions... 9.9.2| The VMOV instruction 6 9.10 Conversions between Half-Precision and Single-Pre 9.11 Conversions to Non-Floating-Point Formats. 9.11.1 Conversions between Integer and Floating-Point.Contents xi 9.11.2. Conversions between Fixed-Point and Floating-Point 9.12 Exercises. Chapter 10 Introduction to Floating-Point: Rounding and Exceptions...... 10.1 Introduction 10.2. Rounding .. 10.2.1 Introduction to Rounding Modes in the IEEE 754-2008 Specification... 10.2.2. The roundTiesToEven (RNE) Rounding Mode. 10.2.3 The Directed Rounding Modes a 10.2.3.1 The roundTowardPositive (RP) Rounding Mod. 10.2.3.2. The roundTowardNegative (RM) Rounding Mode....... . 10.2.3.3 The roundTowardZero (RZ) Rounding Mode. . i 10.2.4 Rounding Mode Summary 10.3 Exceptions... 10.3.1 Introduction to Floating-Point Exception 10.3.2. Exception Handling.. . 10.3.3 Division by Zero 10.3.4 Invalid Operation 10.3.5. Overflow... 10.3.6 Underflow 10.3.7 Inexact Result... 10.4 Algebraic Laws and Floating-Point. 10.5 Normalization and Cancelation... 10.6 Exercises Chapter 11 Floating-Point Data-Processing Instructions 11.1 Introduction .. so 11.2. Floating-Point Data-Processing Instruction Syntax 11.3. Instruction Summar} 11.4 Flags and Their Use....... 11.4.1 Comparison Instructions 11.4.2 The N Fla; 11.4.3 11.4.4 11.4.5 11.4.6 Predicated Instructions, or the Use of the Flags 11.4.7 A Word about the IT Instruction 11.5. Two Special Mode: 11.5.1 Flush-to-Zero ModeChapter 12 Tables. Chapter 13 Subroutines and Stacks... Chapter 14 Exception Handling: ARM7TDMI..... Contents 11.5.2 Default NaN 11.6 Non-Arithmetic Instructions 11.6.1 Absolute Value .... 11.6.2. Negat 11.7. Arithmetic Instructions 11.7.1 Addition/Subtraction 11.7.2. Multiplication and Multiply—Accumulate 11.7.2.1 Multiplication and Negate Multiplication. 1.7.2.2. Chained Multiply. Acoust 11.7.2.3. Fused Multiply-Accumulate.... 11.7.3. Division and Square Root. 11.8 Putting It All Together: A Coding Exampl 11.9. Exercises. 12.1 Introduction .. 12.2. Integer Lookup Tables... 12.3. Floating-Point Lookup Table: 12.4 Binary Searches 12.5 Exercises....... 13.1 Introduction ... 13.2 The Stack... 13.2.1 LDM/STM Instruction: 13.2.2. PUSH and POP. 13.2.3 Full/Empty Ascending/Des 13.3. Subroutines... 13.4 Passing Parameters to Subroutines........ 13.4.1 Passing Parameters in Registers 13.4.2. Passing Parameters by Reference: 13.4.3 Passing Parameters on the Stack 13.5) The ARM APCS esses 13.6 Exercises... 14.1 Introduction 14.2 Interrupts 14.3 Error Conditions... 14.4. Processor Exception Sequence. 14.5 The Vector Table. 14.6 Exception HandlerContents xiii 14.7 Exception Prioritie 14.8 Procedures for Handling Exception: 14.8.1 Reset Exceptions .. 14.8.2. Undefined Instructions 14.8.3. Interrupts... 14.8.3.1 Vectored Interrupt Controtle 14.8.3.2. More Advanced VICs 14.8.4 Aborts.. 14.8.4.1 Prefetch Aborts 14.8.4.2 Data Aborts... 5 SVC 14.9 Exercises... Chapter 15. Exception Handling: v7-M..... Introduction .. . Operation Modes and Privilege Levels The Vector Table .. ; Stack Pointers . Processor Brenton Sequence. 15.5.1 Entry. Exception Types .. Chapter 16 Memory-Mapped Peripherals... 16.1 Introduction ... The Memory Map Configuring the UART.... Writing the Data to the UART Putting the Code Togethel Running the Code. ‘The Memory Map Configuring the D/A Converter. Generating a Sine Wave .. Putting the Code Togethe Running the Code. 16.4 The Tiva Launchpad... 16.4.1 General-Purpose /O 16.4.2. The Memory MapChapter 17 Chapter 18 Contents 16.4.3 Configuring the GPIO Pins 16.4.4 Turning on the LEDs.... 16.4.5. Putting the Code Togethe 16.4.6 Running the Code 16.5. Exercises... ARM, Thumb and Thumb-2 Instructions........... 17.1 Introduction... — 17.2. ARM and 16-Bit Thumb Instructions " 17.2.1 Differences between ARM and 16-Bit Thumb 17.2.2. Thumb Implementation. 17.3. 32-Bit Thumb Instructions .. 17.4 Switching between ARM sand Thumb Seates. 17.5 How to Compile for Thumb .. . 17.6 Exercises... Mixing C and Assembly. 18.1 Introduction 18.2 Inline Assembler... 18.2.1 Inline Assembly Syntax. : 18.2.2. Restrictions on Inline Assembly Operations... 18.3. Embedded Assembler. 18.3.1 Embedded Assembly Syntax... 18.3.2 Restrictions on Embedded Assembly Operations. 387 18.4 Calling between C and Assembly ... 18.5 Exercises Appendix A: Running Code Composer Studi 393 Appendix B: Running Keil To0}s..........0.00:0nesnsnennnnnninnennannnnnse 399 Appendix C: ASCII Character Codes .... 407 ‘Appendix D.... 409 Glossary .. References. Index,a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.Authors William Hohl held the position of Worldwide University Relations Manager for ARM, based in Austin, Texas, for 10 years, He was with ARM for nearly 15 years and began as a principal design engineer to help build the ARM1020 microproces- sor. His travel and university lectures have taken him to over 40 countries on 5 continents, and he continues to lecture on low-power microcontrollers and assembly language programming. In addition to his engineering duties, he also held an adjunct faculty position in Austin from 1998 to 2004, teaching undergraduate mathematics. Before joining ARM, he worked at Motorola (now Freescale Semiconductor) in the ColdFire and 68040 design groups and at Texas Instruments as an applications engi- neer. He holds MSEE and BSEE degrees from Texas A&M University as well as six patents in the field of debug architectures. Christopher Hinds has worked in the microprocessor design field for over 25 years, holding design positions at Motorola (now Freescale Semiconductor), AMD, and ARM. While at ARM he was the primary author of the ARM VEP floating-point architecture and led the design of the ARM10 VFP, the first hardware implementa- tion of the new architecture, Most recently he has joined the Patents Group in ARM, identifying patentable inventions within the company and assisting in patent litiga~ tion. Hinds is a named inventor on over 30 US patents in the areas of floating-point implementation, instruction set design, and circuit design. He holds BSEE and MSEE degrees from Texas A&M University and an MDiv from Oral Roberts University, where he worked to establish the School of Engineering, creating and teaching the first digital logic and microprocessor courses. He has numerous published papers and presentations on the floating-point architecture of ARM processors. xxia You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.An Overview of Computing Systems 7 1.2.2 THe Creation or ARM Lr. In 1989, the dominant desktop architectures, the 68000 family from Motorola and the x86 family from Intel, were beginning to integrate memory management units, caches, and floating-point units on board the processor, and clock rates were going up—25 MHz in the case of the first 68040. (This is somewhat misleading, as this processor used quadrature clocks, meaning clocks that are derived from overlapping phases of two skewed clocks, so internally it was running at twice that frequency.) To compete in this space, the ARM3 was developed, complete with a 4K unified cache, also running at 25 MHz. By this point, Acorn was struggling with the dominance of the IBM PC in the market, but continued to find sales in education, specialist, and hobbyist markets. VLSI Technology, however, managed to find other companies will- ing to use the ARM processor in their designs, especially as an embedded processor, and just coincidentally, a company known mostly for its personal computers, Apple. was looking to enter the completely new field of personal digital assistants (PDAS). Apple’s interest in a processor for its new device led to the creation of an entirely separate company to develop it, with Apple and Acorn Group each holding a stake, and Robin Saxby (now Sir Robin Saxby) being appointed as managing director. The new company, consisting of money from Apple, twelve Acorn engineers, and free tools from VLSI Technology, moved into a new building, changed the name of the architecture from Acorn RISC Machine to Advanced RISC Machine, and developed a completely new business model. Rather than selling the processors, Advanced RISC Machines Ltd. would sell the rights to manufacture its processors to other companies, and in 1990, VLSI Technology would become the first licensee. Work began in earnest to produce a design that could act as either a standalone processor or a macrocell for larger designs, where the licensees could then add their own logic to the processor core. After making architectural extensions, the numbering skipped a few beats and moved on to the ARM6 (this was more of a marketing decision than anything else). Like its competition, this processor now included 32-bit addressing and supported both big- and little-endian memory formats. The CPU used by Apple was called the ARM610, complete with the ARM6 core, a 4K cache, a write buf- fer, and an MMU. Ironically, the Apple PDA (known as the Newton) was slightly ahead of its time and did quite poorly in the market, partly because of its price and partly because of its size. It wouldn't be until the late 1990s that Apple would design a device based on an ARM7 processor that would fundamentally change the way people viewed digital media—the iPod. The ARM7 processor is where this book begins. Introduced in 1993, the design was used by Acorn for a new line of computers and by Psion for a new line of PDAs, but it still lacked some of the features that would prove to be huge selling points for its successor—the ARM7TDMI, shown in Figure 1.4. While it’s difficult to imag- ine building a system today without the ability to examine the processor’s registers the memory system, your C++ source code, and the state of the processor all in a nice graphical interface, historically, debugging a part was often very difficult and involved adding large amounts of extra hardware to a system. The ARM7TDMI expanded the original ARM7 design to include new hardware specifically for an external debugger (the initials “D” and “I” stood for Debug and ICE, or In-Circuita You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.An Overview of Computing Systems " to support large operating systems, such as Linux, Android, and Windows. At the high end of the computing spectrum, these processors are also likely to support sy tems containing multiple cores, such as those found in servers and wireless base st tions, where you may need up to eight processors at once. The 32-bit Cortex-A family includes the Cortex-A5, A7, A8, A9, Al2, and A15 cores. Newer, 64-bit architectures include the A57 and A53 processors. In many designs, equipment manufacturers build custom solutions and do not use off-the-shelf SoCs; however, there are quite a few commereial parts from the various silicon vendors, such as Freescale’s i.MX line based around the Cortex-A8 and A9; TI’s Davinci and Sitara lines based on the ARM9 and Cortex-A8; Atmel’s SAMASD3 products based on the Cortex-A5; and the OMAP and Keystone multi-core solutions from TI based on the Cortex-A15. Most importantly, there are very inexpensive evaluation modules for which students and instructors can write and test code, such as the Beaglebone Black board, which uses the Cortex-A8. The Cortex-R cores (R4, R5, and R7) are designed for those applications where real-time and/or safety constraints play a major role; for example, imagine an embed- ded processor designed within an anti-lock brake system for automotive use. When the driver presses on the brake pedal, the system is expected to have completely deterministic behavior—there should be no guessing as to how many cycles it might take for the processor to acknowledge the fact that the brake pedal has been pressed! In complex systems, a simple operation like loading multiple registers can introduce unpredictable delays if the caches are turned on and an interrupt comes in at the just the wrong time. Safety also plays a role when considering what might happen if a fails or becomes corrupted in some way, and the solution involves build- ing redundant systems with more than one processor. X-ray machines, CT scan- ners, pacemakers, and other medical devices might have similar requirements. These cores are also likely to be asked to work with operating systems, large memory systems, and a wide variety of peripherals and interfaces, such as Bluetooth, USB, and Ethernet. Oddly enough, there are only a handful of commercial offerings right now, along with their evaluation platforms, such as TMS570 and RM4 lines from TI. 1.2.4.2, The Cortex-M Family Finally, the Cortex-M line is targeted specifically at the world of microcontrollers, parts which are so deeply embedded in systems that they often go unnoticed. Within this family are the Cortex-M0, M0+, MI, M3, and M4 cores, which the silicon ven- dors then take and use to build their own brand of off-the-shelf controllers. As the much older, 8-bit microcontroller space moves into 32-bit processing, for controlling car seats, displays, power monitoring, remote sensors, and industrial robotics, indus- try requires a variety of microcontrollers that cost very little, use virtually no power, and can be programmed quickly. The Cortex-M family has surfaced as a very popu- lar product with silicon vendors: in 2013, 170 licenses were held by 130 companies, with their parts costing anywhere from two dollars to twenty cents. The Cortex-M0 is the simplest, containing only a core, a nested vectored interrupt controller (NVIC), a bus interface, and basic debug logic. Its tiny size, ultra-low gate count, and small instruction set (only 56 instructions) make it well suited for applications that only require a basic controller. Commercial parts include the LPC1100 line from NXP, and the XMC1000 line from Infineon. The Cortex-M0+ is similar to the MO, witha You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.An Overview of Computing Systems 15 1.4. NUMBER SYSTEMS Since computers operate internally with transistors acting as switches, the combi- national logic used to build adders, multipliers, dividers, ete., understands values of I or 0, either on or off. The binary number system, therefore, lends itself to use in computer systems more easily than base ten numbers. Numbers in base two are centered on the idea that each digit now represents a power of two, instead of a power of ten. In base ten, allowable numbers are 0 through 9, so if you were to count the number of sheep in a pasture, you would say 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and then run out of digits. Therefore, you place a | in the 10’s position (see Figure 1.10), to indicate you've counted this high already, and begin using the old digits again—10, Il, 12, 13, ete. Now imagine that you only have two digits with which to count: 0 or 1. To count that same set of sheep, you would say 0, 1 and then you're out of digits. We know the next value is 2 in base ten, but in base two, we place a | in the 2’s position and keep counting—10, I, and again we're out of digits to use. A marker is then placed in the 4's position, and we do this as much as we like. EXAMPLE 1.1 Convert the binary number 110101, to decimal. SowTiON This can be seen as This would be equivalent to 32 + 16 +4 +1=53,q. The subscripts are normally only used when the base is not 10. You will see quickly that a number such as 101 normally doesn’t raise any questions until you start using computers. At first glance, this is interpreted as a base ten number— one hundred one. However, careless notation could have us looking at this num- ber in base two, so be careful when writing and using numbers in different bases. After staring at I's and 0’s all day, programming would probably have people jump- ing out of windows, so better choices for representing numbers are base eight (octal, although you'd be hard pressed to find a machine today that mainly uses octal nota~ tion) and base sixteen (hexadecimal or hex, the preferred choice), and here the digits 10? 10! 109 43 8 7 AN Ahundreds | 8 ones Btens FIGURE 1.10 Base ten representation of 438.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.An Overview of Computing Systems 19 One’s complement numbers are not used much in modern computing systems either, mostly because there is too much extra work necessary to perform basic arithmetic operations. To create @ negative value in this representation, simply invert all the bits of its positive, binary value. The sign bit will be a 1, just like sign-magnitude representations, but there are two issues that arise when work- ing with these numbers. The first is that you end up with two representations for 0, and the second is that it may be necessary to adjust a sum when adding two values together, causing extra work for the processor. Consider the following two examples. EXAMPLE 1.6 Assuming that you have 16 bits to represent a number, add the values ~124 to 236 in one’s complement notation. SowTION To create ~124 in one’s complement, simply write out the binary representation for 124, and then invert all the bits: 124 — 0000000001111100 -124-1111111110000011 Adding 236 gives us -124 1111111110000011 +236 +0000000011101100 carry > 1 0000000001101111 The problem is that the answer is actually 112, or 0x70 in hex. In one’s comple- ment notation, a carry in the most significant bit forces us to add a one back into the sum, which is one extra step 0000000001101111 +1 og 1 112 0000000001110000 EXAMPLE 1.7 Add the values ~8 and 8 together in one’s complement, assuming 8 bits are avail- able to represent the numbers, SowuTiON Again, simply take the binary representation of the positive value and invert all the bits to get -8: