I.
NMOS Inverter with Resistor Pull-Up
R
+
VOUT
V
_ DD
CL
+
VIN
_
VOUT
Cutoff
VOH
vout
vin V = -gm(R||ro)
M
VM
Saturation
Triode
VOL
VIL
VM
VIH
VIN
EECS 6.012 Spring 1998
Lecture 12
II. NMOS Inverter with Current-Source Pull-Up
A. Motivation
With the resistor pull-up we could increase R to sharpen transfer
characteristic BUT it slows down inverter operation.
B. Idealized Current-Source Pull-Up
iSUP
+
+
iSUP
vSUP
ISUP
vSUP
roc
_
(a)
iSUP
ISUP
roc
1
roc
vSUP
(b)
(c)
Incremental resistance can be large --> high small-signal gain
Current is large ---> Fast transitions
EECS 6.012 Spring 1998
Lecture 12
C. NMOS Inverter with Current-Source Pull-Up
Replace resistor with current source
VDD
+
vSUP
iSUP
_
iD
CL
vIN
+
vOUT
Find the voltage transfer curve graphically by superimposing
iSUP vs. vOUT (load line) on top of the drain characteristics
iSUP
-1
curve is mirrored
vOUT = VDD --> vSUP = 0
--> vSUP = VDD
vOUT = 0
roc
I SUP
VDD
vOUT
EECS 6.012 Spring 1998
Lecture 12
D. Load Line Analysis
Voltage transfer curve is much closer to that of the ideal inverter
iD
V
ISUP + rDD
oc
VIN = VGS
3
2
1
VDD
vOUT = vDS
(a)
VOUT
4
VIN
(b)
EECS 6.012 Spring 1998
Lecture 12
E. PMOS as a Current-Source Pull-Up
Substitute p-channel MOSFET (with bulk connected to the source to
make VSB =0 and source connected to the supply voltage)
The bias voltage VB is selected so that the appropriate source-gate
voltage drop is obtained: VSG2 = VDD - VB. The supply current iSUP as a
function of the supply voltage vSUP = VSD2 = VDD - VOUT is:
VDD
ID
M2
VB
ID
VIN
M1
CL
VOUT
VDD
(a)
VOUT
(b)
VOUT
ID
VMAX = V +
M1 Cutoff, M2 Triode
M1 Sat, M2 Triode
1
2
3
5 4
M1 Sat, M2 Sat
VIN
.............4
2
VMIN
1
VOUT
M1 Triode, M2 Sat
5
V+ VIN
In order to find the slope at VIN = VM, we note that both transistors
are saturated there (near point 3) and that our small-signal models
from Chapter 4 are valid
EECS 6.012 Spring 1998
Lecture 12
F. Calculate midpoint - VM
VM is the input voltage VIN, where the output voltageVOUT = VIN
Both transistors are saturated
Equate drain currents, omitting the channel length modulation terms
I
Dn
2
1
W
- V M VT
= -2 n C ox --L n
n
2
1
W
- ( V DD V B + V Tp )
I Dp = -2 p C --ox L p
G. Find slope of transfer characteristic at VM
s2
+
gmpvsg2
vsg2 = 0 V
+
vin
rop
d2
g2
g1
vout
d1
vgs1
gmnvgs1
ron
s1
dv OUT
d v IN
VM
v out
= --------- = g mn r on r op
v in
EECS 6.012 Spring 1998
Lecture 12
III. Complementary MOS (CMOS) Inverter
A. Motivation
When input is high, the n-channel MOSFET is in the triode region
conducting ID = IL from VDD to ground.
Power dissipation of P = IL x VDD
Need a current source load which itself is switchable -- turning itself
off when the output is low.
B. Concept
VDD
INPUT
HIGH
VDD
OUTPUT
LOW
INPUT
LOW
OUTPUT
HIGH
CL
(a)
VDD
VIN
CL
(b)
+
CL
VOUT
(c)
C. Practical realization:
Connect input to gate of p-channel device.
VIN = VDD --> VSG2 = VDD - VIN = 0 < |VTp| --> cutoff
VIN = 0 --> VSG2 = VDD - VIN = VDD >> |VTp| --> on (triode region)
NMOS transistor is off when PMOS is in triode region
PMOS transistor is off when NMOS is in triode region
EECS 6.012 Spring 1998
Lecture 12
D. CMOS Transfer Characteristic
Plotting the p-channel load on the n-channel drivers drain
characteristics allows us to find the input-output voltage pairs which
satisfy the constraint
IDn = -IDp
VOUT
VDD 1
5
VDD
VIN
IDp = IDn
IDn = IDp
VIN
3
3
4
1
VDD
5
n-channel
(a)
2
VOUT
1
VDD
VOUT
p-channel
(b)
We can arrange to have the upper and lower noise margins be
identical, if the transistor geometries are selected appropriately
EECS 6.012 Spring 1998
Lecture 12
III. Quantitative Noise Margins
A. CalculateVM
VM is the input voltage VIN, where the output voltageVOUT = VIN
Both transistors are saturated
Equate drain currents, omitting the channel length modulation terms
I
Dn
2
1
W
- ( V M V Tn )
= 2- n C ox --L n
2
1
W
- ( V DD V M + V Tp )
I Dp = -2 p C --ox L p
Let kn = n Cox (W/L)n and kp = p Cox (W/L)p
1
- kn ( V M
2
V Tn )
1
= -2 k p ( V DD V M + V Tp )
Result:
p
+
---- ( V DD + V Tp )
Tn
k
n
= -------------------------------------------------------V
+ ----pk
EECS 6.012 Spring 1998
Lecture 12
B. Small-Signal Model: CMOS Inverter at VIN = VM
s2
+
vsg2
_
g1 = g2
d1=d2
vgs1
vin
rop
gmpvsg2
gmnvgs1
vout
ron
_
s1
p-channel MOSFET small-signal source-gate voltage is vsg2 = - vin
d1=d2
g1=g2
vout
+
vin
gmnvin
gmpvin
ron
rop
_
s1=s2
EECS 6.012 Spring 1998
Lecture 12
C. Approximate Transfer Curve
The small-signal gain (which is the slope of the transfer curve when
the input is equal to the mid-point voltage) is:
v
out
v in = ( g mn + g mp ) r on
op
An inverter optimized for gain can have values in the 100s.
Real inverters have a channel length which is as small as possible (to
minimize the area ... and maximize speed)
Output resistance is lowered and a typical value is vout / vin = -5.
IL
V DD V M
= V M + ------------------------Av
V
IH
VM
= V M -------Av
VOUT
VOH = VDD
VDD VM
Av
VM
VDD VM
Av
VOL = 0 V
VIL
VM
VIH
VIN
EECS 6.012 Spring 1998
Lecture 12
