A4982

DMOS Microstepping Driver with Translator

And Overcurrent Protection
Features and Benefits

Description

Low RDS(ON) outputs

Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
3.3 and 5 V compatible logic supply
Thin profile QFN and TSSOP packages
Thermal shutdown circuitry
Short-to-ground protection
Shorted load protection
Low current Sleep mode, < 10 A
No smoke no fire (NSNF) compliance (ET package)

The A4982 is a complete microstepping motor driver with

built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, and sixteenth-step
modes, with an output drive capacity of up to 35 V and 2 A.
The A4982 includes a fixed off-time current regulator which
has the ability to operate in Slow or Mixed decay modes.
The ET package meets customer requirements for no smoke
no fire (NSNF) designs by adding no-connect pins between
critical output, sense, and supply pins. So, in the case of a
pin-to-adjacent-pin short, the device does not cause smoke
or fire. Additionally, the device does not cause smoke or fire
when any pin is shorted to ground or left open.
The translator is the key to the easy implementation of the
A4982. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A4982 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.

Packages:
32-contact QFN

with exposed thermal pad

5 mm 5 mm 0.90 mm
(ET package)

Approximate size

During stepping operation, the chopping control in the A4982

automatically selects the current decay mode, Slow or Mixed.
In Mixed decay mode, the device is set initially to a fast decay
for a proportion of the fixed off-time, then to a slow decay for
the remainder of the off-time. Mixed decay current control

24-pin TSSOP
with exposed thermal pad
(LP Package)

Continued on the next page

Typical Application Diagram

VDD

0.1 F

0.22 F
VREG ROSC

0.22 F

CP1

CP2

0.1 F

VCP

VDD

VBB2

5 k
Microcontroller or
Controller Logic

SLEEP
STEP

VBB1

OUT1A

A4982

OUT1B
SENSE1

MS1
MS2
DIR

OUT2A

ENABLE

OUT2B

RESET
VREF

4982-DS Rev. 5

GND

GND

SENSE2

100 F

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Description (continued)
results in reduced audible motor noise, increased step accuracy,
and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
undervoltage lockout (UVLO), and crossover-current protection.

Special power-on sequencing is not required.

The A4982 is supplied in two surface mount package, the ET, a
5mm 5 mm, 0.90 mm nominal overall package height QFN
package, and the LP package, a 24pin TSSOP. Both packages have
exposed pads for enhanced thermal dissipation, and are lead (Pb)
free (suffixT), with 100% matte tin plated leadframes.

Selection Guide
Part Number

Package

Packing

A4982SETTR-T

32-pin QFN with exposed thermal pad

1500 pieces per 7-in. reel

A4982SLPTR-T

24-pin TSSOP with exposed thermal pad

4000 pieces per 13-in. reel

Absolute Maximum Ratings

Characteristic

Symbol

Notes

Rating

Units

35

Load Supply Voltage

VBB

Output Current

IOUT

Logic Input Voltage

VIN

0.3 to 5.5

Logic Supply Voltage

VDD

0.3 to 5.5

2.0 to 37

VSENSE

0.5 to 0.5

VREF

5.5

Motor Outputs Voltage

Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature

20 to 85

TJ(max)

TA

Range S

150

Tstg

55 to 150

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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Functional Block Diagram

0.1 F

0.22 F
VREG
VDD

Current
Regulator

ROSC

CP1

CP2

Charge
Pump

OSC

VCP
0.1 F
DMOS Full Bridge
REF
DAC

VBB1

OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay

STEP

OCP
Gate
Drive

DIR
RESET
MS1

Translator

Control
Logic

MS2

PWM Latch
Blanking
Mixed Decay

SLEEP
DAC

DMOS Full Bridge

VBB2

RS1

OUT2A
OCP

ENABLE

SENSE1

OUT2B

SENSE2

RS2

VREF

Allegro MicroSystems, LLC

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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A4982

DMOS Microstepping Driver with Translator

And Overcurrent Protection

ELECTRICAL CHARACTERISTICS1 at TA = 25C, VBB = 35 V (unless otherwise noted)

Characteristics
Output Drivers

Min.

Typ.2

Max.

Units

8
0
3.0

320
320

35
35
5.5
430
430
1.3
1.3
4
2
10
8
5
10

V
V
V
m
m
V
V
mA
mA
A
mA
mA
A

VIN(1)

VDD0.7

VIN(0)

20

<1.0

VDD0.3
20

20

<1.0

20

5
0.7
20
23
0
3

100

100
33.3
11
1
30
30

475

19
1.3
40
37
4
3
15
5
5
800

k
k
%
s
s
s
V
A
%
%
%
ns

2.1

2.7

165
15
2.8
90

2.9

A
C
C
V
mV

Symbol

Load Supply Voltage Range

VBB

Logic Supply Voltage Range

VDD

Output On Resistance

RDSON

Body Diode Forward Voltage

VF

Motor Supply Current

IBB

Logic Supply Current

IDD

Test Conditions
Operating
During Sleep Mode
Operating
Source Driver, IOUT = 1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = 1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
Operating, outputs disabled
Sleep Mode
fPWM < 50 kHz
Outputs off
Sleep Mode

Control Logic
Logic Input Voltage
Logic Input Current
Microstep Select
Logic Input Hysteresis
Blank Time

IIN(1)
IIN(0)
RMS1
RMS2
VHYS(IN)
tBLANK

Fixed Off-Time

tOFF

Reference Input Voltage Range

Reference Input Current

VREF
IREF

Current Trip-Level Error3

errI

Crossover Dead Time

Protection
Overcurrent Protection Threshold4
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VDD Undervoltage Lockout
VDD Undervoltage Hysteresis

tDT
IOCPST
TTSD
TTSDHYS
VDDUVLO

VDDUVLOHYS

VIN = VDD0.7

VIN = VDD0.3
MS1 pin
MS2 pin
As a % of VDD
OSC = VDD or GND
ROSC = 25 k

VREF = 2 V, %ITripMAX = 38.27%

VREF = 2 V, %ITripMAX = 70.71%
VREF = 2 V, %ITripMAX = 100.00%

VDD rising

1For

input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3V
ERR = [(VREF/8) VSENSE] / (VREF/8).
4Overcurrent protection (OCP) is tested at T = 25C in a restricted range and guaranteed by characterization.
A
2Typical

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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

THERMAL CHARACTERISTICS may require derating at maximum conditions

Characteristic

Symbol

Package Thermal Resistance

RJA

Test Conditions*

Value Units

ET package; estimated, on 4-layer PCB, based on JEDEC standard

32

C/W

LP package; on 4-layer PCB, based on JEDEC standard

28

C/W

*In still air. Additional thermal information available on Allegro Web site.

Maximum Power Dissipation, PD(max)

5.5
5.0
4.5

Power Dissipation, PD (W)

4.0
(R

3.5

(R

3.0

2.5

31

28

/W

/W

2.0
1.5
1.0
0.5
0.0

20

40

60

80
100
120
Temperature (C)

140

160

180

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115 Northeast Cutoff
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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

tA

tB

STEP
tC

tD

MS1, MS2,
RESET, or DIR

Time Duration

Symbol

Typ.

Unit

STEP minimum, HIGH pulse width

tA

STEP minimum, LOW pulse width

tB

Setup time, input change to STEP

tC

200

ns

Hold time, input change to STEP

tD

200

ns

Figure 1: Logic Interface Timing Diagram

Table 1: Microstep Resolution Truth Table

MS1

MS2

Microstep Resolution

Excitation Mode

Full Step

2 Phase

Half Step

1-2 Phase

Quarter Step

W1-2 Phase

Sixteenth Step

4W1-2 Phase

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115 Northeast Cutoff
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A4982

DMOS Microstepping Driver with Translator

And Overcurrent Protection

Functional Description
Device Operation. The A4982 is a complete microstepping

motor driver with a built-in translator for easy operation with

minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step resolution
modes. The currents in each of the two output full-bridges and all
of the N-channel DMOS FETs are regulated with fixed off-time
PWM (pulse width modulated) control circuitry. At each step,
the current for each full-bridge is set by the value of its external
current-sense resistor (RS1 and RS2), a reference voltage (VREF),
and the output voltage of its DAC (which in turn is controlled by
the output of the translator).
At power-on or reset, the translator sets the DACs and the phase
current polarity to the initial Home state (shown in Figures 10
through 13), and the current regulator to Mixed decay mode for
both phases. When a step command signal occurs on the STEP
input, the translator automatically sequences the DACs to the
next level and current polarity. (See Table 2 for the current-level
sequence.) The microstep resolution is set by the combined effect
of the MSx inputs, as shown in Table 1.
When stepping, if the new output levels of the DACs are lower
than their previous output levels, then the decay mode for the
active full-bridge is set to Mixed. If the new output levels of the
DACs are higher than or equal to their previous levels, then the
decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that
results from the back EMF of the motor.

Low Current Microstepping. Intended for applications

where the minimum on-time prevents the output current from

regulating to the programmed current level at low current steps.
To prevent this, the device can be set to operate in Mixed decay
mode on both rising and falling portions of the current waveform.
This feature is implemented by shorting the ROSC pin to ground.
In this state, the off-time is internally set to 30 s.

S
E
T
). The R E S E T input sets the translator
Reset Input (RE

to a predefined Home state (shown in Figures 10 through 13), and

turns off all of the FET outputs. All STEP inputs are ignored until
E
S E
T
input is set to high.
the R

Step Input (STEP). A low-to-high transition on the STEP

input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is
determined by the combined state of inputs MS1 and MS2.

Direction Input (DIR). This determines the direction of rota-

tion of the motor. Changes to this input do not take effect until the
next STEP rising edge.

Internal PWM Current Control. Each full-bridge is con-

trolled by a fixed off-time PWM current control circuit that limits

the load current to a desired value, ITRIP. Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows
through the motor winding and the current sense resistor, RSx.
When the voltage across RSx equals the DAC output voltage, the
current sense comparator resets the PWM latch. The latch then
Microstep Select (MS1 and MS2). The microstep resolution is set by the voltage on logic inputs MS1 and MS2, as shown turns off either the source FET (when in Slow decay mode) or the
sink and source FETs (when in Mixed decay mode).
in Table 1. MS1 has a 100 k pull-down resistance, and MS2 has
a 33.3 k pull-down resistance. When changing the step mode the The maximum value of current limiting is set by the selection of
change does not take effect until the next STEP rising edge.
RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting,
If the step mode is changed without a translator reset, and absoITripMAX (A), which is set by
lute position must be maintained, it is important to change the
step mode at a step position that is common to both step modes in
ITripMAX = VREF /(8 RS)
order to avoid missing steps. When the device is powered down,
or reset due to TSD or an overcurrent event the translator is set to where RS is the resistance of the sense resistor () and VREF is
the home position which is by default common to all step modes. the input voltage on the REF pin (V).

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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Slow
Decay

Mixed
Decay

Slow
Decay

Mixed
Decay

Slow
Decay

Mixed
Decay

Slow
Decay

Mixed
Decay

Missed
Step

Voltage on ROSC terminal 2 V/div.

Step input 10 V/div.

t , 1 s/div.
Figure 2: Missed Steps in Low-Speed Microstepping
Mixed Decay

ILOAD 500 mA/div.

Step input 10 V/div.

No Missed
Steps

t , 1 s/div.

Figure 3: Continuous Stepping Using Automatically-Selected Mixed Stepping (ROSC pin grounded)

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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

The DAC output reduces the VREF output to the current sense
comparator in precise steps, such that
Itrip = (%ITripMAX /100)

ITripMAX

(See Table 2 for %ITripMAX at each step.)

It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.

Fixed Off-Time. The internal PWM current control circuitry

uses a one-shot circuit to control the duration of time that the

DMOS FETs remain off. The off-time, tOFF, is determined by the
ROSC terminal. The ROSC terminal has three settings:
ROSC tied to VDD off-time internally set to 30s, decay
mode is automatic Mixed decay except when in full step where
decay mode is set to Slow decay
ROSC tied directly to ground off-time internally set to
30s, current decay is set to Mixed decay for both increasing
and decreasing currents.
ROSC through a resistor to ground off-time is determined
by the following formula , the decay mode is automatic Mixed
decay for all step modes.
tOFF ROSC 825
Where tOFF is in s.

Blanking. This function blanks the output of the current sense

comparators when the outputs are switched by the internal current

control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (s), is approximately
tBLANK 1 s

Shorted-Load and Short-to-Ground Protection.

If the motor leads are shorted together, or if one of the leads is

shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the
E
E
P input goes
device will remain disabled (latched) until the S L
high or VDD power is removed. A short-to-ground overcurrent
event is shown in Figure 4.
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time (1s) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into

a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in Figure 5.
If the driver is operating in Mixed decay mode, it is normal for
the positive current to spike, due to the bridge going in the forward direction and then in the negative direction, as a result of the
direction change implemented by the Mixed decay feature. This
is shown in Figure 6. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.

Charge Pump (CP1 and CP2). The charge pump is used to

generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 F ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 F ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric 15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.

VREG (VREG). This internally-generated voltage is used to

operate the sink-side FET outputs. The nominal output voltage

of the VREG terminal is 7V. The VREG pin must be decoupled
with a 0.22 F ceramic capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4982 are disabled.
Capacitor values should be Class 2 dielectric 15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.

Enable Input (ENABLE ). This input turns on or off all of the

FET outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs as
required. The translator inputs STEP, DIR, MS1, and MS2, as well
as the internal sequencing logic, all remain active, independent of
N A B L
E
input state.
the E

Shutdown. In the event of a fault, overtemperature (excess TJ)

or an undervoltage (on VCP), the FET outputs of the A4982 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.

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A4982

DMOS Microstepping Driver with Translator

And Overcurrent Protection

Sleep Mode ( SLEEP ). To minimize power consumption

when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator,
E
E
P pin puts the A4982
and charge pump. A logic low on the S L
into Sleep mode. A logic high allows normal operation, as well as
start-up (at which time the A4982 drives the motor to the Home
microstep position). When emerging from Sleep mode, in order
to allow the charge pump to stabilize, provide a delay of 1 ms
before issuing a Step command.

5 A / div.

Mixed Decay Operation. The bridge operates in Mixed

decay mode, at power-on and reset, and during normal running

according to the ROSC configuration and the step sequence, as
shown in Figures 10 through 13. During Mixed decay, when the
trip point is reached, the A4982 initially goes into a fast decay
mode for 31.25% of the off-time, tOFF. After that, it switches to
Slow decay mode for the remainder of tOFF. A timing diagram for
this feature appears in Figure7.
Typically, mixed decay is only necessary when the current in the
winding is going from a higher value to a lower value as determined
by the state of the translator. For most loads automatically-selected
mixed decay is convenient because it minimizes ripple when the current is rising and prevents missed steps when the current is falling.
For some applications where microstepping at very low speeds is
necessary, the lack of back EMF in the winding causes the current to
increase in the load quickly, resulting in missed steps. This is shown
in Figure 2. By pulling the ROSC pin to ground, mixed decay is set
to be active 100% of the time, for both rising and falling currents,
and prevents missed steps as shown in Figure 3. If this is not an
issue, it is recommended that automatically-selected mixed decay
be used, because it will produce reduced ripple currents. Refer to the
Fixed Off-Time section for details.

Synchronous Rectification. When a PWM-off cycle is

triggered by an internal fixed-off-time cycle, load current recirculates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low FET RDS(ON). This reduces power dissipation
significantly, and can eliminate the need for external Schottky
diodes in many applications. Synchronous rectification turns off
when the load current approaches zero (0 A), preventing reversal
of the load current.

Fault
latched

Figure 4: Short-to-Ground Event

5 A / div.
Fixed off-time

t
Figure 5: Shorted Load (OUTxA OUTxB) in Slow Decay
Mode

5 A / div.
Fixed off-time

Fast decay portion

(direction change)
t
Figure 6: Shorted Load (OUTxA OUTxB) in Mixed Decay
Mode
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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982
VSTEP
100.00
70.71

See Enlargement A

IOUT

70.71
100.00

Enlargement A
toff
IPEAK

tFD

tSD
Slow Decay

Mixed Decay

IOUT

Fa

st

De

ca

t
Symbol
toff
IPEAK

Characteristic
Device fixed off-time
Maximum output current

tSD

Slow decay interval

tFD

Fast decay interval

IOUT

Device output current

Figure 7: Current Decay Modes Timing Chart

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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Application Layout
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor
(CIN2). This is necessary because the ceramic capacitor will be
responsible for delivering the high frequency current components.
The sense resistors, RSx, should have a very low impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. The SENSEx
pins have very short traces to the RSx resistors and very thick,
low impedance traces directly to the star ground underneath the
device. If possible, there should be no other components on the
sense circuits.

Layout. Typical application circuits and layouts are shown in

Figures 8 (LP package) and 9 (ET package).The printed circuit
board should use a heavy groundplane. For optimum electrical
and thermal performance, the A4982 must be soldered directly
onto the board. On the underside of the A4982 package is an
exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed
surface on the PCB. Thermal vias are used to transfer heat to
other layers of the PCB.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A4982, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.

Solder

A4982

Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)

PCB

Thermal (2 oz.)

Thermal Vias

OUT2B
C3
U1
GND

C6

GND

C4

GND

C3
OUT2A

C5

R4

ROSC

R5

C4
C5

OUT1A
C1

GND

OUT1B
GND

GND
BULK
CAPACITANCE
C2

VDD

VCP
VREG
MS1
MS2
ROSC
SLEEP
VDD
STEP

C1
GND

GND
ENABLE
OUT2B

CP2

RESET

ROSC
GND

A4982

CP1

PAD

VBB2
SENSE2
OUT2A

C6
R4

OUT1A
SENSE1
VBB1

R5

OUT1B

REF

DIR

C2

GND

VDD

VBB

VBB

Figure 8: LP Package Typical Application and Circuit Layout

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DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982
OUT2A

OUT2B

OUT1A

OUT1B
OUT2B

GND

OUT1A

OUT2A

R5

R4

GND

OUT1B

OUT2B

C6
BULK
CAPACITANCE

SLEEP

MS1

R3

STEP

C4

GND

C2

REF
ROSC

CP2

C3

RESET

A4982

VCP

C1

DIR
GND

CP1

GND
C3

VBB1

GND

C6

VBB

OUT1B

PAD

ENABLE

VREG

U1

VBB2

VDD

C2

OUT1A

VBB

SENSE1

SENSE2

R5

MS2

R4

OUT2A

C7

VDD

C1

C5

ROSC

C4
GND

C5 ROSC

VDD

Figure 9: ET Package Typical Application and Circuit Layout

Pin Circuit Diagrams

VDD

VBB

VBB
8V
GND

GND

SENSE

GND

CP2

GND

GND

GND

GND
GND

VBB

10 V

CP1

40 V

PGND

VREG

VCP

VREG

DMOS
Parasitic
GND

8V

STEP
MS1
MS2
DIR
ENABLE
RESET
SLEEP

VBB
OUT
DMOS
Parasitic

8V
GND

GND

DMOS
Parasitic

GND

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13

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982
RESET

STEP

STEP

100.00

Mixed*

70.71

Mixed*

Slow

70.71

70.71
100.00
100.00

Home Microstep Position

0.00

100.00
100.00
70.71

0.00

Mixed*

Slow Slow

70.71

Phase 2
IOUT2A
Direction = H
(%)

Mixed

0.00

70.71

Phase 2
IOUT2B
Direction = H
(%)

Slow

Mixed

Home Microstep Position

Phase 1
IOUT1A
Direction = H
(%)

Slow

Home Microstep Position

Phase 1
IOUT1A
Direction = H
(%)

Slow

Mixed

Mixed

Home Microstep Position

100.00

Slow

Mixed

Slow

Mixed

0.00

70.71

70.71

100.00

100.00

*With ROSC pin tied to GND

*With ROSC pin tied to GND

DIR= H

DIR= H

Figure 10: Decay Mode for Full-Step Increments

Figure 11: Decay Modes for Half-Step Increments

STEP
100.00
92.39
70.71

Slow

Slow

Mixed

38.27
70.71
92.39
100.00
100.00
92.39

Slow

Mixed*

70.71

Phase 2
IOUT2B
Direction = H
(%)

Mixed

0.00
Home Microstep Position

Phase 1
IOUT1A
Direction = H
(%)

Mixed*

38.27

38.27

Slow
Mixed

Slow

Mixed

Slow

Mixed

0.00
38.27
70.71
92.39
100.00

*With ROSC pin tied to GND

DIR= H
Figure 12: Decay Modes for Quarter-Step Increments
Allegro MicroSystems, LLC
115 Northeast Cutoff
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14

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982
STEP
100
96
88
83
77
71
63
56
47

Mixed*

38
29

Phase 1
IOUT1A
Direction = H
(%)

20
10

Slow

Mixed

Slow

Mixed

10
20
29

Home Microstep Position

38
47
56
63
71
77
83
88
96
100
100
96
88
83
77
71
63
56
47
38

Mixed*

29

Phase 2
IOUT2B
Direction = H
(%)

20
10
0

Slow
Mixed

Slow

Mixed

Slow

10
20
29
38
47
56
63
71
77
83
88
96
100

*With ROSC pin tied to GND

DIR= H
Figure 13: Decay Modes for Sixteenth-Step Increments

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15

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Table 2: Step Sequencing Settings

Home microstep position at Step Angle 45; DIR = H
Full
Step
(#)

Half
Step
(#)

1/4
Step
(#)

1/16
Phase 2
Phase 1
Step
Step
Current
Current
Angle
(#) (% ITRIP(max)) (% ITRIP(max))
()
1

0.00

100.00

0.0

9.38

100.00

18.75

29.69

Full
Step
(#)

Half
Step
(#)

1/4
Step
(#)

1/16
Phase 2
Phase 1
Step
Step
Current
Current
Angle
(#) (% ITRIP(max)) (% ITRIP(max))
()
33

0.00

100.00

180.0

5.6

34

9.38

100.00

185.6

98.44

11.3

35

18.75

98.44

191.3

95.31

16.9

36

29.69

95.31

196.9

37.50

92.19

22.5

37

37.50

92.19

202.5

46.88

87.50

28.1

38

46.88

87.50

208.1

56.25

82.81

33.8

39

56.25

82.81

213.8

64.06

76.56

39.4

40

64.06

76.56

219.4

70.31

70.31

45.0

41

70.31

70.31

225.0

10

76.56

64.06

50.6

42

76.56

64.06

230.6

11

82.81

56.25

56.3

43

82.81

56.25

236.3

12

87.50

46.88

61.9

44

87.50

46.88

241.9

13

92.19

37.50

67.5

45

92.19

37.50

247.5

14

95.31

29.69

73.1

46

95.31

29.69

253.1

15

98.44

18.75

78.8

47

98.44

18.75

258.8

16

100.00

9.38

84.4

48

100.00

9.38

264.4

17

100.00

0.00

90.0

49

100.00

0.00

270.0

18

100.00

9.38

95.6

50

100.00

9.38

275.6

19

98.44

18.75

101.3

51

98.44

18.75

281.3

20

95.31

29.69

106.9

52

95.31

29.69

286.9

21

92.19

37.50

112.5

53

92.19

37.50

292.5

22

87.50

46.88

118.1

54

87.50

46.88

298.1

23

82.81

56.25

123.8

55

82.81

56.25

303.8

24

76.56

64.06

129.4

56

76.56

64.06

309.4

25

70.31

70.31

135.0

57

70.31

70.31

315.0

26

64.06

76.56

140.6

58

64.06

76.56

320.6

27

56.25

82.81

146.3

59

56.25

82.81

326.3

28

46.88

87.50

151.9

60

46.88

87.50

331.9

29

37.50

92.19

157.5

61

37.50

92.19

337.5

30

29.69

95.31

163.1

62

29.69

95.31

343.1

31

18.75

98.44

168.8

63

18.75

98.44

348.8

32

9.38

100.00

174.4

64

9.38

100.00

354.4

33

0.00

100.00

180.0

0.00

100.00

360.0

10

11

12

13

14

15

16

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16

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Pin-out Diagrams
LP Package

CP2

SENSE2
NC
OUT2A
NC
NC
OUT1A
NC
SENSE1
1
2
3
4
5
6
7

24 GND

CP2 2

23 ENABLE

VCP 3

22 OUT2B

24
23
22
21
20
19
18

PAD

OUT1B
NC
VBB1
NC

21 VBB2

VREG 4

20 SENSE2

MS1 5
MS2 6

PAD

RESET 7

DIR
GND
REF
17 STEP

ROSC 8
SLEEP 9
VDD 10
STEP 11

9
10
11
12
13
14
15
16

OUT2B
NC
VBB2
NC
ENABLE
GND
CP1

CP1 1

32
31
30
29
28
27
26
25

ET Package

VCP
VREG
MS1
MS2
RESET
ROSC
SLEEP
VDD

REF 12

19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND

Terminal List Table

Name
CP1

Number

Description

ET1

LP

Charge pump capacitor terminal

CP2

Charge pump capacitor terminal

DIR

20

14

Logic input
Logic input

E
NA
BLE

23

GND

6, 19

13, 24

MS1

11

Logic input

MS2

12

Logic input

NC

2, 4, 21,
23, 26, 28,
29, 31

No connection

Ground2

OUT1A

27

18

DMOS Full Bridge 1 Output A

OUT1B

24

15

DMOS Full Bridge 1 Output B

OUT2A

30

19

DMOS Full Bridge 2 Output A

OUT2B

22

DMOS Full Bridge 2 Output B

REF

18

12

Gm reference voltage input

RE
S
ET

13

Logic input

ROSC

14

Timing set

SENSE1

25

17

Sense resistor terminal for Bridge 1

SENSE2

32

20

Sense resistor terminal for Bridge 2

S
LE
EP

15

Logic input

STEP

17

11

Logic input

VBB1

22

16

Load supply

VBB2

21

Load supply

VCP

Reservoir capacitor terminal

VDD

16

10

Logic supply

VREG

10

Regulator decoupling terminal

PAD

Exposed pad for enhanced thermal dissipation*

*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.

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17

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

ET Package, 32-Contact QFN with Exposed Thermal Pad

5.00 0.15
32
1
2

0.30

32

0.50

1.00
1
2

A
5.00 0.15

3.40

5.00

1
33X

SEATING
PLANE

0.08 C
0.250.10

0.90 0.10

0.50 BSC

3.40

5.00

PCB Layout Reference View

For Reference Only; not for tooling use

(reference JEDEC MO-220VHHD-6)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown

0.500.10
3.40
B

2
1
32

3.40

A Terminal #1 mark area

B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 QFN50P500X500X100-33V6M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals

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18

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

LP Package, 24-Pin TSSOP with Exposed Thermal Pad

7.80 0.10
24

0.65

0.45

4 4
+0.05
0.15 0.06

B
3.00

4.40 0.10

6.40 0.20

6.10

(1.00)

4.32

0.25

24X

SEATING
PLANE

0.10 C
+0.05
0.25 0.06

3.00

0.60 0.15

0.65

1.20 MAX
0.15 MAX

SEATING PLANE
GAUGE PLANE

1.65

4.32
C

PCB Layout Reference View

For Reference Only; not for tooling use

(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)

Allegro MicroSystems, LLC

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com

19

DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

Revision History
Revision

Revision Date

March 21, 2012

May 7, 2014

Description of Revision
Update example layout
Revised Fixed Off-Time section and Figure 10

Copyright 2008-2014, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegros product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com
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1.508.853.5000; www.allegromicro.com

20