VGA DISPLAY

Video Graphics Array (VGA) refers specifically to the display hardware first introduced with
the IBM PS/2 line of computers in 1987, but through its widespread adoption has also come to mean either
an analog computer display standard, the 15-pin D-subminiature VGA connector or the 640480 resolution
itself. While this resolution was superseded in the personal computer market in the 1990s, mobile devices
have only caught up in the last few years.
VGA was the last graphical standard introduced by IBM that the majority of PC
clone manufacturers conformed to, making it today (2013) the lowest common denominator that almost all
post-1990 PC graphics hardware can be expected to implement. For example, the Microsoft Windows splash
screen, in versions prior to Windows Vista, appears while the machine is still operating in VGA mode, which
is the reason that this screen always appears in reduced resolution and color depth. Windows Vista and newer
versions can make use of the VESA BIOS Extension support of newer graphics hardware to show their
splash screen in a higher resolution than VGA allows.
VGA was officially followed by IBM's Extended Graphics Array (XGA) standard, but it was
effectively superseded by numerous slightly different extensions to VGA made by clone manufacturers that
came to be known collectively as Super VGA. VGA is a standard interface for controlling analog
monitors. The computing side of the interface provides the monitor with horizontal and vertical sync signals,
color magnitudes, and ground references.
Standard VGA text mode uses an 80x25 character display, rendered with a 9x16 pixel font,
for an effective resolution of 720x400 in 16 colors. 16-color 80x50 (8x8 font grid), 40x25 (360x400
resolution) modes are also available.
The original VGA specifications are as follows:

256 kB Video RAM (The very first cards could be ordered with 64 kB or 128 kB of RAM, at the cost of
losing some or all high-resolution 16-color modes.)
16-color and 256-color paletted display modes.
262,144-color global palette (6 bits, and therefore 64 possible levels, for each of the red, green, and blue
channels via the RAMDAC)
Selectable 25.175 MHz or 28.322 MHz master clock
Maximum of 800 horizontal pixels
Maximum of 600 lines
Refresh rates at up to 70 Hz
Vertical blank interrupt (Not all clone cards support this.)
Barrel shifter
Split screen support
0.7 V peak-to-peak

VGA Controller

A controller is used to tranfer the data for display on to the monitor by synchronising the
display timing. It generates analog signals corresponding to R, B and G contents of the data to be displayed.
Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA
controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of
the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image
source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitors
analog inputs. It also provides the sync signals for the VGA monitor.

Figure 1. Example VGA Controller Implementation

The horizontal and vertical sync signals are 0V/5V digital waveforms that synchronize the
signal timing with the monitor. Being digital, they are provided directly by the FPGA (3.3V meets the
minimum threshold for a logical high, so 3.3V can be used instead of 5V).
The color magnitudes are 0V-0.7V analog signals sent over the R, G, and B
wires. (Alternatively, the green wire can use 0.3V-1V signals that incorporate both the horizontal and
vertical sync signals, eliminating the need for those lines. This is called sync-on-green and is not addressed
here.) The three color magnitude wires are terminated with 75 resistors. These lines are also terminated
with 75 inside the monitor. To create these analog signals, the FPGA outputs an 8-bit bus for each color to
a video DAC, in this example an ADV7123 from Analog Devices. This video DAC also requires a pixel
clock to latch in these values.
The VGA interface also specifies four wires that can be used to communicate with a ROM in
the monitor. This ROM contains EDID (extended display identification data), which consists of the
monitors parameters in a standard format. Several communication standards exist to access this data, but in
the simplest case, these lines can be left unconnected.

VGA Connector
VGA connections use a 15 pin connector called a DB15. Figure 2 shows the DB15 female receptacle. Table
1 lists the pinout for the connector.

Figure 2. VGA Female Connector (DB15 Receptacle)

Table 1. VGA Connector Pinout and Signals

Pin

Signal

Description

Connection

analog red, 0-0.7V

DAC output

analog green, 0-0.7V or 0.3-1V (if sync-on-green)

DAC output

analog blue, 0-0.7V

DAC output

EDID Interface

function varies depending on standard used

no connect

GND

general

GND

GND

for R

GND

GND

for G

GND

GND

for B

GND

no pin

or optional +5V

no connect

10

GND

for h_sync and v_sync

GND

11

EDID Interface

function varies depending on standard used

no connect

12

EDID Interface

function varies depending on standard used

no connect

13

h_sync

horizontal sync, 0V/5V waveform

FPGA output

14

v_sync

vertical sync, 0V/5V waveform

FPGA output

15

EDID Interface

function varies depending on standard used

no connect

VGA Signal Timing & Synchronization

There are a wide variety of standard VGA modes, each with a specific resolution and refresh
rate. Each mode has defined timing parameters. The VGA controller uses the GENERIC parameters
declared in the ENTITY to set all of the timing specifications except for the pixel clock, which must be
provided. The provided example implementation of the VGA controller uses a 1920x1200 resolution with a
60Hz refresh rate, which is the maximum resolution of the monitor used.

Pixel Clock
The VGA controller requires the user to provide the pixel clock. This can be brought into the FPGA on a
dedicated clock pin or can be derived inside the FPGA using a PLL.

Theory of Operation
Figure 3 illustrates the timing signals produced by the VGA controller. The controller
contains two counters. One counter increments on pixel clocks and controls the timing of
the h_sync (horizontal sync) signal. By setting it up such that the display time starts at counter value 0, the
counter value equals the pixels column coordinate during the display time. The horizontal display time is
followed by a blanking time, which includes a horizontal front porch, the horizontal sync pulse itself, and the
horizontal back porch, each of specified duration. At the end of the row, the counter resets to start the next
row.
The other counter increments as each row completes, therefore controlling the timing of the v_sync (vertical
sync) signal. Again, this is set up such that the display time starts at counter value 0, so the counter value
equals the pixels row coordinate during the display time. As before, the vertical display time is followed by
a blanking time, with its corresponding front porch, sync pulse, and back porch. Once the vertical blanking
time completes, the counter resets to begin the next screen refresh.
A display enable is defined by the logical AND of the horizontal and vertical display times.
Using these counters, the VGA controller outputs the horizontal sync, vertical sync, display enable, and pixel
coordinate signals. The sync pulses are specified as positive or negative polarity for each VGA mode. The
GENERIC parameters h_pol (horizontal polarity) and v_pol (vertical polarity) set the polarity of the VGA
controllers h_sync and v_sync outputs, respectively.

Horizontal blanking interval

Horizontal blanking interval refers to a part of the process of displaying images on a computer
monitor or television screen via raster scanning. CRT screens display images by moving beams of electrons
very quickly across the screen. Once the beam of the monitor has reached the edge of the screen, the beam is
switched off, and the deflection circuit voltages (or currents) are returned to the values they had for the other

edge of the screen; this would have the effect of retracing the screen in the opposite direction, so the beam is
turned off during this time. This part of the line display process is the Horizontal Blank.
In detail, the Horizontal blanking interval consists of:
front porch blank while still moving right, past the end of the scanline,
sync pulse blank while rapidly moving left; in terms of amplitude, "blacker than black".
back porch blank while moving right again, before the start of the next scanline. Colorburst occurs
during the back porch, and unblanking happens at the end of the back porch.

Vertical Blanking Interval

The vertical blanking interval (VBI), also known as the vertical interval or VBLANK, is the
time difference between the last line of one frame or field of a raster display, and the beginning of the first
line of the next frame. It is present in analog television, VGA, DVI and other signals. During the VBI the
incoming data stream is not displayed on the screen. In raster cathode ray tube displays, the beam is
blanked to avoid displaying the retrace line. The signal source, such as a television broadcast, does not
supply image information during the blanking period.

Figure 3. Signal Timing Diagram

Figue 4 : Signal Timing Synchorinisation

The vertical sync signal tells the monitor to start displaying a new image or frame, and the monitor
starts in the upper left corner with pixel (0,0).

The horizontal sync signal tells the monitor to refresh another row of 640 pixels

After 480 rows of pixels are refreshed with 480 horizontal sync signals, a vertical sync signal resets
the monitor to the upper left corner and the process continues

During the time when pixel data is not being displayed and the beam is returning to the left column to
start another horizontal scan, the RGB signals should all be set to black color (all zero)

In a PC graphics card, a dedicated memory location is used to store the color value of every pixel in
the display. This memory is read out as the beam scans across the screen to produce the RGB signals.

Horizontal scan rate

Horizontal scan rate, or horizontal frequency, usually expressed in kilohertz, is
the frequency at which a CRT moves the electron beam from the left side of the display to the right and back,
and therefore describes the number of horizontal lines displayed per second. CRT timings actually include
some horizontal scans before the visible display, after it, and during the travel from bottom to top (known as
vertical back porch, vertical front porch, and vertical sync width, respectively, and collectively known
as vertical blank time), so the horizontal scan rate does not directly correlate to visible display lines, unless
the unseen lines are also known, but it can still be used to approximate the display lines, as the total blank
time is usually a small but significant portion of the total lines. It is usually the most limiting factor of a CRT
display. This limit is due to how quickly the CRT's yoke can move the electron beam from one side of the
display to the other.
Compare vertical scan rate (refresh rate), which indicates how often the electron beam is
moved from the bottom of the display to the top. Given the horizontal scan rate, the refresh rate can be
approximated by dividing the horizontal scan rate by the number of horizontal lines multiplied by 1.05 (since
about 5% of the time it takes to scan the screen is spent moving the electron beam back to the top). For
instance, a monitor with a horizontal scanning frequency of 96 kHz at a resolution of 1280 x 1024 has a
refresh rate of 96,000 / (1024 x 1.05) 89 Hz (rounded down).

Figure 5 : Horizontal and vertical synchronization signals timing diagram for a 25.175 MHz clock

For most common VGA mode 640480 "60 Hz" non-interlaced the horizontal timings are:
Parameter

Value

Unit

Pixel clock frequency

25.175

MHz

Horizontal frequency

31.4686

kHz

Horizontal pixels

640

Total time for each line

31.77

Front porch (A)

0.94

Sync pulse length (B)

3.77

Back porch (C)

1.89

Active video (D)

25.17

(Total horizontal sync time 6.60 s)

The vertical timings are:

Parameter

Value

Vertical lines

480

Vertical frequency

59.94

Hz

Front porch (E)

0.35

ms

Sync pulse length (F)

0.06

ms

Back porch (G)

1.02

ms

Active video (H)

15.25

ms

(Total vertical sync time 1.43 ms)

Unit

Timing Specifications for Various VGA Modes

Resolution
(pixels)

Ref
resh
Rat
e
(Hz)

Pixel
Clock
(MHz)

Horizontal (pixel clocks)

Vertical (rows)

h_syn
c
Polari
ty

v_syn
c
Polari
ty

Disp
lay

Fron
t
Porc
h

Syn
c
Pul
se

Bac
k
Por
ch

Dis
pla
y

Front
Porch

Syn
c
Pul
se

Bac
k
Por
ch

640x350

70

25.175

640

16

96

48

350

37

60

640x350

85

31.5

640

32

64

96

350

32

60

640x400

70

25.175

640

16

96

48

400

12

35

640x400

85

31.5

640

32

64

96

400

41

640x480

60

25.175

640

16

96

48

480

10

33

640x480

73

31.5

640

24

40

128

480

29

640x480

75

31.5

640

16

64

120

480

16

768x576

75

45.51

768

40

80

120

576

22

768x576

85

51.84

768

40

80

120

576

25

800x600

60

40

800

40

128

88

600

23

800x600

75

49.5

800

16

80

160

600

21

1024x768

43

44.9

1024

176

56

768

41

1024x768

60

65

1024

24

136

160

768

29

1024x768

70

75

1024

24

136

144

768

29

1024x768

75

78.8

1024

16

96

176

768

28

1024x768

85

94.5

1024

48

96

208

768

36

1024x768

100

113.31

1024

72

112

184

768

42

1152x864

75

108

1152

64

128

256

864

32

1280x1024

85

157.5

1280

64

160

224

102
4

44