OBJECTIVE QUESTION IN MICROPROCESSOR

1. A byte corresponds to (a) 4 bits (b) 8 bits (c) 16 bits (d) 32 bits
2. The storage required for an image such as an X-ray is approximately (a) a few bytes (b)
a few hundred bytes (c) a few gigabytes (d) in the megabyte range.
3. A gigabyte represents (a) 1 billion bytes (b) 1000 kilobytes (c) 230 bytes (d) 1024 bytes
4. A megabyte represents (a) 1 million bytes (b) 1000 kilobytes (c) 220 bytes (d) 1024
bytes
5. A Kb corresponds to (a) 1024 bits (b) 1000 bytes (c) 210 bytes (d) 210 bits
2
6. A superscalar processor has (a) multiple functional units (b) a high clock speed (c) a
large amount of RAM (d) many I/O ports
7. A 32-bit processor has (a) 32 registers (b) 32 I/O devices (c) 32 Mb of RAM (d) a 32bit bus or 32-bit registers
8. Information is stored and transmitted inside a computer in (a) binary form (b) ASCII
code form (c) decimal form (d) alphanumeric form
9. The minimum number of bits required to store the hexadecimal number FF is (a) 2, (b)
4, (c) 8, (d) 16
10. A parity bit is (a) used to indicate uppercase letters (b) used to detect errors (c) is the
first bit in a byte (d) is the last bit in a byte
11. !A 20-bit address bus allows access to a memory of capacity (a) 1 Mb (b) 2 Mb (c)
32Mb (d) 64 Mb
12. A 32-bit address bus allows access to a memory of capacity (a) 64 Mb (b) 16 Mb (c) 1
Gb (d) 4 Gb
13.!Clock speed is measured in (a) bits per second (b) baud (c) bytes (d) Hertz

14. On-chip cache has (a) lower access time than RAM (b) larger capacity than off chip
cache (c) its own data bus (d) become obsolete
15. An FPU (a) makes integer arithmetic faster (b) makes pipelining more efficient (c)
increases RAM capacity (d) makes some arithmetic calculations faster
16. Pipelining improves CPU performance due to
(a) reduced memory access time (b) increased clock speed (c) the introduction of
parallellism (d) additional functional units
17. The system bus is made up of (a) data bus (b) data bus and address bus (c) data bus and
control bus (d) data bus, control bus and address bus
18. The von Neumann bottleneck is due to (a) mismatch in speed between secondary and
primary storage (b) mismatch in speed between the CPU and primary storage (c) slow speed
of I/O devices (d) low clock speeds
19. Cache memory enhances (a) memory capacity (b) memory access time (c) secondary
storage capacity (d) secondary storage access time
20. Cache memory (a) has greater capacity than RAM (b) is faster to access than CPU
registers (c) is permanent storage (d) faster to access than DRAM
21. A machine cycle refers to (a) fetching an instruction (b) clock speed (c) fetching,
decoding and executing an instruction (d)executing an instruction
22. CISC machines (a) have fewer instructions than RISC machines (b) use more RAM than
RISC machines (c) have medium clock speeds (d) use variable size instructions
23. RISC machines typically (a) have high capacity on-chip cache memories (b) have fewer
registers than CISC machines (c) are less reliable than CISC machines (d) typically execute
1 instruction per clock cycle.
24. CPU performance may be measured in (a) BPS (b) MIPS (c) MHz (d) VLSI
25. Modern processor chips may be classified as (a) LSI (b) ULSI (c) MIPS (d) SSI

26. Silicon chips are becoming more complex because (a) die size is decreasing (b) feature
size is decreasing (c) yield is increasing (d) the scale of integration is decreasing
27. Accessing disk storage is slower than accessing RAM by an order of (a) 10 (b) 100 (c)
1000 (d) 100,000

28. The typical disk storage capacity of a PC is of the order of (a) 32 MB (b) 2 Gb (c) 2 Tb
(d) 5120 Kb
29. Disk access takes of the order of (a) x millisecs (b) x microsecs (c) x/100 secs (d) x
nanosecs
30. RAM access takes of the order of (a) x millisecs (b) x microsecs (c) x/100 secs (d) x
nanosecs
31. Cache memory access takes of the order of (a) x millisecs (b) x microsecs (c) x secs (d)
x nanosecs
32. Accessing RAM is slower than accessing cache memory by an order of (a) 10 (b) 100
(c) 200 (d) 50
33. Optical tape storage (a) has faster access time than disk storage (b) smaller capacity than
CD-ROM (c) greater capacity than DAT storage (d) smaller capacity than DAT storage
34. DIP involves the use of a (a) scanner (b) plotter (c) microphone (d) CD-ROM
35. The typical RAM capacity of a PC is of the order of (a) 32 MB (b) 16 Gb (c) 16 Tb (d)
512 Kb
36. Modem speeds are measured in (a) bps (b) kbps (c) mbps (d) mips
37. In Synchronous data Transfer type both Transmitter and Receiver will operate in
a) Same Clock pulse
b) Different Clock pulse
c) None of the above

38. The term PSW Program Status word refers

a) Accumulator & Flag register
b) H and L register
c) Accumulator & Instruction register
d) B and C register

39. In 8085 the MAR, or .. register, latches the address from the program counte r. A bit later the MAR
applies this address to the , where a read operations performed
a) Memory address, ROM
b) Memory address, RAM
c) Memory address, PROM
d) Memory address EPROM

40. In micro processors like 8080 and the 8085, the ..cycle may have from one to live machine cycle
a) micro instruction
b) source program
c) instruction
d) fetch cycle

41. Repeated addition is one way to do multiplication, programmed multiplication is used in most
microprocessors because
a) that ALUs can only add and subtract
b) this saves on memory
c) a separate set of instructions is needed for the two
d) None of the above.

42. A is used to isolate a bit, it does this because that ANI sets all other bits to Zero
a) subroutine
b) flag
c) label
d) mask

43. Interaction between a CPU and a peripheral device that takes place during and imput output
operation is known as
a) handshaking
b) flagging
c) relocating
d) subroutine

44. Addressing in which the instructions contains the address of the data to the operated on is known
as
a) immediate addressing
b) implied addressing
c) register addressing
d) direct addressing

45. Resart is a special type of CALL in which

a) the address is programmed but not built into the hardware
b) the address is programmed built into the hardware
c) the address is not programmed but built into the hardware
d) None of the above

46. 8085 has software restarts and .. hardware restarts

a) 10, 5
b) 8,4
c) 7,5
d) 6,6

47. Serial input data of 8085 can be loaded into bit 7 of the accumulator by
a) executing a RIM instruction
b) executing RST1
c) using TRAP
c) None of the above

48. The address to which a software or hardware restart branches is known as

a) vector location
b) SID
c) SOD
d) TRAP

49. TRAP is ..whereas RST 7.5, RST 6.5, RST 5.5 are.
a) maskable, non maskable
b) maskable, maskable
c) non - maskable, non maskable

d) non - maskable, maskable

50. micro processor with a 16 bit address bus is used in a linear memory selection configuration
address bus lines are directly used as chip selects of memory chips with four memory chips. The
maximum addressable memory space is
a) 64K
b) 16 K
c) 8K
d) 4K
51. How many outputs are there in the output of a 10-bit D/A converter?
a) 1000
b) 1023
c) 1024
d) 1224

52. The stack is a specialized temporary access memory during .. and instructions
a) random, store, load
b) random, push, load
c) sequential, store, pop
d) sequential, push, pop

53. The memory address of the last location of a 1K byte memory chip is given as OFBFFH what will be
the address of the first location ?

a) OF817H
b) OF818H
c) OF8OOH
d) OF801H

54. What is the direction of address bus ?

a) Uni directional into microprocessors
b) Uni directional out of microprocessors
c) Bi directional
d) mixed direction is when lines into micro processor and some othe r out of micro
processes.
55. The No. of control lines are 56. The length of A register is - bits
57. The length of program counter is bits
58. The length of stack pointer is bits
59. The length of status word is - bit
60. The length of temporary register - bits
61. The length of Data buffer register - bits
62. The No. of flags are 63. The No. of interrupts are -

64. The memory word addressing capability is K

65. The No. of input output ports can be accessed by direct method 66. The No. of input output ports can be accessed by memory mapped method K
67. If instruction RST is written in a program the program will jump - location.
68. When TRAP interrupt is triggered program control is transferred to - location.

69. The RST 5.5 interrupt service routine start from location.
70. What is the purpose of using ALE signal high ?
a) To latch low order address from bus to separate A0 A7
b) To latch data Do D 7 from bus go separate data bus
c) To disable data bus latch

71. What is the purpose of READY signal?

a) It is used to indicate to user that microprocessor is workin g and ready to use
b) It is used to provide for proper WAIT states when microprocessor is communicating with slow
peripheral device.
c) It is used to provide for proper showing down of fast peripheral devices so as to communicate at
micro processors speed.

72. What is the addressing mode used in instruction MOV M, C?

a) Direct
b) Indirect
c) Indexed

d) Immediate
73. In 8085 the direction of address business is
a)bidirectional
b)unidirectional out of MP
c)unidirectional int MP
d)none of the above

74. In 8085 the hardware interrupts are

a)TRAP,RST 6.5,RST 7.5, RST 5.5 and INTR
b)RST o, RST 1..RST 7
c)both a b
d)none of the above

75. In the TRAP, RST 7.5, RST 6.5, RST 5.5, which is having top priority
a)TRAP
b)RST 7.5
c)RST 6.5
d)RST 5.5
76.In 8085 the no . of software interrupts are
a) 8
b)7
c)5

d)4
77. In the following interrupts which is the non-vectored interrupt
a)TRAP
b)INTR
c)RST 7.5
d)RST 6.5

78. Vector address for the TRAP interrupt is

a)0024 H
b)003C H
c)0034 H
d)002C H

79. In the following interrupt which is non-maskable interrupt

(a) Rst7.5
b) Rst 6.5
c) TRAP
d) INTR

79. Vector location Address for RST O Instruction is inflex

(a) ooooH
b) ooo8H

c) oo1oH
d)oo18H

80. In 8085 the Interput Acknowledge is represended by _______

(a) INTA
b)INTA
c) INTR
d) none of the above

81. The maximum number of I\o devices can be interfaced with 8085 in the I\o mapped I\o technique
are
a) 128
b) 256
c) 64
d) 1024

82. The maximum number of I\o devices which can be interfaced in the memory mapped I\o technique
are
a) 256
b) 128
c) 65536
d) 32768

83. Shadow Address will exist in

a) absolute decoding
b) linear decoding
c) partical decoding
d) none of the above

84. The Instructions used for data transfer in I\o mapped I\O are
a) IN, OUT
b) IN, LDA add
c) STA add
d) None of the above

85. Number of Address lines required to interface 1KB of memory are

a) 10
b)11
c) 12
d) 13