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Binary Multiplier

The document describes the design of a sequential binary multiplier circuit. It uses one adder and a shift register. The multiplication process starts with the multiplier and multiplicand loaded into registers. It then sequentially checks each bit of the multiplier and conditionally adds the multiplicand to a running partial product. The design steps include specifying the register operations and designing the control logic using a state diagram and table. The control logic is implemented using flip-flops, decoders and multiplexers to sequentially control the register operations based on the current state and inputs.

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HimeshParyani
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41 views

Binary Multiplier

The document describes the design of a sequential binary multiplier circuit. It uses one adder and a shift register. The multiplication process starts with the multiplier and multiplicand loaded into registers. It then sequentially checks each bit of the multiplier and conditionally adds the multiplicand to a running partial product. The design steps include specifying the register operations and designing the control logic using a state diagram and table. The control logic is implemented using flip-flops, decoders and multiplexers to sequentially control the register operations based on the current state and inputs.

Uploaded by

HimeshParyani
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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BINARY MULTIPLIER

To Multiply two unsigned binary numbers.


Sequential Multiplier

Uses one adder and a shift register.

Initially Multiplier in Q and Multiplicand in B


With S = 0 no action and circuit is in state T0
Multiplication process starts when S = 1 and
control goes to T1.
Register A and C set to 0 and counter P set to n,
the number of bits in multiplier.
System goes to T2.

Multiplier bit Q0 is checked and if = 1,


multiplicand B added to partial product A.
Carry from addition transferred to C
Partial product in A and C left unchanged if Q0 = 0

P decremented, next state is T3.


Registers CAQ shifted once to right

Design steps:
Design of register operations in the datapath
Design of control logic
Diamond boxes determine the conditions for
next state transition
Register transfer operations come from State
and Conditional boxes

In the design of control logic:


Establish required sequence of operations & provide
signals to control register transfer operations.

Sequence specified in state diagram


Signals for controlling register operations:
T1 ( for clearing A and C), T2 ( for decrementing P)
T3( for shifting CAQ), Q0 to decide whether to add B or not

Inputs S and Z, outputs T0, T1, T2, T3


L = T2Q0 to load sum into A if Q0 = 1 while in T2.

State assignment for control


State

Binary

T0
T1
T2
T3

00
01
10
11

Gray code
00
01
11
10

One-Hot
0001
0010
0100
1000

Control logic design using sequence register


and decoder
An n bit sequence register is a circuit with n
flip-flops
Multiplier having four states and two inputs
needs two flip-flops for the register and a 2:4
decoder for outputs

State Table:
Present
state
G1 G0

Inputs

0
0
0
1
1
1

0 X
1 X
X X
X X
X 0
X 1

0
0
1
0
1
1

Next
state
G1 G0
0
0
1
1
1
0

0
1
0
1
0
0

Outputs

T0 T1 T2 T3
1
1
0
0
0
0

0
0
1
0
0
0

0
0
0
1
0
0

0
0
0
0
1
1

Input columns have dont care entries whenever


the input variable is not used to determine the next state
Outputs are functions of present state, generated with a
Decoder with two inputs ( G1 G0) and four outputs ( T0 T3)

Next state of G1 is equal to 1


when the present state is T1,
when the present state is T2,
when the present state is T3, provided Z = 0
So we write:
DG1 = T1 + T2 + T3Z
Similarly:
DG0 = T0S + T2.

Use of One Hot assignment which uses one


Flip-flop per state
Single 1 propagates from one flip-flop to another
under the control of decision logic.
DT0 = T0S + T3Z
DT1 = T0S
DT2 = T1 + T3Z
DT3 = T2.

T1 ( for clearing A ,C and load P), T2 ( for decrementing P)


T3( for shifting CAQ), T2Q0 to decide whether to Load A or not

Design with Multiplexers


Combinational circuit can be implemented with
Multiplexers instead of gates.
Results in regular pattern of three level of
components.
1. Multiplexers that determine next state of register
2. Registers that hold the present state
3. Decoders that provide separate output for
control state
Predefined standard cell in many ICs.

State boxes left empty as it is only to design


Control sequence
Binary assignments specified at upper right corner
Decision boxes specify state transition as a function
of four control inputs w, x, y,z
Three level control implementation includes
MUX, registers and decoders

Multiplexer input conditions


Present Next
state
state
G1 G0 G1 G0
0 0 0 0
0 0
0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 1 0
1 0 1 1
1 1 0 1
1 1
1 0
1 1 1 1

Input
Inputs
conditions
MUX1
MUX2
w
w
0
w
x
x
1
x
y
yz
yz+yz = y
yz
yz
yz
y
yz
y + yz = y + z yz +yz =y

Design Example:
Count number of 1s in a register
Two registers R1 and R2 and Flip-flop E
System counts number of 1s in R1 and sets R2
to that number.
Done by shifting each bit in R1 one at a time
into E, E checked by control and if 1 R2 is
incremented.
Control uses external input S to start and
uses status input E and Z from datapath.
Z = 1 when R1 = 0

Multiplexer input conditions


Present Next
state
state
G1 G0 G1 G0
0 0
0 0
0 0
0 1

Input
conditions
S
S

Inputs
MUX1

MUX2

0 1
0 1

0
1

0
0

Z
Z

1 0

None

1 1
1 1

1 0
0 1

E
E

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