CMPE12

5) LC-3 Architecture
(Textbooks Chapter 4-ish)

The Stored-Program Computer

1943: ENIAC
Hard-wired program -- settings of dials and switches.

1944: Beginnings of EDVAC - Electronic Discrete

Variable Automatic Computer

among other improvements, includes program stored in memory

1945: John von Neumann

wrote a report on the stored-program computer,

known as the First Draft of a Report on EDVAC

CMPE12 Fall 2006 A. Di Blas (Orig. by C. Barzeghi)

First Draft of a Report on EDVAC

The basic structure proposed in the draft
became known as the von Neumann
machine (or model).
This machine/model had five main
components:
1. the Central Arithmetical part, CA
2. the Central Control part, CC
3. the Memory, M, for both
instructions and data
4. the Input, I
5. the Output, O
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Von Neumann Model*

MEMORY
MAR

MDR

INPUT
Keyboard
Mouse
Scanner
Disk

OUTPUT
PROCESSING UNIT
ALU

TEMP

Monitor
Printer
LED
Disk

CONTROL UNIT
PC

IR

* A slightly modified version of Von Neumanns original diagram

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CISC vs. RISC

CISC : Complex Instruction Set Computer
Lots of instructions of variable size, very memory
optimal, typically less registers.
RISC : Reduced Instruction Set Computer Less
instructions, all of a fixed size, more registers,
optimized for speed. Usually called a
Load/Store architecture.

CMPE12 Fall 2006 A. Di Blas (Orig. by C. Barzeghi)

What is Modern
For embedded applications and for
workstations there exist a wide variety of
CISC and RISC and CISCy RISC and RISCy
CISC.
Most current PCs use the best of both
worlds to achieve optimal performance.

CMPE12 Fall 2006 A. Di Blas (Orig. by C. Barzeghi)

LC-3 Architecture
o RISC - only 15 instructions
o 16-bit data and address
o 8 general-purpose registers (GPR)
Plus 4 special-purpose registers:
o Program Counter (PC)
o Instruction Register (IR)
o Condition Code Register (CC)
o Process Status Register (PSR)
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Memory
2 k x m array of stored bits:
Address
unique (k-bit) identifier of location
LC-3: k = 16
Contents
m-bit value stored in location
LC-3: m = 16
Basic Operations:
LOAD
read a value from a memory location
STORE
write a value to a memory location

CMPE12 Fall 2006 A. Di Blas (Orig. by C. Barzeghi)

address
0000
0001
0010
0011
0100
0101
0110
1101
1110
1111

00101101

10100010

contents

Interface to Memory
How does the processing unit get data to/from memory?
MAR: Memory Address Register
MEMORY
MDR: Memory Data Register
To LOAD from a location (A):
1. Write the address (A) into the MAR.
2. Send a read signal to the memory.
3. Read the data from MDR.

MAR

MDR

To STORE a value (X) into a location (A):

1. Write the data (X) to the MDR.
2. Write the address (A) into the MAR.
3. Send a write signal to the memory.

CMPE12 Fall 2006 A. Di Blas (Orig. by C. Barzeghi)

Input and Output

Devices for getting data into and
out of computer memory
Each device has its own interface,
usually a set of registers like the
memorys MAR and MDR

INPUT

OUTPUT

Keyboard
Mouse
Scanner
Disk

Monitor
Printer
LED
Disk

LC-3 supports keyboard (input) and monitor (output)

keyboard: data register (KBDR) and status register (KBSR)
monitor: data register (DDR) and status register (DSR)
Some devices provide both input and output
disk, network
The program that controls access to a device is usually called a driver.

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Instruction Fetch/Execute Cycle

In addition to input & output a program also:
Evaluates arithmetic & logical functions to determine
values to assign to variable.
Determines the order of execution of the statements in
the program.
In assembly this distinction is captured in the notion of
arithmetic/logical, and control instructions.

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Processing Unit
Functional Units
ALU = Arithmetic/Logic Unit
could have many functional units.
some of them special-purpose
(multiply, square root, )
LC-3 performs ADD, AND, NOT

PROCESSING UNIT
ALU

TEMP

Registers
Small, temporary storage
Operands and results of functional units
LC-3 has eight registers (R0, , R7), each 16 bits wide

Word Size
number of bits normally processed by ALU in one instruction
also width of registers
LC-3 is 16 bits

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Control Unit
Controls the execution of the program

CONTROL UNIT
PC

IR

Instruction Register (IR) contains the current instruction.

Program Counter (PC) contains the address of the next instruction to be
executed.

Control unit:
reads an instruction from memory
the instructions address is in the PC
interprets the instruction, generating signals that tell the other
components what to do
an instruction may take many machine cycles to complete
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LC-3
Can you
identify the 5
Von Neumann
components?

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Instructions
The instruction is the fundamental unit of work.
Specifies two things:
opcode: operation to be performed
operands: data/locations to be used for operation

Three basic kinds of instructions:

Computational instructions
Data-movement instructions
Flow-control instructions

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Breaking down an instruction

ADD

a, b, c

ADD

a b c

Source registers/immediate
Opcode
Destination register

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An instruction is encoded as a sequence of bits. (Like

data)

Often, but not always, instructions have a fixed length, such

as 16 or 32 bits.
Control unit interprets instruction:
generates sequence of control signals to carry out operation.
Operation is either executed completely, or not at all.

A computers instructions and their formats is known as

its Instruction Set Architecture (ISA).

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Instruction encoding
What meaning which bits have, depending on the
situation
Ex: in LC-3, the most-significant four bits contain
the instructions OPCODE always.
15 14 13 12

The meaning of the other bits changes according to

the instruction.
Look up the textbook to find all 16 LC-3 instruction
format descriptions
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Ex: LC-3s ADD Instruction

LC-3 has 16-bit instructions.
Each instruction has a four-bit opcode, bits [15:12].

LC-3 has 8 registers (R0-R7) for temp. storage.

Sources and destination of ADD are registers.

Add the contents of R2 to the contents of R6, and store the

result in R6.
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Ex: LC-3s LDR Instruction

Load instruction read data from memory
Base + offset mode:
add offset to base register - result is memory address
load from memory address into destination register

Add the value 6 to the contents of R3 to form a memory

address. Load the contents of that memory location to R2.
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Instruction Processing
Fetch instruction from memory
Decode instruction
Evaluate address
Fetch operands from memory
Execute operation
Store result
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Six basic phases of instruction processing:

F D EA OP EX S
NOTE:
Not all phases are needed by every
instruction
All instructions will go through F and D at
least
Phases may take more than 1 machine cycle
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FETCH
F

Load next instruction (at address stored in PC)

from memory into Instruction Register (IR).

Copy contents of PC into MAR.

Send read signal to memory.
Copy contents of MDR into IR.

Then increment PC, so that it points to the next

instruction in sequence.

EA
OP

PC becomes PC+1.

EX
S

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DECODE
First identify the opcode.
In LC-3, this is always the first four bits of
instruction.
A 4-to-16 decoder asserts a control line
corresponding to the desired opcode.

F
D
EA

Depending on opcode, identify other operands

from the remaining bits.
Example:
for LDR, last six bits is offset
for ADD, last three bits is second source
operand

OP
EX
S

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EVALUATE
ADDRESS
For instructions that require memory access,
compute address used for access.

F
D
EA

Examples:
add offset to base register (as in LDR)
add offset to PC
add offset to zero

OP
EX
S

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FETCH
OPERANDS
Obtain source operands needed to
perform operation.
Examples:
load data from memory (LDR)
read data from register file (ADD)

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F
D
EA
OP
EX
S

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EXECUTE
F
Perform the operation, using the source
operands.
Examples:

D
EA

send operands to ALU and assert ADD signal

do nothing (e.g., for loads and stores)

OP
EX
S

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STORE RESULT
Write results to destination.
(register or memory)
Examples:
result of ADD is placed in destination register
result of memory load is placed in destination
register
for store instruction, data is stored to memory
write address to MAR, data to MDR
assert WRITE signal to memory

F
D
EA
OP
EX
S

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Changing the Sequence of

Instructions
In the FETCH phase, we increment the Program
Counter by 1.
What if we dont want to always execute the
instruction that follows this one?
examples: loop, if-then, function call

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Flow-control instructions
We need special instructions that change the
contents of the PC.
These are the flow-control instructions:
jumps are unconditional -- they always change
the PC
branches are conditional -- they change the PC
only if some condition is true (e.g., the result of
an ADD is zero)

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Ex: LC-3 JMP

Set the PC to the value contained in a
register. This becomes the address of the
next instruction to fetch.

Load the contents of R3 into the PC.

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Recommended exercises:
Ex 4.5 (excluding point b3 for now)
Ex 4.7, 4.8, 4.10
Ex 4.13 and 4.16 (a little bit more advanced)

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