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Bicmos Logic Gates

This document discusses BiCMOS logic gates. It begins by explaining that BiCMOS achieves low standby power dissipation like CMOS but high speed and current drive capability like bipolar logic. It then notes that the disadvantage of BiCMOS is increased fabrication complexity compared to CMOS or bipolar logic. Notable examples of BiCMOS technology include Intel's Pentium Pro CPU from 1996. The document then discusses BiCMOS inverters and NAND gates. It explains that BiCMOS gates contain both CMOS and bipolar transistors to achieve the advantages of both. The document notes issues with reduced logic swings at lower supply voltages and describes various techniques to achieve full rail-to-rail operation in Bi

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Ravi Chandra Kumar
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249 views

Bicmos Logic Gates

This document discusses BiCMOS logic gates. It begins by explaining that BiCMOS achieves low standby power dissipation like CMOS but high speed and current drive capability like bipolar logic. It then notes that the disadvantage of BiCMOS is increased fabrication complexity compared to CMOS or bipolar logic. Notable examples of BiCMOS technology include Intel's Pentium Pro CPU from 1996. The document then discusses BiCMOS inverters and NAND gates. It explains that BiCMOS gates contain both CMOS and bipolar transistors to achieve the advantages of both. The document notes issues with reduced logic swings at lower supply voltages and describes various techniques to achieve full rail-to-rail operation in Bi

Uploaded by

Ravi Chandra Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BiCMOS Logic Gates

University of Connecticut

224

BiCMOS - Best of Both Worlds?


n
n

CMOS circuitry exhibits very low power dissipation, but


Bipolar logic achieves higher speed and current drive capability.

BiCMOS achieves low standby dissipation like CMOS, but high


speed and current drive capability like TTL and ECL.

The disadvantage of BiCMOS is fabrication complexity (up to 30


masking steps, compared to about 20 for bipolar logic or
CMOS). This translates into higher cost and longer design
cycles.
$

Notable examples of the BiCMOS technology are the Intel P6


(a.k.a. Pentium Pro) which appeared in 1996, and its successor
the P7.

University of Connecticut

225

BiCMOS Inverter
VDD

P1

QP
N3

VOUT
VIN

N1

P1 and N1 perform the logic


function.
QP and QO are lowimpedance output drivers.
N2 and N3 remove base
charge from the bipolar
transistors during switching.

QO
N2

University of Connecticut

226

BiCMOS Inverter
VDD

VIN = 0.

P1
QP
N3
VOUT
VIN

N1

QO

VIN = V DD.

N2

University of Connecticut

227

BiCMOS Inverter VTC


VOUT

3.0

The BiCMOS inverter shown


here exhibits reduced logic
swing (VDD - 2VBEA) compared
to CMOS (VDD).
Reduction of the supply
voltage will make this problem
more severe.

CMOS

BiCMOS

2.0

V DD = 3.3V

1.0

K = 40 A / V 2 VT = 1V
F = 50 VBEA = 0.7V
0.0
0.0

1.0

2.0

3.0

VIN
University of Connecticut

228

BiCMOS NAND Gate


VDD
PA

With both inputs high:

PB
QP
NB3
NA3
VOUT

VB
VA

With VA high, VB low:

NB1
NA1

QO
N2

University of Connecticut

229

How Fast is BICMOS?


n

VDD
P1
QP
N3
VOUT
VIN

N1

QO
N2
n

University of Connecticut

For highly-capacitive off-chip


loads, fast switching is possible
due to the high current driving
capability of the bipolar
transistors. The speed is limited
by the parasitic capacitances of
the QP, which must be driven by
the P1 - N3 CMOS circuit.
For on-chip loads presenting very
little capacitance, BiCMOS offers
no advantage if
CL < C BCP
BiCMOS integrated circuits are
really CMOS on the inside!

230

BiCMOS Applications
n
n

Modern BiCMOS, invented by Intel, hit the market in 1992.


Ever-increasing clock frequencies on motherboards of PCs and
workstations may require that the VLSI / ULSI chips be made in
BiCMOS. (Witness the Intel, AMD, and Cyrix P chips.)
Central Processing Units (CPUs) of minisupercomputers can
be implemented in BiCMOS, with packing density and
dissipation advantages over ECL. (e.g., the Cray Research
Baby Cray J916 Computer)
TTL will soldier on in motherboard SSI and MSI applications,
where BiCMOS does not boast an advantage.
But the BiCMOS party may be over when supply
voltages drop below 1.8 V. BJTs have a fixed turn-on
voltage; MOSFET thresholds can be reduced to at least
0.3V for room temperature operation.

University of Connecticut

231

The Problem with BiCMOS


n
n

For standard BiCMOS, the logic swing is VDD - 2VBEA.


Supply voltages are continually being reduced, because
2
P C LVDD

When VDD is reduced to 1.8V, standard BiCMOS will provide a


logic swing of only 0.4V; this isnt acceptable! We can provide
shunt elements which increase the voltage swing of BiCMOS,
but
Turning off the BJTs isnt the answer! If the supply voltage is
1.8V, the BJTs can only conduct for
0.7 V VOUT 1.1V

In this case the BJTs can not effectively boost the switching
speed.

University of Connecticut

232

Full-Rail BiCMOS Inverter w/


Resistive Shunts
VDD
P1
QP
R1

VIN

N1

QO
R2

University of Connecticut

VOUT

This BiCMOS design provides a


rail-to-rail voltage swing.
For VOUT < VBEA, N1 and R2
conduct, bringing VOL all the way to
0.
For VBEA < VOUT < VDD - VBEA, one
or both BJTs conducts.
For VDD - VBEA < VOUT, P1 and R1
conduct, bringing VOH all the way to
VDD.
It is not practical to fabricate this
circuit with resistors, but a similar
circuit can be made using an active
shunt for QO.

233

BiCMOS Inverter w/ Active Shunt


VDD
P1
QP
VOUT
N3
VIN

N1

This BiCMOS design provides a


voltage swing of VDD - VBEA.
For VOUT < VBEA, N3 and N2
conduct, bringing VOL all the way to
0.
For VBEA < VOUT < VDD - VBEA, one
or both BJTs conducts.
The base-emitter junction of QP is
not shunted, so VOH = VDD - VBEA.

QO
N2

University of Connecticut

234

Full Rail BiCMOS Inverter w/


Paralleled CMOS Output
VDD
PO
P1
QP
N3
VOUT
VIN

N1

QO
N2

The parallel CMOS


inverter provides rail-to-rail
operation.
For VOUT < VBEA, NO
conducts, bringing VOL all
the way to 0.
For VBEA < VOUT < VDD VBEA, one or both BJTs
conducts.
For VDD - VBEA < VOUT, PO
conducts, bringing VOH all
the way to VDD.

NO
University of Connecticut

235

Buffered CMOS

University of Connecticut

236

CMOS - Single Stage


tOX = 100 Angstroms

VDD = 1.8V
VT = -0.6V
2.2 m/ 0.5 m

VIN
VT = 0.6V
0.9 m/ 0.5 m

k P' = 80 A / V 2
VOUT

k N' = 200 A / V 2

CL

tP =

A=

University of Connecticut

237

CMOS - Single Stage / 50pF


VDD = 1.8V
VT = -0.6V
2.2 m/ 0.5 m

VIN
VT = 0.6V
0.9 m/ 0.5 m

VOUT

KP =
KN =

50pF

tP =

University of Connecticut

238

CMOS - Three Stages / 50pF


VDD = 1.8V
2.2/ 0.5

11/ 0.5

55/ 0.5

0.9/ 0.5

4.5/ 0.5

22/ 0.5

VOUT

VIN

50pF

K1 =
C L1 =

K2 =
CL 2 =

C L3 =

tP1 =

tP 2 =

tP3 =

K3 =

tP =
University of Connecticut

239

CMOS - Six Stages / 50pF


VDD = 1.8V
2.2/ 0.5

11/ 0.5

55/ 0.5

VIN
0.9/ 0.5

4.5/ 0.5

22/ 0.5

K3 =

K1 =
C L1 =

K2 =
CL 2 =

C L3 =

tP1 =

tP 2 =

tP3 =

University of Connecticut

WIRED
TO THE
NEXT
PAGE!

240

CMOS - Six Stages / 50pF


VDD = 1.8V
275/ 0.5
WIRED
FROM THE
PREVIOUS
PAGE!

K4 =
CL 4 =
tP 4 =

110/ 0.5

1375/ 0.5

6875/ 0.5

550/ 0.5

2750/ 0.5

K5 =

K6 =

C L5 =

C L6 =

t P5 =

tP6 =

VOUT

50pF

tP =
University of Connecticut

241

GaAs Direct-Coupled FET Logic


(DCFL)

University of Connecticut

242

DCFL Inverter

VDD

VOUT
VIN

University of Connecticut

DCFL gates are similar to NMOS


circuits, but are implemented with GaAs
MESFETs rather than Si MOSFETs.
The advantage of DCFL is speed - it
is up to 3 times faster than CMOS.
The disadvantages of DCFL are
fabrication complexity and cost.
GaAs 75 mm wafer - $100
Si 200 mm wafer - $10
Si 300 mm wafers - coming soon!
GaAs technology is less
established compared to Si
technology, and the fabrication of
enhancement type MESFETs is
difficult.
243

DCFL Inverter - Basic Operation


VIN = LOW.
VDD
NL
VOUT
VIN

University of Connecticut

NO

VIN = HIGH.

244

DCFL NOR Gate


VA = VB = VOL.
VDD
NL
VOUT
VA

NOA

VB

NOB

VA = VDD or VB = VDD.

DCFL NAND gates are not practical due to restrictions imposed on VDD, VOL,
and the enhancement device threshold voltages.

University of Connecticut

245

Buffered DCFL NOR Gate


VDD

VOUT
VA

VB

VA

VB

The added source follower provides a low-impedance output driver for off-chip
loads.

University of Connecticut

246

DCFL Characteristics
Compare the 1999 state-of-the art for GaAs DCFL and Si CMOS:
GaAs DCFL vs. Si CMOS: 0.25 m technology
GaAs DCFL

Si CMOS

propagation delay

35 ps

75 ps

dissipation

30 W (DC)

1 W / MHz

SRAM embedded in VLSI

32 kB

128 kB

GaAs exhibits higher electron mobility than Si.


Due to the GaAs electron velocity characteristic, DCFL can operate
at a reduced supply voltage without a penalty in switching speed.
University of Connecticut

247

DCFL Applications
n

For a given minimum linewidth, GaAs DCFL circuitry is about 2


to 3 times faster than Si CMOS because of the difference in
electron mobilities.
The extra speed comes at a premium, because GaAs
technology is less developed and DCFL is expensive.
DCFL applications are at the high end, where the extra cost can
be justified. Examples are the Cray Y-MP and the Vitesse
Semiconductor GaAs microprocessor, which boasts 1.2 M
transistors [see Ira Deyhimy, Gallium Arsenide Joins the Giants, IEEE
Spectrum, pp. 33-40, February 1995].
At the present time, the area of fastest growth for GaAs DCFL is
communications.
A factor of three isnt much, though, when you consider the rapid
advancement of Si CMOS / BiCMOS technology.

University of Connecticut

248

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