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Module 6 Layout Hierarchy Concept

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55 views

Module 6 Layout Hierarchy Concept

ecectroni

Uploaded by

Muhammad Syameer
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Module 6 Layout Hierarchy Concept

Learning
Outcome

At the end of this unit, participants will


Know what hierarchy and instance arrays are.
Be able to traverse hierarchy using schematic and layout
tools.
Be able to create and remove hierarchy in layout.

Introduction

For today design capacity with millions of transistor, it is almost


impossible to carry out the implementation with a flat hierarchy
design. In order to improve the design cycle throughput time,
hierarchy concept is widely used.

Hierarchy

Hierarchy - different levels of layout on a chip


o Country state county city neighborhood
o Chip cluster unit block cell
Instance - a cell placed within another cell
o Perak is an instance of a state
o Intel is an instance of a corporation
Child Cell - cell contained in larger cell is child of that cell
Parent Cell - cell containing smaller cells is parent of those cells
Hierarchy organizes & simplifies complexity

Block diagram
of hierarchy

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


Layout
representation
of hierarchy

Schematic and
layout
hierarchy

Hierarchy is usually determined by schematic design


o Hierarchy should make sense for layout
o Suggest modifications if necessary
o Schematic organization of logic follows layout design
Schematic and Layout hierarchy should match
o Simplifies use of design and verification tools:
o Allows verification to be run at intermediate levels
o Verification runtimes are faster
o Easier to get parasitic data back into simulations
o Easier to complete ECO (Engineering Change Order)

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


What is array?

Array - ordered instantiation (placement) of same cell or objects in a


design
o Object can be a cell, group of cells, or other structure
o Objects are related, physically and logically
o Array can extend in X and/or Y direction
Flipping each alternate instance is the mirror image in X and/or Y
direction of the original cell
Stepping the distance between neighboring instances
o User can specify stepping (counted from origin to origin of
instances)
Row vs column row horizontal, column vertical

Stepped Cells

The example below shows multiple cell instances placed with the
same orientation (no flipping) and same distance between neighbors.
The origin of the instantiated cell is determined by the small triangle
in the lower left corner.
o Origin at X:0, Y:0 of child cell
Example: 6x1 array of cell circuit

Stepped Cells
with space

This example shows multiple cell instances placed with the same
orientation, without flipping but with stepping. Notice the equal
distance between each cell.
Example: 4x1 array of cell circuit

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


Flipped Cells

This example shows multiple cell instances placed with the same
orientation, with flipping and no stepping
Example: 5x1 array of cell circuit

Example of gate array layout

Basic hierarchy
planning

This is included
Understanding constraints
Basic Wire Planning
Block Sizing Fundamentals
Block Placement Fundamentals
Datapath Definition
Basic Datapath Pitch Planning
Estimating Layout Time

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


Understand the
constraints

Basic Wire
Planning

When creating a wire plan, you need to:


Include all the input and output pins on your block.
Include all the M2/M3/M4 feed thru to your block.
Include shielding if needed.
Plan to have two or more power lines in larger-pitch cells.
Use the standard line pitch for signals and power lines (unless they
are specified differently).
Plan to share tracks when possible.

Interface signals
Critical signals
Metal allocations
Schedule

Keep in mind, when parallel lines are routed at minimum design rule
widths, there is no room to make a connection to the upper layer due to
metal overlap requirements for the via.
Avoid making unnecessary jogs in routing (i.e. if a wire can go straight
it should). This will help performance and area.
Your wire plan specifies the tracks needed for your over-the-cell
routing, in conjunction with your port definitions.
You need a wire plan to see if your fab will be metal-limited and to reserve
room for over-the-cell routing. Make sure this is planned before starting
layout.

Block sizing
fundamentals

The area required by a design is determined by the number of transistors


device-limited or by the interconnects metal-limited.

If device-limited, the area is based on transistor density. The


density is found by multiplying the number of transistors by the
area needed for one transistor (in sq. mils/device).

If metal-limited, the cells area is determined by the total number


of line pitch.

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


Block
placement
fundamentals

Datapath

Place blocks efficiently using the least amount of routing. This is


especially important for critical nets.
The Clock driver should be placed close to the clock input.
If available, use the Layout Planner as a template to start placing
your blocks.
Utilize track-sharing and use the cross-reference file to understand
how the blocks relate to each other.

Datapath describes layout that has the chips data buses running
through it and being used in it, in a bit-slice fashion.

Data busses are large (up to 86 bits for floating point), and typically
use arrays to implement the logic; one cell is created, and then
instantiated for each data bit.

Unique inputs and outputs to particular cell positions (bits) are usually
handled with ports.

Making the right connections at the upper levels is called


programming.

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


Basic datapath
pitch planning

In planning a datapath pitch (cell width), the pitch will usually be


determined by the widest cell.

It is desirable to match pitches through different parts of the chip to


reuse common layout (for example, adders).

Pitches usually fall in the range between 25 and 60 microns. Outside


these values, the aspect ratios become inefficient and/or cumbersome
to use.

Datapath Pitch Planning Process:


o Obtain a cross-reference file for all your blocks.
o Have Wire planning and Cell pitch sizing ready.
o Dont skimp on power line widths.
o If the pitch seems too narrow for an efficient layout, you can
always upsize it. Dont go any smaller than the worst-case pitch.
o Be creative.

CMOS VLSI Layout Design

Module 6 Layout Hierarchy Concept


Estimating
layout time

Plan the layout before estimating the schedule.


Determine your priorities: is getting the job done quickly or is
density* more important for this project?
75 devices/week is an example of productivity factor from Wmt
project. The actual number depends on the type of layout (Datapath
vs. Control vs. Ram) and the layout tools used.
Do not include your planning time here because Layout and Planning
are two different tasks. You should have a plan ready before you can
begin to estimate the layout time.

DESIGN

PLANNING

Design is a creative activity


whose aim is to establish the
multi-faceted qualities of
objects, processes, services and
their systems in whole life
cycles. Therefore, design is the
central factor of innovative
humanisation of technologies
and the crucial factor of cultural
and economic exchange.

A basic management function


involving formulation of one or
more detailed plans to achieve
optimum balance of needs or
demands with the available
resources.
The planning process
(1) identifies the goals or objectives
to be achieved,
(2) formulates strategies to achieve
them,
(3) arranges or creates the means
required, and
(4) implements, directs, and
monitors all steps in their proper
sequence.

CMOS VLSI Layout Design

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