Scribd
Upload
237 views

Variable Entered Maps

The document describes mapping rules for VEM mapping. It presents three versions of the mapping rules: Version 1 maps 1's to don't cares and ensures all entries are mapped. Version 2 converts 1's to a format matching adjacent map variables and uses don't cares freely. Version 3 confirms the two solutions are equivalent by expanding them to a 4-variable non-VEM map, with the only difference being a don't care value which is unimportant.

Uploaded by

solai12sunny
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
237 views

Variable Entered Maps

The document describes mapping rules for VEM mapping. It presents three versions of the mapping rules: Version 1 maps 1's to don't cares and ensures all entries are mapped. Version 2 converts 1's to a format matching adjacent map variables and uses don't cares freely. Version 3 confirms the two solutions are equivalent by expanding them to a 4-variable non-VEM map, with the only difference being a don't care value which is unimportant.

Uploaded by

solai12sunny
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 11

VEM mapping rules A

Map rules (Version 1)


1.
2.
3.
4.
5.

Map 1s
Convert 1s to dont cares (X)
Map LIKE entries
Use dont cares in any manner
Ensure that ALL entries are mapped

P
0

done

Q
0

done

1 ready

Q
0
1s to Xs

1 ready

out

Q done

Q ready

6
Software Design

VEM mapping rules B




Map rules (Version 2)


1.
2.
3.
4.

Convert 1s to ( a + A ) format that matches adjacent map entered variables


Map LIKE entries
Note
Use dont cares in any manner
1 = done + done
Ensure that ALL entries are mapped

1 = ready + ready
P
0

out

P
1

0 done

1 ready

P done

Q
0

done + done

done

1 ready

Q done

Q ready

Software Design

VEM mapping rules C




Are the two solutions the same ????????

Version 2

out =

P done

Version 1

out =

+ Q done + Q ready

+ Q done +

??????

Q ready

OK
P

PQ
00
done ready

P
0

0 done

1 ready

11

10

00

01

11

10

ready

Expanding to a 4-variable
Non-VEM map

01

done

Q
3

Software Design

VEM mapping rules C




Are the two solutions the same ????????


out =

Version 2

P done

PQ
00
done ready

P
Q

+ Q done + Q ready

0
0 done
1 ready

1
1
X

Expanding to a 4-variable
Non-VEM map

P
01

11

10

00

01

11

10

ready
done

Software Design

VEM mapping rules C




Are the two solutions the same ????????


Version 1

out =

Q ready

PQ
00
done ready

P
0

+ Q done +

0 done

1 ready

Expanding to a 4-variable
Non-VEM map

P
01

11

00

01

11

10

ready

The difference is the DONT CARE (X) square


P Q ready done
However, this is not a problem as it is dont
care.

10

done

Both solutions are equivalent


Version 1 is more efficient

Software Design

Asynchronous signals


Asynchronous input signals


clock
Input signal edge
not related to
clock edges

No assumption can be made as to when an asynchronous


input signal will occur


Signal can often only be defined in terms of probability




Input signal

E.g. a keyboard signal

Special circuits called synchronisers can be used to convert


an asynchronous input signal to a synchronous input signal

Software Design

Synchronizer circuit

Asynchronous
input
FF2

FF1

input signal

output signal

clock

Synchronized
signal
Global lowskew clock

Software Design

Assignment of state codes




The state codes can be allocated in any way, but must adhere
to one rule
Asynchronous variable rule

State
variables

1.

There should never be more than 2 states


from a state whose branching is controlled
by an asynchronous input variable

2.

The two next states MUST have logically


adjacent states

DE
00

State
codes

Asynchronous
input

a
00

b
01

c
11

d
10

From state a, next states b and c are adjacent.


i.e. only differ by D
8

Software Design

No race condition

Next
state
logic

DD

QD

Next
state
logic

DE

QE

clock

Software Design

Assignment of state codes




The state codes can be allocated in any way, but must adhere
to 1 rule
Asynchronous variable rule

DE
00

1.

There should never be more than 2 states


from a state whose branching is controlled
by an asynchronous input variable

2.

The two next states MUST have logically


adjacent states

Asynchronous
input

a
00
P

P
b
01

c
10

d
11

D
0

From state a, next states b and c are NOT adjacent.


i.e. differ by D and E
10

Software Design

Race condition


If P changes at the same time as the clock edge then state


outputs will be unpredictable

Routes of race
condition

Next
state
logic

DD

QD

Next
state
logic

DE

QE

Delay
causes race
clock
11

Software Design

System design


Digital system consist of two cooperating units





Data
Control
Data in

Data
manipulation

Control signals

control

Control signals

Data out

E.g. A computer, a graphics card, an ethernet interface, etc


12

Software Design

Data manipulation components




The components available to the designer include




Registers
Counters

Shift registers

Multplexors

Up, down
Left, right
Also called data selectors

De-multiplexors
 Comparators
 Arithmetic units


Adders, subtractors, incrementors, multipliers, ALUs

At design time it is important to see these blocks as BLACK BOXES





Their individual design can be decided at a later stage


Need only define inputs and outputs




Direction
Polarity
Level or edge

13

Software Design

Data manipulation components




Register



Also called a latch


Simple digital value store (memory location)

Data inputs
n wires

load

register

Output enable

n wires

Data outputs
+ve Edge
triggered
Optional
connection

14

Software Design

Data manipulation components




Counter

Data inputs
n wires

load

clock

counter
Up/down

Output enable
n wires

Data outputs

15

Software Design

Data manipulation components




Shift register



Allows serial to parallel and parallel to serial conversions


three types
Serial in  serial out
Serial in  parallel out
 Parallel in  serial out



parallel inputs
Left/right
Serial in

n wires

Output enable

Shift register
load

n wires

Serial out
clock

parallel outputs

16

Software Design

Data manipulation components




Multiplexer


Allows switching of many inputs to one output

Output enable

m wires
m wires

2n
inputs

multiplex

m wires

1
output

m wires
n wires

select

17

Software Design

Data manipulation components




De-multiplexor


Allows switching of one input to many outputs

Output enable

m wires

1
input

m wires

De multiplex

m wires

2n
outputs

m wires
n wires

select

18

Software Design

Data manipulation components




comparator

Output enable

m wires

Input A

A=B
A<B
A>B

Comparator

m wires
A=5

Input B

A = 2,3,4,7

etc

19

Software Design

Data manipulation components




Arithmetic unit


General purpose
Output enable

m wires

Input A

m wires

ALU

Arithmetic result

m wires

Carry/borrow/etc

Input B

Result = 0
Result > 0
Result < 0

Operation select

20

Software Design

10

Data manipulation components




Arithmetic unit


Simple adder

Output enable

m wires

Input A

m wires

adder

Arithmetic result

m wires

Carry

Input B

21

Software Design

11

You might also like