Verilog HDL Simulation Labs

Overview
The Verilog simulation labs in this course are designed to maximize your hands-on
introduction to Verilog coding. Therefore, you are asked to create all hardware
modules and testbenches from scratch. After finishing these labs, you will gain the
level of coding skill, syntax proficiency, and understanding that can only be
achieved through meaningful practice and effort.
ost of the early lab exercises are standalone tasks that reinforce and illustrate
language concepts that are fundamental to all Verilog coding.
Objectives
After completing these labs, you will be able to!
" #rite $T% descriptions for simple circuits
" &reate a structural Verilog description for simple circuits
" 'uild hierarchy by using Verilog
" &reate a Verilog testbench to verify the hierarchical structure created in the
previous steps
" (se the simulation software
" &reate basic input stimulus
" $un a simulation
Labs Outline
%ab )! 'uilding *ierarchy
%ab +! ,imulation-Verification
%ab .! n-bit 'inary &ounter
%ab /! &omparator
%ab 0! Arithmetic %ogic (nit 1A%(2
+
Lab 1: Building Hierarchy
3n this lab, you will write a complete $T% description for the modules 45A67+
and 458$+ and build the circuit shown below 19igure )2 in a structural Verilog
description of the top-level module A6758$.
9igure )
This lab comprises three primary steps! 4ou will create a software pro:ect; write
$T% descriptions; and check the syntax of your $T% code.
Lab 2: SimulationVeri!ication
3n this lab, you will write a Verilog testbench for the AND_OR module completed
in the previous exercise. As part of the testbench, you will create a simple input
stimulus by using both concurrent and se<uential statements.
=xamine the circuit below 19igure +2. 3n this lab, you will write a complete Verilog
testbench description for the module AND_OR.
9igure +
.
8(T)
36>?+@
36>?A@
36>?)@
36>?.@
"o# level: $%D&O' 45A67+
()
45A67+
(1
458$+
(2
S*+1
S*+2
This lab comprises four primary steps! 4ou will create a new pro:ect and import
Verilog source files; create a testbench with the Verilog testbench wizard in the
simulation software; create initial and always input stimulus statements; and,
finally, verify the logic structure and functionality by running a simulation and
examining the resulting waveforms.
Lab ,: n-bit Binary .ounter
3n this lab, you will write a complete $T% description for the module CNTR by
using parameter statements to specify the bit width. This is an n-bit binary,
up-down, loadable counter, with active-%ow asynchronous reset. 4ou will then
build a Verilog *7% testbench to verify the functionality of the $T% code as well
as the hardware it models.
=xamine the circuit below 19igure .2. 3n this exercise, you will create a fully
functional binary counter that can be dynamically scaled to any length. The use of
parameter statements is an important tool for module reuse and source code
readability. The circuit is an n-bit binary, up-down loadable counter, with active-
%ow asynchronous reset.
9igure .
/
D_IN Q_OUT
RST
CE
LOAD
UpDn
CLK
CNTR
This lab comprises three primary steps! 4ou will create a software pro:ect; declare
the parameter statements; and, finally, create a testbench to verify the design.
&reate the input stimulus!
). ,et the .LO./ input to toggle at a rate of 100 MHz
+. Assert the '0S0" input at time 15 ns, hold for 25 ns, then de-assert
.. ,et the .0 input initially High, de-assert 1set Lw2 at time !00, hold for 100 ns"
reassert
/. ,et the LO$D input initially Lw, toggle High at time 500 ns, for one full clock
cycle
0. ,et (>76 to initially High, then Lw at time #50 ns
B. ,et the D&*% input value to $%h0& or CDb00001111
Lab 1: .om#arator
3n this lab, you will write description for the module COM' 1,ynchronous
&omparator2 using an i()else statement.
=xamine the circuit below 19igure /2!
9igure /
This lab comprises four primary steps! 4ou will create a software pro:ect; create an
$T% version of COM'; and, finally, create a testbench to verify that the behavioral
model functions correctly.
0
3f the expected result and the data are e<ual, the result is T$(=; otherwise, the
result is 9A%,=.
7eclarations of input and output are shown in the following table!
>ort %abel %ength 7escription
enable )bit 3nput; enable the comparator
expected / bit 3nput; expected output
data / bit 3nput; actual output;
result ) bit 8utput; result of comparison
clk ) bit &lock input
Lab 2: $rithmetic Logic (nit 3$L(4
3n this lab, you will write a complete $T% description for the module AL*. The
op-codes and functionality of the synchronous AL* is described below.
3nputs 8utputs
A536 1/ bit 2 8(T>(T 1/ bit2
'536 1/ bit 2
8>&87= 1/ bit 2
&%E
=6A'%=
(se a case statement to describe the functionality for the AL* as shown in the
following table, which shows the +,L,CT-ON O'COD, and the
operation-function for each. 7o not forget the =6A'%= input.
8>&87=
,. ,+ ,) ,A 8peration 9unction
F
A A A A
4 G A Transfer
A A A )
4 G A H ) 3ncrement
A A ) A
4 G A H ' Addition
A A ) )
4 G A H ' H ) Addition and 3ncrement
A ) A A
4 G A H 1I' 2 Add H )s comp
A ) A )
4 G A H 1I ' 2 H ) ,ubtraction
A ) ) A
4 G A J ) 7ecrement
A ) ) )
4 G A and ' A67
) A A A
4 G A or ' 8$
) A A )
4 G A xor ' K8$
) A ) A
4 G I A &ompliment
) A ) )
4 G A Transfer As
Table! ,=%=&T386 8>&87=
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