TIMING ANALYSIS OF A SYNCHRONOUS SEQUENTIAL CIRCUIT 239

can also be written as

(r-reg+l)=unsigned (m)
Since the r,req+l operation is needed for incrementing operation, we can use it in com-
parison and eliminate the decrementor. The revised VHDL code is shown in Listing 8.16.
Listing 8.16 More efficient description of a programmable mod-rn counter
archi t ect ure two-seg-effi-arch of prog-counter i s
si gnal r-reg : unsigned ( 3 downto 0) ;
si gnal r-next , r-inc : unsigned(3 downto 0) ;
begin
5 - r e g i s t e r
process (clk, reset)
begin
i f (reset=l) then
r-reg <= ( ot he r s => O ) ;
r-rag <= r-next;
10 e l s i f (clkevent and clk=l) then
end i f ;
end process;
-- ne xt - s t at e l o g i c
IS r-inc <= r-reg + 1;
r-next <= ( ot he r s => O ) when r-inc=unsigned(m) e l s e
-- o u t p u t l o g i c
q <= std-logic-vector(r-reg);
20 end two-seg-eff i-arch;
r-inc ;
Note that we employ a separate statement for the shared expression:
r-inc <= r-reg + 1;
and use the r-inc signal for both comparison and incrementing. The diagram of the revised
code is shown in Figure 8.14(b).
8.6 TIMING ANALYSIS OF A SYNCHRONOUS SEQUENTIAL CIRCUIT
The timing of a combinational circuit is characterized primarily by the propagation de-
lay, which is the time interval required to generate a stable output response from an input
change. The timing characteristic of a sequential circuit is different because of the con-
straints imposed by memory elements. The major timing parameter in a sequential circuit
is the maximal clock rate, which embeds the effect of the propagation delay of the combina-
tion circuit, the clock-to-q delay of the register and the setup time constraint of the register.
Other timing issues include the condition to avoid hold time violation and VO-related timing
parameters.
8.6.1 Synchronized versus unsynchronlred input
Satisfying the setup and hold time constraints is the most crucial task in designing a sequen-
tial circuit. One motivation behind synchronous design methodology is to group all FFs
together and control them with the same clock signal. Instead of considering the constraints
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240 SEQUENTIAL CIRCUIT DESIGN: PRINCIPLE
of tens or hundreds of FFs, we can treat them as one memory component and deal with the
timing constraint of a single register.
The conceptual diagram of Figure 8.5 can be considered as a simplified block diagram for
all synchronous sequential circuits. In this diagram, FFs and registers are grouped together
as the state register. The input of this register is the statenext signal. It is generated
by next-state logic, which is a combinational logic with two inputs, including the external
input and the output of the state register, st at ei eg. To study the timing constraint of the
state register, we need to examine the impact of the two inputs of the next-state logic. Our
discussion considers the following effects:
0 The effect of the s t at ei eg signal.
0 The effect of synchronized external input.
0 The effect of unsynchronized external input.
Since the st at ereg signal is the output of the state register, it is synchronized by the
same clock. A closed feedback loop is formed in the diagram through this signal. The timing
analysis of a synchronous sequential circuit focuses mainly on this loop and is discussed in
Section 8.6.2 .
A synchronized external input means that the generation of the input signal is controlled
by the same clock signal, possibly from a subsystem of the same design. The timing
analysis is somewhat similar to the closed-loop analysis describe above, and is discussed
in Section 8.6.5.
An unsynchronized external input means that the input signal is generated from an
external source or an independent subsystem. Since the system has no information about
the unsynchronized external input, it cannot prevent timing violations. For this kind of
input, we must use an additional synchronization circuit to synchronize the signal with the
system clock. This issue is be discussed in Chapter 16.
8.6.2 Setup time violation and maximal clock rate
In Figure 8.5, the output of the register is processed via next-state logic, whose output
becomes the new input to the register. To analyze the timing, we have to study the operation
of this closed feedback loop and examine the s t at ei eg and statenext signals. The
st at ei eg signal is the output of the register, and it also serves as the input to the next-state
logic. The statenext signal is the input of the register, and it is also the output of the
next-state logic.
Maximal clock rate The timing diagram in Figure 8.15 shows the responses of the
st at ereg and statenext signals during one clock cycle. At time t o, the clock changes
from 0 to 1. We assume that the statenext signal has stabilized and doesnt change
within the setup and hold time periods. After the clock-to-q delay (i.e., Tcp), the registers
output, st at ei eg, becomes available at time tl, which is t o + Tcq. Since s t at ei eg
is the input of the next-state logic, the next-state logic responds accordingly. We define
the propagation delays of the fastest and slowest responses as Tnezt(min) and Tnezt(maz)
respectively. In the timing diagram, the statenext signal changes at t z . which is tl +
Tnezt(min), and becomes stabilized at t 3 , which is tl + Tnezt(maz). At time t 5 , a new rising
clock edge arrives and the current clock cycle ends. The statenext is sampled at t 5 and
the process repeats again. t 5 is determined by the period (T,) of the clock signals, which is
t o + Tc.
Now let us examine the impact of the setup time constraint. The setup time constraint
indicates that the statenext signal must be stabilized at least Tsetvp before the next
TIMING ANALYSIS OF A SYNCHRONOUS SEQUENTIAL CIRCUIT 241
Figure 8.15 Timing analysis of a basic sequential circuit.
sampling edge at t 5 . This point is labeled t 4 in the timing diagram. To satisfy the setup
time constraint, the st at enext signal must be stabilized before t 4. This requirement
translates into the condition
t 3 t 4
From the timing diagram, we see that
t 3 = t o + Tcq + Tnezt(maz)
and
We can rewrite the inequality equation as
t 4 = t 5 - Tsetup = t o + Tc - Tsetup
t o + Tcq + Tnezt(maz) < t o + Tc - Tsetup
which is simplified to
This shows the role of the clock period on a sequential circuit. To avoid setup time violation,
the minimal clock period must be
Tcq + Tnezt(maz) + Tsetup < Tc
Tc(min) = Tcq + Tnezt(rnaz) + Tsetup
The clock period is the main parameter to characterize the timing and performance of a
sequential circuit. We commonly use the maximal clock rate or frequency, the reciprocal
of the minimal period, to describe the performance of a sequential circuit, as in a 500-MHz
counter or 2-GHz processor.
242 SEQUENTIAL CIRCUIT DESIGN: PRINCIPLE
Clock rate examples For a given technology, the Tcq and Tsetup of a D FF are obtained
from the data sheet. We can determine the maximal clock rate of a sequential circuit once the
propagation delay of the next-state logic is known. This information can only be determined
after synthesis and placement and routing. However, we can calculate and estimate the rate
of some simple examples.
Assume that we use the technology discussed in Section 6.2.6, and Tcq and Tsetup of its
D FF cell are 1 and 0.5 ns respectively. The delay information of combinational components
can be obtained from Table 6.2. Let us first consider the free-running shift register of
Section 8.5.2. The next-state logic of the shift register only involves the routing of the input
and output signals. If we assume that the wiring delay is negligible, its propagation delay
is 0. The minimal clock period and maximal clock rate become
-- - x666.7MHz
1
fmax =
Tcq + Tsetup 1.5 ns
Clearly, this is the maximal clock rate that can be achieved with this particular technology.
The second example is an 8-bit free-running binary counter, similar to the 4-bit version of
Section 8.5.4. The next-state logic of this circuit is the incrementor, as shown in Figure 8.12.
If we choose the incrementor that is optimized for area, the clock rate for this %bit binary
counter is
x 256.4 MHz
1
- -
1
fmax =
Tcq + TS-bit-inc(area) + Tsetup
1 ns + 2.4 ns 0.5 ns
If we increase the size of the counter, a wider incrementor must be utilized, and the propa-
gation delay of the incrementor is increased accordingly. The clock rate of a 16-bit binary
counter is reduced to
1
x 142.9 MHz
- -
1
fmax =
Tcq + TlG-biLznc(area) Tsetup
1 ns + 5.5 ns + 0.5 ns
and the clock rate of a 32-bit counter is reduced to
To increase the performance of a binary counter, we must reduce the value of Tcq +
Tnezt(max) + Tsetup. Since Tcq and Tsetup are determined by the intrinsic characteristics
of FFs, they cannot be altered unless we switch to a different device technology. The only
way to increase performance is to reduce the propagation delay of the incrementor. If we
replace the incrementors that are optimized for delay, the clock rates of the 8-, 16- and
32-bit binary counters are increased to
x 333.3 MHz
1
- -
1
fmax =
Tcq -k TS-biLinc(delay) + Tsetup
1 ns 1.5 ns $. 0.5 ns
1
1 nS + 3.3 nS + 0.5 ns
- -
1
Tcq -k T16-bit-inc(delay) + Tsetup
1
Tcq 4- T32-bit-znc(delay) + Tsetup
fmax =
and
1
1 ns + 7.5 ns + 0.5 ns
- -
fmaz =
respectively.
M 208.3 MHz
x 111.1 MHz
TIMING ANALYSIS OF A SYNCHRONOUS SEQUENTIAL CIRCUIT 243
8.6.3 Hold time violation
The impact of the hold time constraint is somewhat different from the setup time constraint.
Hold time, Thold, is the time period that the input signal must be stabilized after the sampling
edge. In the timing diagram of Figure 8.15, it means that the st at enext must be stable
between t o and t h, which is t o +Thold. Note that the earliest time that st at enext changes
is at time t 2. To satisfy the hold time constraint, we must ensure that
th < t2
From the timing diagram, we see that
t 2 = t o + Tcq + Tnert(min)
and
The inequality becomes
t h = t o + Thold
to -k Thold < t o + Tcq + Tnezt(mzn)
which is simplified to:
Tnezt(min) depends on the complexity of next-state logic. In some applications, such as
the shift register, the output of one FF is connected to the input of another FF, and the
propagation delay of the next-state logic is the wire delay, which can be close to 0. Thus,
in the worst-case scenario, the inequality becomes
Thold < Tcq + Tnezt(min)
Thold < Tcq
Note that both parameters are the intrinsic timing parameters of the FF, and the inequality
has nothing to do with the next-state logic. Manufacturers usually guarantee that their
devices satisfy this condition. Thus, we need not worry about the hold time constraint
unless the clock edge cannot arrive at all FFs at the same time. We discuss this issue in
Chapter 16.
8.6.4 Output-related timing considerations
The closed feedback diagram in Figure 8.5 is the core of a sequential system. In addition,
there are also external inputs and outputs. Let us first consider the output part of the circuit.
The output signal of a sequential circuit can be divided into the Moore-typed output (or just
Moore output) and Mealy-typed output (or just Mealy output). For Moore output, the output
signal is a function of system state (i.e., the output of the register) only. On the other hand,
for Mealy output, the output signal is a function of system state and the external input. The
two types of output can coexist, as shown in Figure 8.16. The main timing parameter for
both types of outputs is Tco, the time required to obtain a valid output signal after the rising
edge of the clock. The value of Tco is the summation of Tcq and TWtpt (the propagation
delay of the output logic); that is,
Tco = Tcq + Toutput
For Mealy output, there exists a path in which the input can affect the output directly. The
propagation delay from input to output is simply the combinational propagation delay of
output logic.
244 SEQUENTIAL CIRCUIT DESIGN: PRINCIPLE
next-state
logic
external
input
clk
2
MOOm
external
input
clk
Figure 8.16 Output circuits of a sequential circuit.
Mealy
output
Moore
output
I
subsystem 2
Figure 8.17 Input timing of two synchronous subsystems.
8.6.5 Input-related timing considerations
In a large design, a system may contain several synchronous subsystems. Thus, it is possible
that 'an input comes from a subsystem that is controlled and synchronized by the same clock.
The block diagram of this situation is shown in Figure 8.17. Note that the two subsystems
are controlled by the same clock and thus are synchronous. At the rising edge of the clock,
the register of subsystem 1 samples a new input value. After Tco(systeml), its new output,
which is the input for the next-state logic of subsystem 2, becomes available. At this point
the timing analysis is identical to that in Section 8.6.2. To avoid setup time violation, the
timing of the two circuits must satisfy the following condition:
Tco(syatern1) + Tnezt(maz) f Tsetup Tc
Note that Tnezt(maz), the propagation delay of next-state logic, is somewhat different
from the calculation used in Section 8.6.2. The Tnezt(rnaz) here is the propagation delay
ALTERNATIVE ONE-SEGMENT CODING STYLE 245
from the external input to statenext, whereas Tnezt ( maz) used in earlier minimal clock
period calculation in Section 8.6.2 is the propagation delay from the internal register out-
put (i.e., statereg) to statenext. To be more accurate, we should separate the two
constraints. The constraint for the closed loop is
Tcq + Tnezt (max of statereg-to-state-next) + Tsetup < 1
and the constraint for the external input is
Tco(system1) + Tnezt (max of ext-input-to-state-nezt) + Tsetzlp < Tc2
We usually determine the clock period based on the calculation of Tcl. If Tc2 turns out to
be greater than Tc l , we normally redesign the I/O buffer rather than slowing down the clock
rate of the entire system. For example, we can employ an extra input buffer for the external
input of subsystem 2. Although this approach delays the external input by one clock cycle,
it reduces the Tco(systeml) to T,, in the second constraint.
8.7 ALTERNATIVE ONE-SEGMENT CODING STYLE
So far, all VHDL coding follows the basic block diagram of Figure 8.5 and separates the
memory elements from the rest of the logic. Alternatively, we can describe the memory
elements and the next-state logic in a single process segment. For a simple circuit, this
style appears to be more compact. However, it becomes involved and error-prone for more
complex circuits. In this section, we use some earlier examples to illustrate the one-segment
VHDL description and the problems associated with this style.
8.7.1 Examples of one-segment code
D FF with enable Consider the D FF with an enable signal in Listing 8.7. It can be
rewritten in one-segment style, as in Listing 8.17.
Listing 8.17 One-segment description of a D FF with enable
archi t ect ure one-seg-arch of dff-en is
begin
process (clk ,reset)
begin
5 i f (reset=l) then
q < = O ;
i f (en=l) then
e l s i f (clkevent and clk=l) then
q <= d;
10 end i f ;
end i f ;
end proces s ;
end one-seg-arch ;
The code is similar to a regular D FF except that there is an if statement inside the elsif
branch:
i f (en=I) then
end i f ;
q <= d;