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Hardware Flow Chart: Virendra Singh

This document provides details about the hardware implementation of a CISC architecture processor. It includes a block diagram showing the major components like the control store, instruction decoder, datapath, and buses. It also includes a hardware flowchart explaining how instructions are executed step-by-step through the datapath controlled by the microcode in the control store. Examples of instruction sets and datapaths for a minimal processor are also presented to help explain the concepts.

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Parmanand Khajuriya
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98 views

Hardware Flow Chart: Virendra Singh

This document provides details about the hardware implementation of a CISC architecture processor. It includes a block diagram showing the major components like the control store, instruction decoder, datapath, and buses. It also includes a hardware flowchart explaining how instructions are executed step-by-step through the datapath controlled by the microcode in the control store. Examples of instruction sets and datapaths for a minimal processor are also presented to help explain the concepts.

Uploaded by

Parmanand Khajuriya
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CISC

Architecture II
Hardware Flow Chart
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE-309: Microprocessors

Lecture 21 (02 Sep 2014)

CADSL

Micro-coded Implementation
Bus Controller

Clock-Phase Generator
Instruction
Sequencer

Control
Store

Instruction
Decoder

Encoded Control Word Fields

Instruction
Prefetch
Register

Control Word Decoder


Decoded Datapath Control

Address
Out Reg.

Internal A Bus
PC

R0

Datapath

02 Sep 2014

R1

Rn

Shifter

ALU

Internal B Bus

EE-309@IITB

Data
Reg.

CADSL

Instruction Execution
ADD R1, D2(B2)
5A
0

R1
8

B2
12

D2
16

31

v The second operand is added in the rst


v The sum is placed in the rst operand locaBon
v The operand and the sum are treated as 16-bit signed binary
integers
v The rst operand is in the register specied by the R1 eld
v The second operand is in the memory address is calculated
by adding the displacement specied by the D2 eld to the
content of the base register specied by the B2 eld
02 Sep 2014

EE-309@IITB

CADSL

Execution Steps
Steps for ADD instrucBon ExecuBon
1. Fetch the rst half word
2. Find ADD control word sequence
3. Fetch the remaining instrucBon word
4. Calculate the operand address
5. Fetch the operand
6. Add
7. Store the result
02 Sep 2014

EE-309@IITB

CADSL

Execution Steps
1. Fetch the remaining instrucBon word
2. Calculate the operand address
3. Fetch the operand
4. Add
5. Store the result
6. Update the program counter
7. Fetch the rst half word for the next instrucBon
8. Find the address of the next instrucBons control word
sequence
9. Branch to the next instrucBons control word
02 Sep 2014

EE-309@IITB

CADSL

Execution Steps
1. Fetch the remaining instrucBon word
One state to second half of the ADD instrucBon

2. Calculate the operand address


One state to add D2 displacement and the content of the B2
register

3. Fetch the operand


One state to fetch the data half word (put the address on the pads
and wait for the operand half-word)

4. Add
One state to add the operands

5. Store the result


One state to store the result in Register R1
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EE-309@IITB

CADSL

Execution Steps
6. Update the program counter
One state to increament PC
One state to save the incremented value

7. Fetch the rst half word for the next instrucBon


One state to put the PC value on the pads and wait for the rst half
of the next instrucBon

8. Find the address of the next instrucBons control word


sequence
One state to put the next instrucBon into the instrucBon decoder

9. Branch to the next instrucBons control word


Zero state this step is accomplished as a part of the previous step
02 Sep 2014

EE-309@IITB

CADSL

Processor - Block Diagram


Clock-Phase
Generator

Reset & Power-On Logic

Next State
Control

Control
Store

Interrupt Logic

Bus Controller

IR
Decoder

Branch Control
unit

Encoded Control Word Fields

Instruction
Prefetch
Register

Control Word Decoder


Decoded Datapath Control

Address
Out Reg.

PC
Datapath

02 Sep 2014

R0

R1

Internal A Bus

Rn

Shifter

ALU

Internal B Bus

EE-309@IITB

Data
Reg.

CADSL

Hardware Flowchart

02 Sep 2014

EE-309@IITB

CADSL

Hardware Flowchart
Hardware Flowchart
Tells us how to get from the architecture to the
implementaBon
Links programmers (external) model and the
hardware (internal) implementaBon
Specify exactly how commands from the
instrucBon set are carried out using Datapath

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EE-309@IITB

10

CADSL

Flowchart Objective

Limit controller size to some fracBon of


chip area
Make CPU as fast as possible
Complete the project as early as possible
Make the owcharts easy to translate into
hardware
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11

CADSL

Example: MIN Instruction Set


Instruction Format

Programmers
Register Set

First Word
Op-code
Operation
Code

Rx
First
Operand
Register

Mode
Second
Operand
Address
Mode

R0
R1
R2

Ry
First
Operand
Register

.
.
.

Second Word
Rn

Displacement
Optional, depending on second operand address mode

02 Sep 2014

EE-309@IITB

12

CADSL

MIN Instruction Set

ADD
AND
BZ Branch if zero bit is set. (Register Indirect only)
LOAD Second operand is source and Rx is desBnaBon
POP PosBncrement with register indirect only
PUSH Predecrement with register indirect only
STORE
SUB
TEST
02 Sep 2014

EE-309@IITB

13

CADSL

MIN Instruction Set


Second Operand Address
Mode

Ry

Second Operand
Address Mode

First Operand
Register

Address Modes
AB - Base (Ry) plus displacement (second instrucBon
word) is an operand address
AI Register indirect. Ry holds an operand address
AR Register direct: The result is stored in Ry. For two
operand instrucBons, Ry also is an operand source
02 Sep 2014

EE-309@IITB

14

CADSL

MIN Datapath
IRE

IRF

Internal A Bus

AO

PC

T2

R0

R1

DO
Rn

T1

ALU

DI

Internal B Bus

External Data

External Address

Bus (EDB)

Bus (EAB)

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CADSL

MIN Datapath
Rules of OperaBon
1. A transfer from source to bus to desBnaBon takes one state
Bme
2. A source can drive up to three desBnaBon loads
3. Inputs to the ALU are from A (internal) bus and either k
(values 0, +1, -1) or the B (internal) bus
4. When ALU is desBnaBon. T1 is automaBcally loaded from
the ALU output
5. A transfer to AO acBvates the on-chip external bus
controller. This bus controller postpones the next state unBl
the external transfer is complete.
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16

CADSL

Flowcharts
ADD RX AR RY

ADD RX AI (RY)

Register-to-Register
R R
ADD

Register-to-Memory
R M
ADD

rx a alu
ry b alu

edb di
ry b ao

di b alu
rx a alu

t1 b ry

IRE

AO PC T2

R0 R1

Internal A
Bus
Internal B
Bus

02 Sep 2014

ALU

Sequence

ry b ao
t1 a do

IRF
DO

Rn T1

State

k
DI

EE-309@IITB

17

CADSL

Thank You
02 Sep 2014

EE-309@IITB

18

CADSL

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