Design for Test of Digital Systems

TDDC33








Lab Instructions



















Date of last revision 27/08/2008


2007

Anders Larsson, IDA/SaS ESLAB
0 TDDC33 Design for Test of Digital Systems
Table of content

1. Introduction ........................................................................................................................... 2
1. Introduction ........................................................................................................................... 2
2. Initial preparations................................................................................................................. 3
3. Synthesis................................................................................................................................ 4
3.1. Input ............................................................................................................................... 4
3.2. Output............................................................................................................................. 4
3.3. Synthesis procedure ....................................................................................................... 4
4. Design for test using DFTAdvisor ........................................................................................ 6
4.1. Input ............................................................................................................................... 6
4.2. Output............................................................................................................................. 6
4.3. Starting DFTAdvisor...................................................................................................... 6
4.4. Circuit Setup .................................................................................................................. 7
4.5. Test Synthesis ................................................................................................................ 8
4.6. Save results .................................................................................................................. 11
5. Fault Coverage Analysis and Test Pattern Generation using FlexTest ............................... 13
5.1. Input ............................................................................................................................. 13
5.2. Output........................................................................................................................... 13
5.3. Writing test patterns ..................................................................................................... 13
5.4. Starting FlexTest .......................................................................................................... 14
5.5. Circuit setup ................................................................................................................. 15
5.6. Fault simulation............................................................................................................ 15
5.7. Test pattern generation................................................................................................. 17
5.8. Results and analysis ..................................................................................................... 18
6. Test point insertion in VHDL.............................................................................................. 20
6.1. Input ............................................................................................................................. 20
6.2. Output........................................................................................................................... 20
6.3. Inserting test points ...................................................................................................... 20
7. Board test using Boundary Scan (IEEE 1149.1) ................................................................. 21
7.1. Input ............................................................................................................................. 21
7.2. Output........................................................................................................................... 21
7.3. Starting Trainer1149 .................................................................................................... 21
7.4. How to use Trainer1149............................................................................................... 21
7.5. Introducing a fault ........................................................................................................ 22
7.6. Writing and verifying a test program using the Test Constructor................................ 23
7.7. Writing and verifying a test program using the TAP Controller.................................. 25
References ............................................................................................................................... 31

TDDC33 Design for Test of Digital Systems 1
1. Introduction
This document describes the environmental setup and the tools needed to complete the lab
assignments in the course TDDC33 Design for Test of Digital Systems. The tools that are
used in this course are listed in Table 1. For the synthesis, automatic test pattern generation
(ATPG), and design for test (DFT), the core cells from AMS 0.35m [1] standard cell library
will be used together with the test library c35_CORELIB.atpg. A design named s27 will be
used as an example throughout these instructions. The s27 design is described in VHDL
(s27.vhdl) and stored in a directory named s27_test. The name of the design and the directory
will later be changed as you solve the lab assignments.
The rest of this document is organized as follows. Chapter 1 contains information about the
how to setup the system in order to start the tools. The following chapters, Chapter 2 to
Chapter 7, contain instructions for the synthesis, DFT, test pattern generation, test point
insertion, and board testing, respectively.

Table 1: Covered tools
Task Tool Tool vendor
Synthesis Leonardo Spectrum (Mentor Graphics)
Design for test DFTAdvisor (Mentor Graphics)
Test pattern generation FlexTest (Mentor Graphics)
Boundary scan Trainer1149 (Testonica)

TDDC33 Design for Test of Digital Systems 2
2. Initial preparations
The following commands are all executed in a terminal window.

Add the modules /mentor/dft_2005 and mentor/fpgadv if they are missing.
List the available loaded modules.
module list

Add the modules. Note that the order of these commands is important.
module add prog/mentor/dft_2005
module add prog/mentor/fpgadv

Note! Previously loaded mentor modules must be unloaded. If these modules are
loaded by default at login, the login-file (.login) should be changed.

Make a directory s27_test
mkdir s27_test

Download and extract the required files. (Described in the labs)
Download the labx.tar.gz file where x is the number of the lab
gunzip labx.tar.gz
tar xvf labx.tar
Copy the following files to the s27_test directory:
c35_CORELIB.atpg
fflop.vhd
gates.vhd
s27.vhdl

Set the environment variable MODEL_TECH
setenv MODEL_TECH /sw/mentor/fpgadv/6.2/Modeltech/bin

Generate the work directory
$MODEL_TECH/vlib work

Compile the vhdl files
$MODEL_TECH/vcom -93 fflop.vhd
$MODEL_TECH/vcom -93 gates.vhd
$MODEL_TECH/vcom s27.vhdl
TDDC33 Design for Test of Digital Systems 3
3. Synthesis
This chapter describes the synthesis procedure using Leonardo Spectrum from Mentor
Graphics. It is assumed that the initial preparations, described in the Initial preparations, have
been made.
3.1. Input
A compiled VHDL-file
3.2. Output
A synthesised EDF-file
3.3. Synthesis procedure
Start the synthesis program from a command prompt
leonardo &
Click on OK

In the Quick Setup tab
Select library file:
technology->ASIC->AMS->c35_CORELIB

Select input file
Input->Open files: Select the vhdl file (s27.vhd)

Select the name of the output file
s27.edf

In the Advanced tab
Output -> Format->EDIF

In the Quick Setup tab
Check that the Optimize Effort is set to Fastest Runtime
Check that the output filename is correct

Start synthesis
Run Flow
Check the results from the synthesis in the Exemplar.log file
Check that the EDF file (s27.edf) was generated
TDDC33 Design for Test of Digital Systems 4

Figure 1 Synthesis setup
TDDC33 Design for Test of Digital Systems 5
4. Design for test using DFTAdvisor
This chapter describes how scan chain insertion is implemented using DFTAdvisor from
Mentor Graphics.
4.1. Input
A design netlist
An ATPG library
4.2. Output
A new design netlist
Command file (do-file)
4.3. Starting DFTAdvisor
Start the synthesis program from a command prompt
dftadvisor &

In the DFTAdvisor Welcome window illustrated in Figure 2.
Select the design
Select the ATPG Library


Figure 2. DFTAdvisor Welcome window.

Click on Invoke DFTAdvisor

DFTAdvisor has one command-based interface and one graphical interface. In this
description we will mainly used the graphical interface, which is shown in Figure 3. The
textual interface is useful for the verification of the results after the execution of commands.

TDDC33 Design for Test of Digital Systems 6

Figure 3. DFTAdvisor Control Panel.
4.4. Circuit Setup
Specify the clocks
In the Control Panel
Click on Clocks

In the Setup Circuit Clocks window, illustrated in Figure 4.
Check Manually Define
Select the clock H and the Off-State 0
Click on Add
Click on OK

Figure 4. Setup Circuit Clocks window.

In the Control Panel
Click on DRC and Circuit Learning

TDDC33 Design for Test of Digital Systems 7
The Control Panel will, after leaving the Setup mode, change appearance and look as
illustrated in Figure 5.


Figure 5. Control Panel in Test Synthesis mode.
4.5. Test Synthesis
Specify the type of scan.
In the Test Synthesis Control Panel
Click on Setup Identification

Perform the following steps in the Setup for Scan and Test Point Identification window,
illustrated in Figure 6.
TDDC33 Design for Test of Digital Systems 8
Select the type of scan (Full Scan or Partial Scan)
If Partial Scan is selected
o Click on Setup A new window will appear where details about the partial
scan may be specified as illustrated in Figure 7.
o Specify the number of scan cells that should be scanable.
o Click on Done.
Click on OK.


Figure 6. Setup for Scan and Test Point Identification window.


Figure 7. Setup for Partial Scan window.

TDDC33 Design for Test of Digital Systems 9
In the Test Synthesis Control Panel
Click on Run Identification.

In the window named Use Existing Settings or Customize?
Click on Run with Existing Settings.

The results (the number of identified scanable cells) will be presented in the DFTAdvisor
Identification Run Statistics window as illustrated in Figure 8.


Figure 8. Identification Run Statistics window.

Click on Dismiss

In the Test Synthesis Control Panel
Click on Setup/Run Test Synthesis

The Setup/Run Test Synthesis window will appear as illustrated in Figure 9.

TDDC33 Design for Test of Digital Systems 10

Figure 9. Setup/Run Test Synthesis window

Check Synthesize Scan Circuitry into the Design
Click on Setup

The Scan Synthesis Setup window will appear as illustrated in Figure 10.


Figure 10. Scan Synthesis Setup window

Click on Done
Click on OK
Click on Run with Existing Settings
4.6. Save results
On the right hand side of the Control Panel.
Click on Save Results
TDDC33 Design for Test of Digital Systems 11
The Save Results window will appear as illustrated in Figure 11.


Figure 11. Save Results window.

Check Save the New Nelist
Select Format: EDIF
Specify a new filename
Click on ATPG Setup

The Save Results window will appear as illustrated in Figure 12.


Figure 12. Save Results window for ATPG Setup.

Check Save Setup Files for ATPG
Specify the Basename.
Click on OK

TDDC33 Design for Test of Digital Systems 12
5. Fault Coverage Analysis and Test Pattern
Generation using FlexTest
This chapter describes the fault coverage analysis and test pattern generation process using
FlexTest from Mentor Graphics. It is assumed that the initial preparations, described in
Chapter 1, have been made.
5.1. Input
A design netlist
An ATPG library
External test patterns (optional)
Command files; dofile and testproc file (optional)
5.2. Output
Test patterns
Fault coverage
5.3. Writing test patterns
Manually crafted test patterns should be written in a text file using the following format:
Combinational design (not the s27 design)
SETUP =
TEST_CYCLE_WIDTH = 1;
DECLARE INPUT BUS "ibus" = "/INP(0)", "/INP(1)", "/INP(2)",
"/INP(3)", "/INP(4)";
DECLARE OUTPUT BUS "obus" = "/OUTP(0)", "/OUTP(1)";
END;
CYCLE_TEST =
PATTERN = 0;
CYCLE = 0;
FORCE "ibus" "01100" 0;
MEASURE "obus" "11" 1;
PATTERN = 1;
CYCLE = 0;
FORCE "ibus" "10010" 0;
MEASURE "obus" "00" 1;
END;

Sequential design (could be the s27 design)
SETUP =
TEST_CYCLE_WIDTH = 3;
DECLARE INPUT BUS "ibus" = "/H", "/INP(0)", "/INP(1)", "/INP(2)",
"/INP(3)";
DECLARE OUTPUT BUS "obus_3" = "/OUTP(0)";
CLOCK "/H" =
OFF_STATE = 0;
END;
END;

CYCLE_TEST =
CYCLE = 0;
FORCE "ibus" "01111" 0;
FORCE "ibus" "11111" 1;
FORCE "ibus" "01111" 2;
MEASURE "obus_3" "1" 3;
TDDC33 Design for Test of Digital Systems 13
CYCLE = 1;
FORCE "ibus" "01100" 0;
FORCE "ibus" "11100" 1;
FORCE "ibus" "01100" 2;
MEASURE "obus_3" "1" 3;
END;
5.4. Starting FlexTest
Start the synthesis program from a command prompt
flextest &

In the FlexTest Welcome window
Select the design
Select the ATPG Library
Select the Command File (optional)

If scan insertion have been made in a previous step where a command file was generated.
Select the command file

An example of the FlexTest Welcome window is presented in Figure 13.
Start FlexTest.


Figure 13 FlexTest welcome window.
Click on Invoke FlexTest

FlexTest has one command-based interface and one graphical interface. In this description we
will mainly use the graphical interface, which is shown in Figure 14.
TDDC33 Design for Test of Digital Systems 14

Figure 14. FlexTest graphical interface
5.5. Circuit setup
Specify the clocks
In the Control Panel
Click on Clocks

In the Setup Circuit Clocks window
Check Manually Define
Select the clock H and the Off-State 0
Click on Add
Click on OK

In the Control Panel
Click on DRC and Circuit Learning

In the Session Purpose window
Click on Pattern Generation or Fault Simulation
5.6. Fault simulation
After circuit setup, design rule check and circuit learning the fault simulation control panel
appears as shown in Figure 15. Using this panel you can either generate test patterns for the
specified design or load pre-defined test patterns for fault simulation.


TDDC33 Design for Test of Digital Systems 15

Figure 15 FlexTest fault simulation control panel

Specify external test patterns
In the Control Panel
Click on Pattern Source

In the Setup Pattern Source window
Check External Patterns From
Select the file with the external patterns
Check Ascii
Click on OK

Select the type of faults to detect
In the Control Panel
Click on Fault Universe

In the Setup Fault Universe window
Fault Model -> Check Single Stuck-At
Create a Fault List -> Check Add Faults to ALL DESIGN OBJECTS
Fault Type -> Check Both of the Above (Stuck-at 0 and Stuck-at 1)
Click on OK

Run the fault simulation
In the Control Panel
Click on Fault Simulation
Click on Run with Existing Settings
Check Run ALL Test Cycles
Click on Run

How the results can be analyzed is described in Section 5.8.

TDDC33 Design for Test of Digital Systems 16
5.7. Test pattern generation
After circuit setup, design rule check and circuit learning the test pattern generation control
panel appears as shown in Figure 16.


Figure 16. FlexTest test pattern generation control panel

Specify the type of faults that should be detected.
In the Control Panel
Click on Fault Universe.

The fault universe window will appear as illustrated in Figure 17.
Select Fault Model Single Stuck-At.
Select Fault Type Both of Above.
Click on OK.

Figure 17. Setup Fault Universe window.
TDDC33 Design for Test of Digital Systems 17

Run the test pattern generation.
Click on Test Generation.
Click on Run with Existing Settings.
Click on Add All Faults.

The results will be presented in the FlextTest Run ATPG Run Statistics window. How the
results can be analyzed in described in Section 5.8.
5.8. Results and analysis
The Fault Simulation Run Statistics window, illustrated in Figure 18, shows the following
information.
Test Coverage - percentage of all testable faults that are detected by the patterns.
Fault Coverage - percentage of all faults both testable and untestable those are
detected by the patterns.
ATPG effectiveness percentage - a measure of the ability of the ATPG tool to either
provide a test to detect a fault, or prove that a test cannot be created.

Figure 18. ATPG Run Statistics window.

In the Fault Simulation Run Statistics window
Click on Report.

In the Results & Analysis window, illustrated in Figure 19.
Options -> Check Report Faults on ALL DESIGN OBJECTS
Fault Type-> Check Both of the Above
Reported Data -> Click on Show Statistics
Check Entire Design and click on Report
Reported Data -> Click on Report Faults
Click on Close
TDDC33 Design for Test of Digital Systems 18

Figure 19. Results and Analysis window.

In the Fault Simulation Run Statistics window
Click on Dismiss

In the Control panel
Click on Done with Fault Simulation or Done with Pattern Generation
Click on Setup to continue or Exit to close FlexTest



TDDC33 Design for Test of Digital Systems 19
6. Test point insertion in VHDL
This chapter describes how the testability of a design can be improved by inserting test points.
It is assumed that the VHDL description of a design is available.
6.1. Input
A design described in VHDL
6.2. Output
A new design with test points.
6.3. Inserting test points
Add the new input and output ports in the ENTITY block
Add new signals in the ARCHITECTURE block (if needed)
Modify the design (introduction of new gates may be required) such that the new
ports is used to control and observe the hard-to-test parts of the design.

Please refer to Appendix A for an example of VHDL code with inserted test points.


TDDC33 Design for Test of Digital Systems 20
7. Board test using Boundary Scan (IEEE 1149.1)
This chapter describes the boundary scan board test methodology. For the board test
programming and test, a program called Trainer1149 from Testonica Lab is used.
7.1. Input
A board design, consisting of one bsdl-file for each chip together with a list of connections.
7.2. Output
A test program.
7.3. Starting Trainer1149
Verify that the current installed version of java is 1.6 or higher
java version
module add prog/jdk/1.6

Start the Trainer1149 program
java jar trainer1149.jar &

Select an existing project or make a new project
7.4. How to use Trainer1149
The Trainer1149 program has three different modes, Project Mode, Debug Mode, and Board
Edit Mode. The Trainer1149 program will start in the project mode, which allows you to view
and modify the board layout. In Figure 20, the twochips.nl netlist has been chosen in the
Project Explorer.
TDDC33 Design for Test of Digital Systems 21

Figure 20. Trainer1149 in Project Mode.

Select appropriate item in the Mode menu to change the working mode. Another way is to use
the toolbar buttons illustrated in Figure 21.


Figure 21. Mode selection buttons.

In Debug Mode it is possible to perform boundary scan operations on the current design. In
the Board Edit mode the user can create and/or modify the design. In this tutorial we focus on
boundary scan operations in Debug Mode.

7.5. Introducing a fault
The Trainer1149 has a trainer function where faults can be inserted in the design. The trainer
function is used to verify whether the test program detects the faults as intended. The
following instructions show how to insert a stuck-at 0 in net2.

Insert a fault in the design.
Training->Inject Fault

The Injection Fault window, illustrated in Figure 22, will appear.

TDDC33 Design for Test of Digital Systems 22

Figure 22. Inject Fault window.

Insert the stuck-at 0 fault.
Select Stuck-at 0 in Open Fault panel.
Select net2 in Select net panel.
Press Inject fault button.
7.6. Writing and verifying a test program using the Test Constructor
The following procedure describes how to write a test program that detects if there is a stuck-
at 0 fault present at the net2 in Figure 20. (The net identification is retrieved by placing the
cursor over the wire.)

Select the Debug Mode
Mode->Debug
The Test Constructor panel will appear as illustrated in Figure 23.


Figure 23. Test Constructor panel.

TDDC33 Design for Test of Digital Systems 23
The button RUN is used to execute the selected instruction and to load the specified vector,
the buttons TLR, IR, and DR are used for test logic reset, scan instruction register only, and
scan data register only, respectively.

Specify the instruction and test vector.
Select the EXTEST forchip1 and chip2.
Specify the following vectors to detect the stuck-at 0 fault:
Chip1 : 1111111111111111
Chip2 : 1111111111111111

When the test vectors have been applied and captured, the produced test responses can be
compared with the expected test responses and the fault detected. An example is illustrated in
Figure 24 where the stuck-at 0 fault on net2 is detected.
If you have inserted a fault as described in Section 6.3, you can check if you have
successfully detected it.

Check if you have detected the fault.
Training->Check Fault
Select the net that you suspect has a fault



Figure 24. Stuck-at 0 fault detected.

Detected fault
TDDC33 Design for Test of Digital Systems 24
7.7. Writing and verifying a test program using the TAP Controller
The following procedure describes how to write a test program that detects if there is a stuck-
at 0 fault present at the net2 in Figure 20.

Open the TAP Controller state machine.
Press TAP State Diagram button (Figure 25).
The TAP State Diagram window will appear as illustrated in Figure 26.


Figure 25. Button to open the TAP Controller state machine.


Figure 26. The TAP state machine.

Specify the input signals TDI and TMS by pressing the buttons TDI(0) and TMS(0). The test
clock is toggled by pressing TCK(0).

Load the EXTEST instruction and apply the test vector.
The stuck-at 0 fault is detected by applying the test procedure presented in Table 2.

Table 2. Test procedure.
TDI
(Value)
TMS
(Value)
TCK
(No. of click)
Comment
0 0 1
0 1 2 Select IR-Scan
0 0 2 Shift-IR
0 0 16 Shift in EXTEST
0 1 3 Select-DR-Scan
0 0 2 Shift-DR
1 0 36 Shift in test vector (all 1s)
0 1 3 Select-DR-Scan
0 0 1 Capture-DR
0 1 3

TDDC33 Design for Test of Digital Systems 25
Appendix A S27_TP VHDL Description

---------------------------------------------------------------------------------------------------------
--This file is modified by Anders Larsson
--Increased testability by introducing a new control point.
--More control and/or observ points should be added to further increase the testability.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;

ENTITY s27_bench IS
PORT (
--Add a new input
INP: in std_ulogic_vector(0 to 4);
OUTP : out std_ulogic_vector(0 to 0);
H : in std_ulogic
);
END s27_bench ;



ARCHITECTURE structural OF s27_bench IS

component andg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component org
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component xorg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component xnorg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component nandg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;
TDDC33 Design for Test of Digital Systems 26

component norg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component invg
generic (tpd_hl : time;
tpd_lh : time);
port (in1 : std_logic;
out1 : out std_logic);
end component;

component buffg
generic (tpd_hl : time;
tpd_lh : time);
port (in1 : std_logic;
out1 : out std_logic);
end component;

-- ******* Portes generiques sur le nombre d'entr

component andg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time);
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component nandg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time );
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component org_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component norg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component xorg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
TDDC33 Design for Test of Digital Systems 27
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component xnorg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component DFFC
generic (tpd_hl : time;
tpd_lh : time);
port (DFFC,H,C : std_logic;
Q : out std_logic);
end component;

component DFF
generic (tpd_hl : time;
tpd_lh : time);
port (D,H : std_logic;
Q : out std_logic);
end component;

component TFFC
generic (tpd_hl : time;
tpd_lh : time);
port (T,H,C : std_logic;
Q : out std_logic);
end component;

signal INTERP : std_ulogic_vector(0 to 11):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
BEGIN
DFF0 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(1),
H => H,
Q => INTERP(0));

DFF1 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(3),
H => H,
Q => INTERP(2));

DFF2 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(5),
H => H,
Q => INTERP(4));

INV0 : INVG generic map (1 ns,1 ns)
port map (
in1 => INP(0),
out1 => INTERP(6));

INV1 : INVG generic map (1 ns,1 ns)
TDDC33 Design for Test of Digital Systems 28
port map (
in1 => INTERP(3),
out1 => OUTPI(0));

AND0 : ANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(6),
inp(1) => INTERP(2),
out1 => INTERP(7));

OR0 : ORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(9),
inp(1) => INTERP(7),
out1 => INTERP(8));

OR1 : ORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(3),
inp(1) => INTERP(7),
out1 => INTERP(10));

NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(10),
inp(1) => INTERP(8),
out1 => INTERP(11));

NOR0 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(6),
inp(1) => INTERP(3),
out1 => INTERP(1));

NOR1 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(0),
inp(1) => INTERP(11),
out1 => INTERP(3));

NOR2 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(1),
inp(1) => INTERP(4),
out1 => INTERP(9));

NOR3 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(2),
inp(1) => INTERP(9),
out1 => INTERP(5));

BUFFER_OUT : OUTP <= OUTPI;

END structural ;

ARCHITECTURE rtl OF s27_bench IS
--Increase the number of signal wires (from 11 to 12)
signal INTERP : std_ulogic_vector(0 to 12):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
TDDC33 Design for Test of Digital Systems 29
BEGIN
REGVECT : BLOCK (H='1' AND NOT H'STABLE)
BEGIN
DFF3 : INTERP(0) <= GUARDED INTERP(12) after 1 ns;
DFF4 : INTERP(2) <= GUARDED INTERP(3) after 1 ns;
DFF5 : INTERP(4) <= GUARDED INTERP(5) after 1 ns;
END BLOCK ;
INV2 : INTERP(6) <= NOT(INP(0)) after 1 ns;
INV3 : OUTPI(0) <= NOT(INTERP(3)) after 1 ns;
AND1 : INTERP(7) <= INTERP(6) AND INTERP(2) after 1 ns;
OR2 : INTERP(8) <= INTERP(9) OR INTERP(7) after 1 ns;
OR3 : INTERP(10) <= INP(3) OR INTERP(7) after 1 ns;
NAND1 : INTERP(11) <= NOT(INTERP(10) AND INTERP(8)) after 1 ns;
NOR4 : INTERP(1) <= NOT(INTERP(6) OR INTERP(3)) after 1 ns;
NOR5 : INTERP(3) <= NOT(INTERP(0) OR INTERP(11)) after 1 ns;
NOR6 : INTERP(9) <= NOT(INP(1) OR INTERP(4)) after 1 ns;
NOR7 : INTERP(5) <= NOT(INP(2) OR INTERP(9)) after 1 ns;
-- Add the control point
OR4 : INTERP(12) <=INP(4) OR INTERP(1) after 1 ns;
BUFFER_OUT : OUTP <= OUTPI;

END rtl ;


TDDC33 Design for Test of Digital Systems 30
References
[1] http://asic.austriamicrosystems.com/databooks/c35/databook_c35_33/, April 2006.

TDDC33 Design for Test of Digital Systems 31