Chapter Two

based on the sophistication of the synthesis tool and the constraints put
on the design.
Transport Versus Inertial Delay
In VHDL, there are two types of delay that can be used for modeling
behaviors. Inertial delay is the most commonly used, while transport delay
is used where a wire delay model is required.
Inertial Delay
Inertial delay is the default in VHDL. If no delay type is specified, inertial
delay is used. Inertial delay is the default because, in most cases, it
behaves similarly to the actual device.
In an inertial delay model, the output signal of the device has inertia,
which must be overcome for the signal to change value. The inertia value
is equal to the delay through the device. If there are any spikes, pulses,
and so on that have periods where a signal value is maintained for less
than the delay through the device, the output signal value does not
change. If a signal value is maintained at a particular value for longer
than the delay through the device, the inertia is overcome and the device
changes to the new state.
Figure 2-4 is an example of a very simple buffer symbol. The buffer has
a single input A and a single output B. The waveforms are shown for input
Aand the output B. Signal Achanges from a 0 to a 1 at 10 nanoseconds
and from a 1 to a 0 at 20 nanoseconds. This creates a pulse or spike
that is 10 nanoseconds in duration. The buffer has a 20- nanosecond delay
through the device.
The 0 to 1 transition on signal A causes the buffer model to be executed
and schedules an event with the value 1 to occur on output B at
time 30 nanoseconds. At time 20 nanoseconds, the next event on signal A
occurs. This executes the buffer model again. The buffer model predicts a
new event on output B of a 0 value at time 40 nanoseconds. The event
scheduled on output B for time 30 nanoseconds still has not occurred. The
new event predicted by the buffer model clashes with the currently
scheduled event, and the simulator preempts the event at 30 nanoseconds.
The effect of the preemption is that the spike is swallowed. The reason
for the cancellation is that, according to the inertial delay model, the first
Behavioral Modeling 21
A
B
0 10 20 30 40
A B
Delay = 20 ns
Figure 2-4
Inertial Delay Buffer
Waveforms.
event at 30 nanoseconds did not have enough time to overcome the inertia
of the output signal.
The inertial delay model is by far the most commonly used in all currently
available simulators. This is partly because, in most cases, the
inertial delay model is accurate enough for the designers needs. One
more reason for the widespread use of inertial delay is that it prevents
prolific propagation of spikes throughout the circuit. In most cases, this
is the behavior wanted by the designer.
Transport Delay
Transport delay is not the default in VHDL and must be specified. It represents
a wire delay in which any pulse, no matter how small, is propagated
to the output signal delayed by the delay value specified. Transport delay
is especially useful for modeling delay line devices, wire delays on a PC
board, and path delays on an ASIC.
If we look at the same buffer circuit that was shown in Figure 2-4, but
replace the inertial delay waveforms with the transport delay waveforms,
we get the result shown in Figure 2-5. The same waveform is input to
signal A, but the output from signal B is quite different. With transport
delay, the spikes are not swallowed, but the events are ordered before
22 Chapter Two
A B
Delay = 20 ns
A
B
0 10 20 30 40
Figure 2-5
Transport Delay
Buffer Waveforms.
propagation.
At time 10 nanoseconds, the buffer model is executed and schedules an
event for the output to go to a 1 value at 30 nanoseconds. At time 20
nanoseconds, the buffer model is re-invoked and predicts a new value for
the output at time 40 nanoseconds. With the transport delay algorithm,
the events are put in order. The event for time 40 nanoseconds is put in
the list of events after the event for time 30 nanoseconds. The spike is not
swallowed but is propagated intact after the delay time of the device.
Inertial Delay Model
The following model shows how to write an inertial delay model. It is
the same as any other model we have been looking at. The default delay
type is inertial; therefore, it is not necessary to specify the delay type to
be inertial:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY buf IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END buf;
Behavioral Modeling 23
ARCHITECTURE buf OF buf IS
BEGIN
b <= a AFTER 20 ns;
END buf;
Transport Delay Model
Following is an example of a transport delay model. It is similar in every
respect to the inertial delay model except for the keyword TRANSPORT in
the signal assignment statement to signal b. When this keyword exists,
the delay type used in the statement is the transport delay mechanism:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY delay_line IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END delay_line;
ARCHITECTURE delay_line OF delay_line IS
BEGIN
b <= TRANSPORT a AFTER 20 ns;
END delay_line;
Simulation Deltas
Simulation deltas are used to order some types of events during a simulation.
Specifically, zero delay events must be ordered to produce consistent
results. If zero delay events are not properly ordered, results can
be disparate between different simulation runs. An example of this is
shown using the circuit shown in Figure 2-6. This circuit could be part of
a clocking scheme in a complex device being modeled. It probably would
not be the entire circuit, but only a part of the circuit used to generate
the clock to the D flip-flop.
The circuit consists of an inverter, a NAND gate, and an AND gate
driving the clock input of a flip-flop component. The NAND gate and AND
gate are used to gate the clock input to the flip-flop.
Lets examine the circuit operation, using a delta delay mechanism and
another mechanism. By examining the two delay mechanisms, we will
better understand how a delta delay orders events.
24 Chapter Two
D
CLK
Q
QB
DFF
A
Clock
C
D
B
E
F
Figure 2-6
Simulation Delta
Circuit.
To use delta delay, all of the circuit components must have zero delay
specified. The delay for all three gates is specified as zero. (Real circuits
do not exhibit such characteristics, but sometimes modeling is easier if
all of the delay is concentrated at the outputs.) Lets examine the nondelta
delay mechanism first.
When a falling edge occurs on signal A, the output of the inverter
changes in 0 time. Lets assume that such an event occurs at time 10
nanoseconds. The output of the inverter, signal B, changes to reflect the
new input value. When signal B changes, both the AND gate and the
NAND gate are reevaluated. For this example, the clock input is assumed
to be a constant value 1. If the NAND gate is evaluated first, its new
value is 0.
When the AND gate evaluates, signal B is a 0, and signal C is a 1;
therefore, the AND gate predicts a new value of 0. But what happens
if the AND gate evaluates first? The AND gate sees a 1 value on signal
B, and a 1 value on signal C before the NAND gate has a chance to
reevaluate. The AND gate predicts a new value of 1.
Behavioral Modeling 25
AND First NAND First
evaluate inverter evaluate inverter
B <= 1 B <= 1
evaluate AND (C = 1) evaluate NAND
D <= 1 C <= 0
evaluate NAND evaluate AND
C <= 0 D <= 0
evaluate AND
D <= 0
Figure 2-7
Comparison of Two
Evaluation Mechanisms.
The NAND gate reevaluates and calculates its new value as 0. The
change on the output of the NAND gate causes the AND gate to reevaluate
again. The AND gate now sees the value of B, a 1 value, and the new
value of signal C, a 0 value. The AND gate now predicts a 0 on its
output. This process is summarized in Figure 2-7.
Both circuits arrive at the same value for signal D. However, when the
AND gate is evaluated first, a rising edge, one delta delay wide, occurs on
signal D. This rising edge can clock the flip-flop, depending on how the
flip-flop is modeled.
The point of this discussion is that without a delta synchronization
mechanism, the results of the simulation can depend on how the simulator
data structures are built. For instance, compiling the circuit the first time
might make the AND gate evaluate first, while compiling again might
make the NAND gate evaluate firstclearly not desirable results; simulation
deltas prevent this behavior from occurring.
The same circuit evaluated using the VHDL delta delay mechanism
would evaluate as shown in Figure 2-8.
The evaluation of the circuit does not depend on the order of evaluation
of the NAND gate or AND gate. The sequence in Figure 2-8 occurs
irrespective of the evaluation order of the AND or NAND gate.
During the first delta time point of time 10 nanoseconds, signal Areceives
the value 0. This causes the inverter to reevaluate with the new value.
26 Chapter Two
Time Delta Activity
10 ns (1) A <= 0
evaluate inverter
(2) B <= 1
evaluate AND
evaluate NAND
(3) D <= 1
C <= 0
evaluate AND
(4) D <= 0
11 ns
Figure 2-8
Delt