DIGITAL LOGIC DESIGN

BY, KSVKSRIKANTH
Table of Contents
Chapter 1 - Introduction to Digital Concepts
Chapter 2 - Number System and Codes
Chapter 3 - Logic ates
Chapter ! - "oolean #lgebra
Chapter $ - Combinational logic circuit Design
Chapter % - Se&uential logic Circuit Design
Chapter ' - (egisters and Counters
DIGITAL LOGIC DESIGN
Chapter 1: Introduction to digital concepts
1-1 Numerical Representations
1-2 Advantages and Limitations of Digital Techniques
1-3 Digital Number !stem
1-" Representing #inar! $uantities
1-% &loating 'oint Representation
1.1 Numerical resentation
(n science) technolog!) business) and) in fact) most other fields of endeavor) *e are
constantl! dealing *ith quantities+ $uantities are measured) monitored) recorded)
manipulated arithmeticall!) observed) or in some other *a! utili,ed in most ph!sical
s!stems+ (t is important *hen dealing *ith various quantities that *e be able to
represent their values efficientl! and accuratel!+ There are basicall! t*o *a!s of
representing the numerical value of quantities- analog and digital+
#nalog (epresentation
(n analog representation a quantit! is represented b! a voltage) current) or meter
movement that is proportional to the value of that quantit!+ Analog quantities such as
those cited above have an important characteristic- the! can var! over a continuous
range of values+
#elo* is a diagram of analog
voltage vs time-

Digital (epresentation
(n digital representation the quantities are represented not b! proportional quantities
but b! s!mbols called digits+ As an e.ample) consider the digital *atch) *hich
provides the time of da! in the form of decimal digits *hich represent hours and
minutes /and sometimes seconds0+ As *e 1no*) the time of da! changes
continuousl!) but the digital *atch reading does not change continuousl!2 rather) it
changes in steps of one per minute /or per second0+ (n other *ords) this digital
representation of the time of da! changes in discrete steps) as compared *ith the
representation of time provided b! an analog *atch) *here the dial reading changes
continuousl!+
#elo* is a diagram of digital voltage vs time-
The ma3or difference bet*een analog and digital quantities) then) can be simpl!
stated as follo*s-
Analog4continuous
Digital 4 discrete /step b! step0
1)2 #d*antages and Limitations of Digital Techni&ues
#d*antages
5asier to design+ 5.act values of voltage or current are not important) onl! the
range /6(76 or L890 in *hich the! fall+
(nformation storage is eas!+
Accurac! and precision are greater+
8peration can be programmed+ Analog s!stems can also be programmed) but
the variet! and comple.it! of the available operations is severel! limited+
Digital circuits are less affected b! noise+ As long as the noise is not large
enough to prevent us from distinguishing a 6(76 from a L89+
:ore digital circuitr! can be fabricated on (; chips+
Limitations
There is reall! onl! one ma3or dra*bac1 *hen using digital techniques-
The real *orld is mainl! analog+ :ost ph!sical quantities are analog in nature) and it
is these quantities that are often the inputs and outputs that are being monitored)
operated on) and controlled b! a s!stem+
To ta1e advantage of digital techniques *hen dealing *ith analog inputs and outputs)
three steps must be follo*ed-
1+ ;onvert the real-*orld analog inputs to digital form+ /AD;0
2+ 'rocess /operate on0 the digital information+
3+ ;onvert the digital outputs bac1 to real-*orld analog form+ /DA;0
The follo*ing diagram sho*s a temperature control s!stem that requires
analog<digital conversions in order to allo* the use of digital processing techniques+
1)3 Digital Number System
:an! number s!stems are in use in digital technolog!+ The most common are the
decimal) binar!) octal) and he.adecimal s!stems+ The decimal s!stem is clearl! the
most familiar to us because it is a tool that *e use ever! da!+ 5.amining some of its
characteristics *ill help us to better understand the other s!stems+
Decimal System
Decimal !stem The decimal s!stem is composed of 1= numerals or s!mbols+ These
1= s!mbols are =) 1) 2) 3) ") %) >) ?) @) A2 using these s!mbols as digits of a number)
*e can e.press an! quantit!+ The decimal s!stem) also called the base-1= s!stem
because it has 1= digits+
1=
3
1=
2
1=
1
1=
=
1=
-1
1=
-2
1=
-3
41=== 41== 41= 41 + 4=+1 4=+=1 4=+==1
!ost Significant
Digit

Decimal
point

Least Significant
Digit
"inary System
(n the binar! s!stem) there are onl! t*o s!mbols or possible digit values) = and 1+
This base-2 s!stem can be used to represent an! quantit! that can be represented in
decimal or other number s!stem+
"
#
"
"
"
1
"
$
"
%1
"
%"
"
%#
&' &( &" &1 . &1)" &1)( &1)'
!ost Signi*icant
+it

+inar,
point
Least Signi*icant +it

"inary Counting
The #inar! counting sequence is sho*n in the table-

1)! (epresenting "inary +uantities
(n digital s!stems the information that is being processed is usuall! presented in
binar! form+ #inar! quantities can be represented b! an! device that has onl! t*o
operating states or possible conditions+ 5g+ a s*itch has onl! open or closed+ 9e
arbitraril! /as *e define them0 let an open s*itch represent binar! = and a closed
s*itch represent binar! 1+ Thus *e can represent an! binar! number b! using series
of s*itches+
Typical ,oltage #ssignment
+inar, 1- An! voltage bet*een 2B to %B
+inar, $- An! voltage bet*een =B to =+@B
Not used- Boltage bet*een =+@B to 2B) this ma! cause error in a digital circuit+

9e can see another significant difference bet*een digital and analog s!stems+ (n
digital s!stems) the e.act value of a voltage is not important2 eg) a voltage of 3+>B
means the same as a voltage of "+3B+ (n analog s!stems) the e-act value of a voltage
is important+
1-$ -loating point (epresentation
-loating .oint Numbers
A real num.er or *loating point num.er is a num.er /hich has .oth an integer and
*ractional part. E-amples *or real real decimal num.ers are 1"#.(01 $.1"#(1 %$.1"#(01 etc.
E-amples *or a real .inar, num.ers are 11$$.11$$1 $.1$$11 %1.$$11 etc. In general1 *loating
point num.ers are e-pressed in e-ponential notation.
2or e-ample the decimal num.er #$$$$.$ can .e /ritten as # - 1$
(
1 #1".(0 can .e /ritten
as #.1"(0 - 1$
".

Similarl,1 the .inar, num.er 1$1$.$$1 can .e /ritten as 1.$1$$$1 - 1$
#
.
The general *orm o* a num.er N can . e-pressed as
N & 3 m - .
3e
4here m is mantissa1 . is the .ase o* num.er s,stem and e is the e-ponent. A *loating
point num.er is represented ., t/o parts. The *irst part1 called mantissa1 o* the num.er is
a signed *i-ed point num.er and the second part1 called e-ponent1 speci*ies the decimal
or .inar, position.
"inary (epresentation of -loating .oint Numbers
A *loating point .inar, num.er is also represented as in the case o* decimal num.ers.
That5s means the mantissa and e-ponent are e-pressed using signed magnitude notation
in /hich one .it is reser6ed *or sign .it.
Consider a 17%.it /ord is used to store the *loating point num.ers1 Assume that the 8 .its
are reser6ed *or mantissa and 9%.its *or e-ponent and also assume that the mantissa part
is represented in *raction s,stem. That implies1 the assumed .inar, point is immediate
right o* sign .it o* mantissa.
/0ample
A .inar, num.er 11$1.$1 is represented as
!antissa & 11$1$1 :11$1.$1;
"
& $.11$1$1 < "
(
E-ponent & :(;
1$

E-pand mantissa to ' .its /e get 1 11$1$1$$
+inar, representation o* e-ponent :(;
1$
& $$$1$$

DIGITAL LOGIC DESIGN
Chapter 21 Number Systems and Codes
2-1 #inar!-to-Decimal ;onversion
2-2 Decimal-to-#inar! ;onversion
2-3 8ctal Numbers
2-" 6e.adecimal Number !stem
2-% #inar! codes-#;D) 7ra!) A;(() 5#;D(; 5rror detection codes
2-> #inar! numbers Addition) :ultiplication and ubtraction
2)1 "inary-To-Decimal Con*ersion
Introduction
The binar! number s!stem is the most important one in digital s!stems) but several
others are also important+ The decimal s!stem is important because it is universal
used to represent quantities outside a digital s!stem+ This means that there *ill be
situations *here decimal values have to be converted to binar! values before the!
are entered into the digital s!stem+
(n additional to binar! ans decimal) t*o other number s!stems find *ide-spread
applications in digital s!stems+ The octal /base-@0 and he.adecimal /base-1>0 number
s!stems are both used for the same purpose- to provide an efficient means for
representing large binar! s!stem+
This chapter *ill sho* !ou ho* to perform these conversions+
An! binar! number can be converted to its decimal equivalent simpl! b! summing
together the *eights of the various positions in the binar! number *hich contain a 1+
1 1 = 1 1
2
/binar!0
2
"
C2
3
C=C2
1
C2
=
4 1>C@C=C2C1
4 2?
1=
/decimal0
and
1 = 1 1 = 1 = 1
2
/binar!0
2
?
C=C2
%
C2
"
C=C2
2
C=C2
=
4 12@C=C32C1>C=C"C=C1
4 1@1
1=
/decimal0

Dou should noticed the method is find the *eights /i+e+) po*ers of 20 for each bit
position that contains a 1) and then to add them up+
2)2 Decimal-To-"inary Con*ersion

There are 2 methods-
/A0 Reverse of #inar!-To-Digital :ethod
"%
1=
4 32 C = C @ C " C= C 1
4 2
%
C=C2
3
C2
2
C=C2
=
4 1 = 1 1 = 1
2

/#0 Repeat Division
This method uses repeated division b! 2+ 5g+ convert 2%
1=
to binar!
2%< 2 4 12C remainder of 1 1 /Least ignificant #it0
12< 2 4 > C remainder of = =
> < 2 4 3 C remainder of = =
3 < 2 4 1 C remainder of 1 1
1 < 2 4 = C remainder of 1 1 (Most Significant Bit)
Result 2%
1=
4 1 1 = = 1
2
The &lo* chart for repeated-division method is as follo*-
2)3 2ctal Number System1

The octal number s!stem has a base of eight) meaning that it has eight possible
digits- =)1)2)3)")%)>)?+

@
3
@
2
@
1
@
=
@
-1
@
-2
@
-3
4%12 4>" 4@ 41 + 41<@ 41<>" 41<%12
:ost ignificant
Digit

8ctal
point

Least ignificant
Digit
8ctal to Decimal ;onversion
eg+ 2"+>
@
4 2 . /@
1
0 C " . /@
=
0 C > . /@
-1
0 4 2=+?%
1=
#inar!-To-8ctal < 8ctal-To-#inar! ;onversion
8ctal Digit = 1 2 3 " % > ?
#inar! 5quivalent === ==1 =1= =11 1== 1=1 11= 111
5ach 8ctal digit is represented b! three bits of binar! digit+
eg+ 1== 111 =1=
2
4 /1==0 /1110 /=1=0
2
4 " ? 2
@
Repeat Division
This method uses repeated division b! @+ 5g+ convert 1??
1=
to octal and binar!-
1??<@ 4 22C remainder of 1 1 /Least ignificant #it0
22< @ 4 2 C remainder of > >
2 < @ 4 = C remainder of 2 2 (Most Significant Bit)
Result 1??
1=
4 2>1
@
;onvert to #inar! 4 =1=11===1
2
2)$ "inary codes-"CD3 ray3 #SCII3 /"CDIC /rror detection
codes1

+inar, Coded Decimal
E +inar, coded decimal :+CD; represents each decimal digit /ith *our .its
= E-. $$11 $$1$ 1$$1 & #"8
1$
# " 8
> This is N2T the same as $$11$$1$1$$1
"
> 4h, do this? +ecause people thin@ in decimal.
$$$$ $
$$$1 1
$$1$ "
$$11 #
$1$$ (
$1$1 0
$11$ 7
$111 9
1$$$ '
1$$1 8
utting It All Together

DECI!AL +INAAB OCTAL CE<ADECI!AL +CD
$ $ $ $ $$$$
1 1 1 1 $$$1
" 1$ " " $$1$
# 11 # # $$11
( 1$$ ( ( $1$$
0 1$1 0 0 $1$1
7 11$ 7 7 $11$
9 111 9 9 $111
' 1$$$ 1$ ' 1$$$
8 1$$1 11 8 1$$1
1$ 1$1$ 1" A 1$1$
11 1$11 1# + 1$11
1" 11$$ 1( C 11$$
1# 11$1 10 D 11$1
1( 111$ 17 E 111$
10 1111 19 2 1111
E +CD not 6er, e**icient
> Dsed in earl, computers :($s1 0$s;
> Dsed to encode num.ers *or se6en segment displa,s.
> Easier to read?
Gra, Code
> Gra, code is not a num.er s,stem.
= It is an alternate /a, to represent *our .it data
> Onl, one .it changes *rom one decimal digit to the ne-t
> Dse*ul *or reducing errors in communication.
> Can .e scaled to larger num.ers.

DECI!AL
ND!+EAS
+INAAB GAAB CODE
$ $$$$ $$$$
1 $$$1 $$$1
" $$1$ $$11
# $$11 $$1$
( $1$$ $11$
0 $1$1 $111
7 $11$ $1$1
9 $111 $1$$
' 1$$$ 11$$
8 1$$1 11$1
1$ 1$1$ 1111
11 1$11 111$
1" 11$$ 1$1$
1# 11$1 1$11
1( 111$ 1$$1
10 1111 1$$$

ASCII Code
> American Standard Code *or In*ormation Interchange
> ASCII is a 9%.it code1 *reEuentl, used /ith an 'th .it *or error detection :more a.out that
in a .it;.
> ASCII Codes
> A F G :"7 codes;1 a F H :"7 codes;
> $%8 :1$ codes;1 others :IJKLMNOP.;
> Transmission suscepti.le to noise
> T,pical transmission rates :10$$ Q.ps1 07.7 Q.ps;
> Co/ to @eep data transmission accurate?
arit, Codes :Error detection codes;
> arit, codes are *ormed ., concatenating a parity bit3 . to each code /ord o* C.
> In an odd-parity code1 the parit, .it is speci*ied so that the total num.er o* ones is odd.
> In an e6en-parity code1 the parit, .it is speci*ied so that the total num.er o* ones is
e6en.

p Information "its

1 1 $ $ $ $ 1 1

Added e6en parit, .it
$ 1 $ $ $ $ 1 1

Added odd parit, .it
arit, Code E-ample
> Concatenate a parit, .it to the ASCII code *or the characters $1 <1 and & to produce .oth
odd%parit, and e6en%parit, codes.

Character

ASCII

Odd%arit,
ASCII

E6en%arit,
ASCII

$ $11$$$$ 1$11$$$$ $$11$$$$
< 1$11$$$ $1$11$$$ 11$11$$$
& $1111$$ 1$1111$$ $$1111$$

+inar, Data Storage
F +inar, cells store indi6idual .its o* data
= !ultiple cells *orm a register.
= Data in registers can indicate di**erent 6alues
= Ce- :decimal;
= +CD
= ASCII

+inar, Cell
$ $ 1 $ 1 $ 1 1

Aegister Trans*er
> Data can mo6e *rom register to register.
> Digital logic used to process data
Aegister A Aegister +
Aegister C
2)% "inary numbers #ddition3 4ultiplication3 and
Subtraction

+inar, Addition
E +inar, addition is 6er, simple.
> This is .est sho/n in an e-ample o* adding t/o
+inar, num.ersP
1 1 1 1 1 1 carries

1 1 1 1 $ 1
R 1 $ 1 1 1
%%%%%%%%%%%%%%%%%%%%%
1 5 1 5 1 $ $
---------------------

+inar, Su.traction
> 4e can also per*orm su.traction :/ith .orro/s in place o* carries;.
> LetSs su.tract :1$111;
"
*rom :1$$11$1;
"
P

1 1$
$ 1$ 1$ $ $ 1$ .orro/s

1 $ $ 1 1 $ 1
% 1 $ 1 1 1
%%%%%%%%%%%%%%%%%%%%%%%%
1 1 $ 1 1 $
%%%%%%%%%%%%%%%%%%%%%%%-

+inar, !ultiplication

E +inar, multiplication is much the same as decimal multiplication1 e-cept that the
multiplication operations are much simplerP
1 $ 1 1 1
< 1 $ 1 $ : !ultiplication;
%%%%%%%%%%%%%%%%%%%%%%%
$ $ $ $ $
1 $ 1 1 1
$ $ $ $ $
1 $ 1 1 1
%%%%%%%%%%%%%%%%%%%%%%%
1 1 1 $ $ 1 1 $
%%%%%%%%%%%%%%%%%%%%%%%

DIGITAL LOGIC DESIGN
Chapter - 31 Logic gates
3-1 #oolean Bariables G Truth Tables
3-2 8R 8peration
3-3 AND 8peration
3-" N8T 8peration
3-% N8R 8peration
3-> NAND 8peration
#.9 <OA Operation gates
#.' <NOA Operation gates
3)1 "oolean ,ariables 6 Truth Tables
#oolean algebra differs in a ma3or *a! from ordinar! algebra in that #oolean
constants and variables are allo*ed to have onl! t*o possible values) $ or 1+
#oolean = and 1 do not represent actual numbers but instead represent the state of a
voltage variable) or *hat is called its logic level+
ome common representation of = and 1 is sho*n in the follo*ing diagram+
Logic $ Logic 1
2alse True
O** On
Lo/ Cigh
No Bes
Open S/itch Close S/itch
(n #oolean algebra) there are three basic logic operations- 8R) AND and N8T+
These logic gates are digital circuits constructed from diodes) transistors) and
resistors connected in such a *a! that the circuit output is the result of a basic logic
operation /8R) AND) N8T0 performed on the inputs+
Gate Dela,
Aeal gates ha6e dela,. In other /ords1 i* ,ou change the 6alue o* the inputs1 sa, *rom $
and $ to $ and 11 then the output ta@es some small amount o* time .e*ore it changes. This
dela, is called gate delay.
This dela, is due to the *act that in*ormation can tra6el at most1 the speed o* light1 and in
realit,1 the time it ta@es to do the computation is not in*initel, Euic@.
This dela, limits ho/ *ast the inputs can change and ,et the output ha6e meaning*ul
6alues. It also allo/s certain @inds o* circuits to .e created that don5t *ollo/ the rules
*rom the pre6ious section. In particular1 *lip *lops :to .e discussed later; can .e generated
*rom gates that use c,cles.
Truth Ta.le
A truth table is a means for describing ho* a logic circuitHs output depends on the
logic levels present at the circuitHs inputs+
(n the follo*ing t*o-inputs logic circuit) the table lists all possible combinations of logic
levels present at inputs A and # along *ith the corresponding output level I+

9hen either input A 8R # is 1) the output I is 1+ Therefore the JKJ in the bo. is an 8R
gate+
3)2 2( 2peration1
The e.pression I 4 A C # reads as JI equals A OA #J+
The C sign stands for the 8R operation) not for ordinar! addition+
The 8R operation produces a result of 1 *hen an, of the input variable is 1+
The 8R operation produces a result of = onl! *hen all the input variables are =+

3)3 #ND 2peration
The e.pression I 4 A L # reads as JI equals A AND #J+
The multiplication sign stands for the AND operation) same for ordinar!
multiplication of 1s and =s+
The AND operation produces a result of 1 occurs onl! for the single case *hen all
of the input variables are 1+
The output is = for an! case *here one or more inputs are =


An e.ample of three input AND gate and its truth table is as follo*s-


9ith the AND operation) 1L1 4 1) 1L1L1 4 1 and so on+
3)! N2T 2peration1
The N8T operation is unli1e the 8R and AND operations in that it can be performed
on a single input variable+ &or e.ample) if the variable A is sub3ected to the N8T
operation) the result . can be e.pressed as
. 4 AH
*here the prime /H0 represents the N8T operation+ This e.pression is read as-
x equals NOT
x equals t!e inve"se of
x equals t!e complement of
5ach of these is in common usage and all indicate that the logic value of . 4 AH is
opposite to the logic value of A+
The truth table of the N8T operation is as follo*s-

1# $ % &ecause NOT 1 is %
%# $ 1 &ecause NOT % is 1
The N8T operation is also referred to as inversion or complementation) and these
terms are used interchangeabl!+
3)$ N2( 2peration1
N8R and NAND gates are used e.tensivel! in digital circuitr!+ These gates combine
the basic operations AND) 8R and N8T) *hich ma1e it relativel! eas! to describe
then using #oolean Algebra+
N8R is the same as the 8R gate s!mbol except that it has a small circle on the
output+ This small circle represents the inversion operation+ Therefore the output
e.pression of the t*o input N8R gate is-
I 4 / A C # 0H


An e.ample of three input 8R gate can be constructed b! a N8R gate plus a N8T
gate-

3)% N#ND 2peration1
NAND is the same as the AND gate s!mbol except that it has a small circle on the
output+ This small circle represents the inversion operation+ Therefore the output
e.pression of the t*o input NAND gate is-
I 4 / A# 0H


3)' 72( 2peration gates1

<OA gates ha6e t/o .its o* input and a single .it o* output.
The output o* <OA gate is 1 onl, i* the inputs ha6e opposite 6alues. That is1 /hen
one input has 6alue $1 and the other has 6alue 1.. Other/ise1 the output is $.
This is called e0clusi*e-or) The definition of 2(
2
is inclusi*e-or3 8here the output
is 1 if either input is 13 or if both inputs are 1)
72( can be defined using #ND3 2(3 and N2T)
0 72( y 99 : 0 #ND :N2T y; ; 2( : :N2T 0; #ND y ; 99 0<y = y<0
>ere?s a diagram of the 72( gate)

(* ,ou loo@ care*ull, at the dra/ing o* the gate1 there is a second arc .ehind the
*irst one near the inputs. Since this second arc is hard to see1 it5s usuall, a good
idea to /rite the /ord T<OAT inside the gate.
The truth ta.le de*ines the .eha6ior o* this gate.
-
1
-
$
H
= = =
= 1 1
1 = 1
1 1 =
The *unction implemented ., <OA gates has interesting properties:
The *unction is s,mmetric. Thus1 - :R; , && , :R; -. This can .e 6eri*ied .,
using truth ta.les. :4e use :R; to denote logical <OA%%ideall,1 /e5d dra/ it
/ith a R sign inside a circle1 .ut CT!L doesn5t seem to ha6e a s,m.ol *or
this;.
The *unction is associati6e. Thus1 U - :R; , V :R; H && - :R; U , :R; H V. This can
.e 6eri*ied ., using truth ta.les.
3)@ 7N2( 2peration gates 1

<NOA
"
gates ha6e t/o .its o* input and a single .it o* output.

The output o* <NOA gate is the negation o* <OA
"
and has 1 /hen .oth inputs are the
same.
I* ,ou loo@ care*ull, at the dra/ing o* the gate1 there is a second arc .ehind the *irst one
near the inputs. Since this second arc is hard to see1 it5s usuall, a good idea to /rite the
/ord T<NOAT inside the gate.
The truth ta.le de*ines the .eha6ior o* this gate.
-
1
-
$
H
$ $ $
$ 1 1
1 $ 1
1 1 $
The *unction implemented ., <NOA gates has interesting properties:
The *unction is s,mmetric. Thus1 - <NOA , && , <NOA -. This can .e 6eri*ied .,
using truth ta.les.
The *unction is associati6e. Thus1 :- <NOA ,; <NOA H && - <NOA :, <NOA H;. This
can .e 6eri*ied ., using truth ta.les.
DIGITAL LOGIC DESIGN
Chapter -!1 "oolean #lgebra
"-1 Describing Logic ;ircuits Algebraicall!
"-2 5valuating Logic ;ircuit 8utputs
"-3 (mplementing ;ircuits from #oolean 5.pression
"-" #oolean Theorems
"-% De:organHs Theorems
"-> #oolean function simplification G;anonical forms

"-? M-:ap /Marnaugh maps 0Rules and implification

"+@ Rules for Tabular method /$uine :c ;lus1e! method0

"+A Reali,ation of above #oolean e.pression using logic gates
"-1= Nniversalit! of NAND and N8R 7ates
"-11 Alternate Logic-7ate Representations
"-12 Logic !mbol (nterpretation
!)1 Describing Logic Circuits #lgebraically1
An! logic circuit) no matter ho* comple.) ma! be completel! described using the
#oolean operations) because the 8R gate) AND gate) and N8T circuit are the basic
building bloc1s of digital s!stems+

This is an e.ample of the circuit using #oolean e.pression-


'f an exp"ession contains &ot! ND and OR ope"ations( t!e ND ope"ations a"e
pe"fo"med fi"st ()$B*+ , B is pe"fo"med fi"st)( unless t!e"e a"e pa"ent!eses in t!e
exp"ession( in -!ic! case t!e ope"ation inside t!e pa"ent!eses is to &e pe"fo"med
fi"st ()$(*B)*+ , *B is pe"fo"med fi"st).

Circuits containing In6erters
9henever an (NB5RT5R is present in a logic-circuit diagram) its output e.pression is
simpl! equal to the input e.pression *ith a prime /H0 over it+

!)2 /*aluating Logic Circuit 2utputs1
8nce the #oolean e.pression for a circuit output has been obtained) the output logic
level can be determined for an! set of input levels+
This are t*o e.amples of the evaluating logic circuit output-
Let A4=) #41) ;41) D41
I 4 AH#; /ACD0H
4 =HL1L1L /=C10H
4 1 L1L1L /10H
4 1 L1L1L =
4 =
Let A4=) #4=) ;41) D41) 541
I 4 ODC //AC#0;0HP L 5
4 O1 C //=C=01 0HP L 1
4 O1 C /=L10HP L 1
4 O1C =HP L1
4 O1C 1 P L 1
4 1

'n gene"al( t!e follo-ing "ules must al-a/s &e follo-ed -!en evaluating a Boolean
exp"ession,
1. 0i"st( pe"fo"m all inve"sions of single te"ms1 t!at is( % $ 1 o" 1 $ %.
2. T!en pe"fo"m all ope"ations -it!in pa"ent!eses.
2. 3e"fo"m an ND ope"ation &efo"e an OR ope"ation unless pa"ent!eses indicate
ot!e"-ise.
4. 'f an exp"ession !as a &a" ove" it( pe"fo"m t!e ope"ations of t!e exp"ession fi"st
and t!en inve"t t!e "esult.
Determining Output Le6el *rom a Diagram
The output logic level for given input levels can also be determined directl! from the
circuit diagram *ithout using the #oolean e.pression+


!)3 Implementing Circuits -rom "oolean /0pression1
(f the operation of a circuit is defined b! a #oolean e.pression) a logic-circuit diagram
can he implemented directl! from that e.pression+
uppose that *e *anted to construct a circuit *hose output is ! 4 A;C #;H C AH#;+
This #oolean e.pression contains three terms /A;) #;H) AH#;0) *hich are 8R ed
together+ This tells us that a three-input 8R gate is required *ith inputs that are equal
to A;) #;H) and AH#;) respectivel!+
5ach 8R-gate input is an AND product term) *hich means that an AND gate *ith
appropriate inputs can be used to generate each of these terms+ Note the use of
(nverters to produce the AH and ;H terms required in the e.pression+

(.( +oolean Theorems:
(nvestigating the various #oolean theorems /rules0 can help us to simplif! logic
e.pressions and logic circuits+

:ultivariable Theorems-
The theorems presented .elo/ in6ol6e more than one 6aria.le:
/A0 . C ! 4 ! C . /commutative la*0
/1=0 . L ! 4 ! L . /commutative la*0
/110 .C /!C,0 4 /.C!0 C, 4 .C!C, /associative la*0
/120 . /!,0 4 /.!0 , 4 .!, /associative la*0
/13a0 . /!C,0 4 .! C .,
/13b0 /*C.0/!C,0 4 *! C .! C *, C .,
/1"0 . C .! 4 . Oproof see belo*P
/1%0 . C .H! 4 . C !
'roof of /1"0
. C .! 4 . /1C!0
4 . L 1 Ousing theorem />0P
4 . Ousing theorem /20P

Dualit!
E The principle of dualit! is an important concept+ This sa!s that if an e.pression is
valid in #oolean algebra) the dual of that e.pression is also valid+
E To form the dual of an e.pression) replace all C operators *ith+ 8perators) all+
operators *ith C operators) all ones *ith ,eros) and all ,eros *ith ones+
E &orm the dual of the e.pression a C /bc0 4 /a C b0/a C c0
E &ollo*ing the replacement rulesQ a/b C c0 4 ab C ac
E Ta1e care not to alter the location of the parentheses if the! are present+

(nvolution
E This theorem states- aRR 4 a
E Remember that aaR 4 = and aCaR41+
F Therefore) aR is the complement of a and a is also the complement of aR+
F As the complement of aR is unique) it follo*s that aRR4a+
E Ta1ing the double inverse of a value *ill give the initial value+

Absorption
E This theorem states- a C ab 4 a a/aCb0 4 a
E To prove the first half of this theorem- a C ab 4 a + 1 C ab
4 a /1 C b0
4 a /b C 10
4 a /10
a C ab4 a
!)$ De 4organ?s Theorem1
De:organHs theorems are e-tremel, useful in simplif!ing e.pressions in *hich a
product or sum of variables is inverted+ The t*o theorems are-
/1>0 /.C!0H 4 .H L !H
/1?0 /.L!0H 4 .H C !H
Theorem /1>0 sa!s that *hen the 8R sum of t*o variables is inverted) this is the
same as inverting each variable individuall! and then AND ing these inverted
variables+
Theorem /1?0 sa!s that *hen the AND product of t*o variables is inverted) this is the
same as inverting each variable individuall! and then 8R ing them+
5.ample
I 4 O/AHC;0 L /#CDH0PH
4 /AHC;0H C /#CDH0H 5&/ t!eo"em (16)7
4 /AHHL;H0 C /#HCDHH0 5&/ t!eo"em (18)7
4 A;H C #HD
Three Bariables De:organHs Theorem
/1@0 /.C!C,0H 4 .H L !H L ,H
/1A0 /.!,0H 4 .H C !H C ,H
(mplications of De:organHs Theorem
&or /1>0- /.C!0H 4 .H L !H

&or /1?0- /.L!0H 4 .H C !H

!)% "oolean function simplification Canonical forms1 4interms and
4a0terms1
O6er6ie/
> E-pressing +oolean *unctions
> Aelationships .et/een alge.raic eEuations1 s,m.ols1 and truth ta.les
> Simpli*ication o* +oolean e-pressions
>Canonical *orms: !interms and !a-terms
> AND%OA representations
= roduct o* sums
= Sum o* products
+oolean 2unctions
> +oolean alge.ra deals /ith .inar, 6aria.les and logic operations.
> 2unction results in .inar, $ or 1
2 & -:,RHS; 1 Gi6en alge.raic eEuation eEuation implemented /ith circuit
diagram and truth ta.le

TADTC TA+LE
< B G 2
$ $ $ $
$ $ 1 $
$ 1 $ $
$ 1 1 $
1 $ $ 1
1 $ 1 $
1 1 $ 1
1 1 1 1

+oolean 2unctions
> +oolean alge.ra deals /ith .inar, 6aria.les and logic operations.
> 2unction results in .inar, $ or 1
E<: G & -, R,H Implement /ith logic circuit diagram and truth ta.le

<BG <B BH G&-,R,H
$$$ $ $ $
$$1 $ $ $
$1$ $ $ $
$11 $ 1 1
1$$ $ $ $
1$1 $ $ $
11$ 1 $ 1
111 1 1 1

4e /ill learn ho/ to transition .et/een eEuation1 s,m.ols1 and truth ta.le.

Aepresentation Con6ersion
> Need to transition .et/een +oolean e-pression1 truth ta.le1 and circuit :s,m.ols;.
> Con6erting .et/een truth ta.le and e-pression is eas,.
> Con6erting .et/een e-pression and circuit is eas,.
> !ore di**icult to con6ert to truth ta.le.

Truth Ta.le to E-pression
> Con6erting a truth ta.le to an e-pression
= Each ro/ /ith output o* 1 .ecomes a product term
= Sum product terms together.


-,H R -,HS R -S,H
#ny "oolean /0pression can be represented in
sum of products formA

EEui6alent Aepresentations o* Circuits
> All three *ormats are eEui6alent
> Num.er o* 1Ss in truth ta.le output column eEuals
AND terms *or Sum%o*%roducts :SO; G & -,H R -,HS
R -S,H
Aeducing +oolean E-pressions
> Is this the smallest possi.le implementation o* this e-pression? NoW
> Dse +oolean Alge.ra rules to reduce comple-it, /hile preser6ing *unctionalit,.
> Step 1: Dse Theorem 1 :a R a & a;
= So -,H R -,HS R -S,H & -,H R -,H R -,HS R -S,H
> Step ": Dse distri.uti6e rule a:. R c; & a. R ac
= So -,H R -,H R -,HS R -S,H & -,:H R HS; R ,H:- R -S;
> Step #: Dse ostulate # :a R aS & 1;
= So -,:H R HS; R ,H:- R -S; & -,.1 R ,H.1
> Step (: Dse ostulate " :a . 1 & a;
= So -,.1 R ,H.1 & -, R ,H & -,H R -,HS R -S,H
G & -,H R -,HS R -S,H
Aeduced Card/are Implementation
> Aeduced eEuation reEuires less hard/areW
> Same *unction implementedW
< B G G
$ $ $ $
$ $ 1 $
$ 1 $ $
$ 1 1 $
1 $ $ 1
1 $ 1 $
1 1 $ 1
1 1 1 1

< B G G
$ $ $ $
$ $ 1 $
$ 1 $ $
$ 1 1 1
1 $ $ $
1 $ 1 $
1 1 $ 1
1 1 1 1


G & -,H R -,HS R -S,H & -, R ,H

!interms and !a-terms
> Each 6aria.le in a +oolean e-pression is a literal
> +oolean 6aria.les can appear in normal :-; or complement *orm :-S;
> Each AND com.ination o* terms is a minterm
> Each OA com.ination o* terms is a ma-term
2or e-ample:
!interms
- , H !interm
$ $ $ -S,SHS m$
$ $ 1 -S,SH m1
%%%%%% %%%%% %%%
1 $ $ -,SHS m(
%%%%%%%
1 1 1 -,H m9

2or e-ample:
!a-terms
- , H !a-term
$ $ $ -R,RH !$
$ $ 1 -R,RHS !1
P
1 $ $ -SR,RH !(
P
1 1 1 -SR,SRHS !9

Aepresenting 2unctions /ith !interms
> !interm num.er same as ro/ position in truth ta.le :starting *rom top *rom $;
> Shorthand /a, to represent *unctions

< B G G
$ $ $ $
$ $ 1 $
$ 1 $ $
$ 1 1 1
1 $ $ $
1 $ 1 $
1 1 $ 1
1 1 1 1

G&-,H R-,HS R-S,H
G & m9 R m7 R m# & X:#1 71 9;

Complementing 2unctions
> !interm num.er same as ro/ position in truth ta.le :starting *rom top *rom $;
> Shorthand /a, to represent *unctions

< B G G GS
$ $ $ $ 1
$ $ 1 $ 1
$ 1 $ $ 1
$ 1 1 1 $
1 $ $ $ 1
1 $ 1 $ 1
1 1 $ 1 $
1 1 1 1 $

G&-,H R-,HS R-S,H
GS & :-,H R -,HS R -S,H;S & GS Can /e *ind a simpler representation?

Complementing 2unctions
> Step 1: assign temporar, names
= . R c %Y H G & a R . R c
= :aR H;S & GS GS & :a R . R c;S
> Step ": Dse De!organsS La/
= :a R H;S & aS . HS
> Step #: Ae su.stitute :.Rc; *or H
= aS . HS & aS . :. R c;S
> Step (: Dse De!organsS La/ G & a R . R c
= aS . :. R c;S & aS . :.S. cS; GS & aS . .S . cS & aS.ScS
> Step 0: Associati6e rule
= aS . :.S. cS; & aS . .S . cS

Complementation E-ample
> 2ind complement o* 2 & -SH R ,H
= 2S & :-SH R ,H;S
> De!organSs
= 2S & :-SH;S :,H;S
> De!organSs
= 2S & :-SSRHS; :,SRHS;
> Aeduction %Y eliminate dou.le negation on -
= 2S & :-RHS; :,SRHS;
This *ormat is called product o* sums

Con6ersion +et/een Canonical 2orms
> Eas, to con6ert .et/een minterm and ma-term representations
> 2or ma-term representation1 select ro/s /ith $Ss


G & -,H R -,HS R -S,H
G & m9 R m7 R m# & X:#1 71 9;
G & !$!1!"!(!0 &
Z:$111"1(10;
< B G G
$ $ $ $
$ $ 1 $
$ 1 $ $
$ 1 1 1
1 $ $ $
1 $ 1 $
1 1 $ 1
1 1 1 1
G & :-R,RH;:-R,RHS;:-R,SRH;:-SR,RH;:-SR,RHS;
!-' B-4ap :Barnaugh maps ;(ules and Simplification1

4inimiCation 8ith Barnaugh 4aps

8vervie*
E M-maps- an alternate approach to representing #oolean functions
E M-map representation can be used to minimi,e #oolean functions
E 5as! conversion from truth table to M-map to minimi,ed 8' representation+
E imple rules /steps0 used to perform minimi,ation
E Leads to minimi,ed 8' representation+
F :uch faster and more more efficient than previous minimi,ation techniques *ith
#oolean algebra+
F All ro*s of truth table represented *ith a square
F 5ach square represents a minterm
E 5as! to convert bet*een truth table) M-map) and 8'
F Nnoptimi,ed form- number of 1Rs in M-map equals number of minterms /products0 in
8'
F 8ptimi,ed form- reduced number of minterms
Qarnaugh !aps % Aules o* Simpli*ication
The Marnaugh map uses the follo*ing rules for the simplification of e.pressions b! g"ouping
together ad3acent cells containing ones
7roups ma! not include an! cell containing a ,ero

7roups ma! be hori,ontal or vertical) but not diagonal+

7roups must contain 1) 2) ") @) or in general 2
n
cells+
That is if n 4 1) a group *ill contain t*o 1Hs since 2
1
4 2+
(f n 4 2) a group *ill contain four 1Hs since 2
2
4 "+

5ach group should be as large as possible+

5ach cell containing a one must be in at least one group+

7roups ma! overlap+

7roups ma! *rap around the table+ The leftmost cell in a ro* ma! be grouped *ith the
rightmost cell and the top cell in a column ma! be grouped *ith the bottom cell+

There should be as fe* groups as possible) as long as this does not contradict an! of the
previous rules+

Summar,:
1+ No ,eros allo*ed+
2+ No diagonals+
3+ 8nl! po*er of 2 number of cells in each group+
"+ 7roups should be as large as possible+
%+ 5ver! one must be in at least one group+
>+ 8verlapping allo*ed+
?+ 9rap around allo*ed+
@+ &e*est number of groups possible+
Qarnaugh !aps
A Marnaugh map is an arra! containing 2
1
cells *here 1 is the number of variables in the DN&
e.pression to be minimi,ed+ 5ach cell of the Marnaugh map corresponds to one ro* of the truth
table) or one assignment of truth values to the variables of the e.pression+ The cells of a
Marnaugh map are arranged so that con3unctions *hich differ on onl! one variable are ad3acent
to each other+
2-,ariable Barnaugh 4aps
A 2-variable Marnaugh map has four cells+ The map loo1s li1e this-


The cells on the top ro* represent the con3unctions /. and !0 and /not . and !0+ The cells on the
bottom ro* represent /. and not !0 and /not . and not !0+
9hen given a DN& to be minimi,ed) put a 1 in each cell of the Marnaugh map for *hich there is
a con3unction in the DN&+ Then group the cells into groups *hich contain a po*er of t*o cells2
that is) ma1e groups of si,e 2 or "+ 9hen *e get to larger Marnaugh maps !ou *ill be able to
ma1e groups of si,e @ or 1>+ :embers of groups must to ad3acent to one another either
hori,ontall! or verticall!) and groups must be rectangular in shape+ L-shaped groups are not
allo*ed+
LetHs use a Marnaugh map to minimi,e the follo*ing DN&-
S S S S
. ! C . ! C . !
6ere is the Marnaugh map *ith the appropriate 1Hs placed in cells and then grouped-
The onl! group that *e can ma1e that has the upper right cell in it is the pair in the second
column+ And the onl! group that contains the lo*er left cell is the pair in the second ro*+ Note
that *e can use the lo*er right cell in both groups+
8nce !ou have grouped cells) !ou can determine the minimi,ed logical e.pression+ 5ach group
reduces to one con3unction in the minimi,ed e.pression+ A group reduces to a con3unction
containing 3ust those literals that remain the same for ever! cell in the group+ &or e.ample) the
group in the above Marnaugh map that contains the t*o cells in the second column reduces to
the e.pression Jnot .J because both of its members have a Jnot .J in their DN& con3unctions+
The group consisting of both cells in the bottom ro* reduces to Jnot !J+ Thus the minimi,ed
logical e.pression is
S S
. C !
3-,ariable Barnaugh maps
6ere is a 3-variable Marnaugh map-

(n this map) the largest possible group si,e is @+ A group of si,e @) of course) reduces to true+
9e can also ma1e groups of si,e " or 2+ (t is important to understand that the leftmost column in
this Marnaugh map is considered to be ad3acent to the rightmost column+ Thus *e can create
groups li1e this one of si,e "-

That group reduces to the e.pression !+
9hen grouping 1Hs) the ob3ect is to get ever! 1 into as large a group as possible+ ometimes it
is not possible to put a cell into a group2 in that case) the minimi,ed e.pression *ill contain one
con3unction for that cell all b! itself+ As before) if it helps ma1e larger groups *e can put a cell in
more than one group+
Nse a Marnaugh map to minimi,e the follo*ing DN&-
S S S S S S S S S
. ! , C . ! , C . ! , C . ! , C . ! , C . ! ,
6ere is the Marnaugh map-

The reduced e.pressions
S S S
. , C ! C . ,
The *orst case situation *hen attempting to minimi,e a DN& is to end up *ith a Marnaugh map
that loo1s li1e a chec1erboard+ (n such a case) no minimi,ation is possible+
!-,ariable Barnaugh 4aps
A "-variable Marnaugh map loo1s li1e this-

(n a map of this si,e) *e can have groups of si,e 1>) @) ") or 2+ Dou must reali,e that the
leftmost column is considered to be ad3acent to the rightmost column and that the top ro* is
ad3acent to the bottom ro*+ 6ere are some "-variable Marnaugh maps and the resulting
Chapter $ D Combinational logic circuit Design
%+1 8vervie*
%+2 6alf Adder and &ull Adder
%+3 ;ode converters

%+" #;D to even egment Displa! decoder

%+% 5.clusive-8R and 5.clusive-N8R ;ircuits

%+> Decoders and 5ncoders

%+? :ultiple.ers Demultiple.ers

%+@ :ultilevel NAND and N8R gates

0.1 O6er6ie/

E Addition and subtraction of binar! data is fundamental
F Need to determine hard*are implementation
E Represent inputs and outputs
F (nputs- single bit values) carr! in
F 8utputs- um) ;arr!
E 6ard*are features
F ;reate a single-bit adder and chain together
E ame hard*are can be used for addition and subtraction *ith minor changes
E Dealing *ith overflo*
F 9hat happens if numbers are too bigK
0." Cal* Adder and 2ull Adder

Cal* Adder
At this point it *ould be useful to revie* the section on #inar! Addition+
A half adder performs a relativel! simple tas1+ (t ta1es in t*o 1-bit numbers) and adds them+ (f
the digit is supposed to be a 1 then the input is on /as is standard in all these devices0+ (t has
t*o outputs-

A= #= = ;1
= = = =
= 1 1 =
1 = 1 =
1 1 = 1

&rom figure
As *e can see the truth table given for this has a direct lin1 to the rules for adding #inar!
numbers+ The implementation of a 6alf Adder from basic logic elements is ver! eas! to *or1 out
from the Truth Table2 *e *ant the sum to be 8n *hen either but not both of the inputs are on)
and *e *ant a carr! *hen both inputs are on+
Dec #inar!
1 1
C1 C1
---- ---
2 1=

2ull Adder
E &ull adder includes carr! in ;i
Notice interesting pattern in Marnaugh map+
6alf Adders are all right as long as !ou onl! *ant to add single bit numbers+ #ut if *e *ant to
add numbers *ith more than one bit in them then *e need a logic element *hich adds but also
has a Hcarr! inH /Thin1 about it- *here does the carr! out from each element go toK0 o that is
*h! *e have the /single bit0 &ull Adder+ The follo*ing diagram sho*s itHs Truth Table and itHs
implementation













;i Ai #i i ;i C1
= = = = =
= = 1 1 =
= 1 = 1 =
= 1 1 = 1
1 = = 1 =
1 = 1 = 1
1 1 = = 1
1 1 1 1 1