IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

8, AUGUST 2012 3513

A ZVS Interleaved Boost AC/DC Converter Used
in Plug-in Electric Vehicles
Majid Pahlevaninezhad, Member, IEEE, Pritam Das, Member, IEEE, Josef Drobnik, Senior Member, IEEE,
Praveen K. Jain, Fellow, IEEE, and Alireza Bakhshai, Senior Member, IEEE
AbstractThis paper presents a novel, yet simple zero-voltage
switching (ZVS) interleaved boost power factor correction (PFC)
ac/dc converter used to charge the traction battery of an electric
vehicle from the utility mains. The proposed opology consists of
a passive auxiliary circuit, placed between two phases of the in-
terleaved front-end boost PFC converter, which provides enough
current to charge and discharge the MOSFETs output capacitors
during turn-ON times. Therefore, the MOSFETs are turned ON
at zero voltage. The proposed converter maintains ZVS for the
universal input voltage (85 to 265 V
rms
), which includes a very
wide range of duty ratios (0.071). In addition, the control system
optimizes the amount of reactive current required to guarantee
ZVS during the line cycle for different load conditions. This opti-
mization is crucial in this application since the converter may work
at very light loads for a long period of time. Experimental results
from a 3 kW ac/dc converter are presented in the paper to evalu-
ate the performance of the proposed converter. The results show a
considerable increase in efciency and superior performance of the
proposed converter compared to the conventional hard-switched
interleaved boost PFC converter.
Index TermsAC/DC converter, continuous current mode
(CCM), dc/dc converter, interleaved boost converter, power fac-
tor correction (PFC), zero-current switching (ZCS), zero-voltage
switching (ZVS).
NOMENCLATURE
i
LA
Inductor current ripple of boost A (A).

l
Line frequency (rad/s).
Phase-shift between leading leg and lagging leg
pulses.
C
So
Output capacitance of the boost MOSFET (F).
D PFC duty ratio.
f
s
Switching frequency (Hz).
i
Aux,p
Peak value of the auxiliary circuit current (A).
Manuscript received September 27, 2011; revised December 20, 2011;
accepted January 20, 2012. Date of current version April 20, 2012. This work
was supported by Freescale Semiconductor, Inc., Tempe, Arizona. Recom-
mended for publication by Associate Editor A. Emadi.
M. Pahlevaninezhad, P. K. Jain, and A. Bakhshai are with the Queens
Centre for Energy and Power Electronics Research (ePOWER), Queens
University, Kingston, ON K7L3N6, Canada (e-mail: [email protected];
[email protected]; [email protected]).
P. Das was with the Queens Centre for Energy and Power Electronics
Research (ePOWER), Queens University, Kingston, ON K7L3N6, Canada.
He is now with Murata Power Solutions, Markham, ON L3S0J3, Canada
(e-mail: [email protected]).
J. Drobnik is with Freescale Semiconductor, Inc., Tempe, AZ 85284 USA
(e-mail: [email protected]).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2012.2186320
i
in
Input current of power factor correction (PFC) (A).
i
LA
Inductor current of boost A (A).
i
LB
Inductor current of boost B (A).
i
SA1
Switch S
A1
current (A).
I
BAT
Battery current (A).
I
o
DC output current (A).
I
P
Peak current of the boost inductor (A).
I
ref
Peak value of the auxiliary circuit reference current
(A).
I
V
Valley current of the boost inductor (A).
k
1
Controller coefcient.
p
in
Instantaneous input power (W).
p
ref
Instantaneous input power reference value (W).
P
in,pk
Peak input power (W).
P
ref
Power reference value (W).
r
o
Load incremental resistance ().
P
sw
Switching losses (W).
R
e
Converter effective load resistance ().
R
L
PFC inductor series resistance ().
t Time (s).
t
d
Dead time (s).
u Control input.
v
AUX
Voltage across auxiliary circuit (V).
v
in
Instantaneous input voltage of PFC (V).
V
BAT
Battery voltage (V).
V
d
Output diode forward voltage drop (V).
V
o
DC output voltage (V).
x State variables.
ESR Equivalent series resistance ().
SiC Silicon carbide.
Si Silicon.
I. INTRODUCTION
E
LECTRIC vehicle (EV) power conditioning systems usu-
ally utilize a high-energy battery pack to store energy for
the electric traction system [1]. A typical block diagram of the
power conditioning system in an EV is shown in Fig. 1. The
high-energy battery pack is typically charged from a utility ac
outlet [2]. This energy conversion during the battery charging is
performed by an ac/dc converter. Such ac/dc converters, which
are used to charge the high-energy battery, usually consist of
two stages: front-end boost converter, which performs input
PFC and ac/dc conversion, and full-bridge dc/dc converter for
battery charging and galvanic isolation [3]. PFC is essential to
improve the quality of the input current, which is drawn from
the utility so as to comply with the regulatory standards like IEC
61000-3-2.
0885-8993/$31.00 2012 IEEE
3514 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
Fig. 1. Block diagram of EV power conditioning system.
Fig. 2. Interleaved boost PFC schematic.
Boost converters are generally used to realize input PFC and
ac/dc conversion [4][9] in the front end of an ac/dc converter. In
high power applications, interleaving continuous current mode
(CCM) PFC boost stages, as shown in Fig. 2, is a very common
approach to effectively decrease the inductor footprint and vol-
ume as well as the output capacitor current ripple [7][14]. A
typical boost PFC utilizes a switch and a diode. In the range of
a few kilowatt, power MOSFETs are usually used to realize the
boost converter.
The main sources of switching losses in boost PFCconverters
are hard turn-ON of the MOSFET and the reverse recovery
of the boost diode during its turn-OFF. In order to eliminate
the switching losses in a MOSFET-based boost PFC converter,
different auxiliary circuits have been proposed [15][25]. The
typical placement of a zero-voltage switching (ZVS) auxiliary
circuit is shown in Fig. 3. Commonly, these auxiliary circuits
consist of a combination of passive components such as small
inductors and capacitors and additional active components such
as MOSFETs and diodes.
Auxiliary circuits in ZVS- puslewidth modulation (PWM)
single-switch converters are generally one of two types, nonres-
onant [15] and resonant [16][23], depending on whether there
is an LC resonant network placed in series with the switch.
Typical nonresonant and resonant ZVS auxiliary circuits are
shown in Fig. 4(a) and (b)(d), respectively. There is a third
type, dual auxiliary circuits [23], that is a combination of both
resonant and nonresonant circuits. These circuits, which were
rst categorized in [23], are shown in Fig. 4(e).
Fig. 3. Placement of ZVS auxiliary circuit in boost PFC converter.
For each converter in Fig. 4, the auxiliary switch is turned
ON just before the main converter switch is to be turned ON.
The auxiliary switch is used to discharge the capacitor across the
main switch so that it can turn ONwith ZVS. Some capacitance,
either internal to the device and/or external, is needed to slow
down the rise in voltage across the main switch so that it can
turn OFF with ZVS. The auxiliary switch is turned OFF shortly
after the main switch is turned ON, and all the energy in the
auxiliary circuit is eventually transferred to the output. After this
is done, the auxiliary circuit is fully deactivated and the converter
operates like a conventional PWM converter. The components
in the auxiliary circuit have lower ratings than those in the main
power circuit because the circuit is active for a fraction of the
switching cycle. This allows a device that can turn ON with
fewer switching losses than the main switch to be used as the
auxiliary switch.
The addition of an active auxiliary circuit to a PWM con-
verter can also eliminate the reverse-recovery current of the
main power boost diode if a Si device is used. It can be seen
from Fig. 4 that all the auxiliary circuits have an inductor lo-
cated in series with the auxiliary switch. This allows current
to be gradually transferred away from the boost diode to the
auxiliary switch when it is turned ON so that the charge in the
diode is slowly removed during turn-OFF; with such a gradual
transition from conduction state to OFF-state of the diode, its
reverse-recovery current can be greatly reduced, thus, eliminat-
ing reverse recovery losses.
The key limitations of the previously proposed auxiliary cir-
cuits for single-switch boost PFC converters are the use of extra
semiconductor devices such as diodes and MOSFETs [15][23]
as well as passive components and the extra losses associated
with the auxiliary circuit. In resonant-type auxiliary circuits,
the main switch can suffer from addition current stress [20],
while in nonresonant-type auxiliary circuits [15], the auxiliary
switch may undergo hard switching; these key problems in ZVS
auxiliary circuit tend to somewhat offset the gain in efciency
achieved by soft switching of the main boost switches. In ad-
dition, the gating pulse of the auxiliary switch needs to be pre-
cisely synchronized to that of the main switch, which adds to
the complexity of the boost PFC control system.
Auxiliary circuits with active semiconductor devices have
also been used to achieve ZVS in interleaved boost PFCconvert-
ers [24][26]. The key issue related to such auxiliary circuits is
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3515
Fig. 4. ZVS-PWM acdc boost converters with active auxiliary circuits.
that basically two auxiliary circuits are implemented to achieve
ZVS in both phases. This leads to use of multiple semiconductor
switching devices to implement the auxiliary circuits [24][26],
which increases the cost and complexity of the overall converter.
ZVS in interleaved boost converter can be easily achieved if
the current in the boost inductors is always in critical conduction
mode [27], but the main problem related to such critical con-
duction mode boost converters is the limitation of the maximum
power handling capacity of the overall converter, typically such
converters are applicable for operation around 1 kW and their
inherent line current distortion. Magnetically coupled boost in-
ductors in interleaved boost PFC converter can help achieving
ZVS of the main switches [28], but design and mass replication
of such coupled boost inductor cannot be done easily.
In [29], a simple passive auxiliary circuit was proposed to
achieve ZVS in interleaved boost converter for dcdc voltage
conversion applications. The main drawback of this circuit is
that the duty ratio of the boost switches has to remain strictly
above 0.5, which cannot be guaranteed in PFC ac/dc applica-
tions especially for universal ac inputs that vary from 85 to
265 V
rms
. In addition, the amount of reactive current owing
through this auxiliary circuit should be adjusted for the maxi-
mumload, so as to guarantee ZVS for all conditions. This causes
excessive circulating current for light-load conditions and de-
creases the efciency of the converter at light loads. In battery
charger applications, since the converter has to operate at light
loads for a long period of time, this constant circulating current
signicantly deteriorates the performance of the converter.
In this context, it should also be noted that in EV power
conditioning systems, high efciency of the power stages is im-
perative. The front-end ac/dc boost PFC converter plays a key
role in transferring power from external utility mains to the EV
battery packs, and the boost diodes in this converter are key
source of losses. Presently, SiC diodes are gaining popularity
in ac/dc boost converters [30] since they have near-zero reverse
recovery losses but normally SiC diodes have greater forward
voltage drops, typically 2.4 V and more as compared to 1.2 V in
Si diodes for a 600 V device, which is required in this applica-
tion. For instance, a 600-V 10-A SiC diode C3D10060A, from
CREE, Inc., Durham, NC, has a forward voltage drop of 2.4 V
compared to a 600-V 10-A fast recovery diode 10ETF06PBF,
from Vishay, Shelton, CT, which has less than 1.2 V forward
3516 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
voltage drop. In addition, the thermal coefcient of SiC diodes
on the forward voltage drop is positive, implying that the voltage
drop increases with temperature, while the one for Si diode is
negative. Thus, the use of Si diodes in very high power (3 kW
or more) ac/dc boost PFC converter contributes to high reverse-
recovery losses, while the use of SiC diodes contributes to very
high conduction losses in such converters.
In this paper, a novel interleaved boost PFC converter is pro-
posed to achieve soft switching in the main switches of the
converter. The proposed converter implements soft switching
through a simple passive auxiliary circuit placed in between the
two phases of the interleaved boost converter. This auxiliary cir-
cuit is able to provide reactive current to charge and discharge the
output capacitors of the boost MOSFETs and guarantee ZVS.
Since there are no extra semiconductors used in the auxiliary
circuit, high efciency and reliability are the main advantages of
the proposed system. In addition, the proposed converter is able
to optimize the amount of reactive current required to implement
soft switching based on the load condition and the input voltage.
Thus, the conduction losses caused by the auxiliary circuit are
minimized based on the operating condition.
This paper is organized as follows. In Section II, the steady-
state analysis of the proposed interleaved boost PFCconverter is
explained. Aqualitative study of the proposed converter is given
in Section III. Section IV presents the proposed control system
for the interleaved boost converter. A summary of the design
procedure for the auxiliary circuit inductor is provided in Section
V. Experimental results obtained from a 3 kW prototype are
presented in Section VI and nally Section VII is the conclusion.
II. STEADY-STATE ANALYSIS OF THE ZVS INTERLEAVED
BOOST PFC CONVERTER
Fig. 5 shows the power circuit of the ZVS interleaved boost
PFC converter. In this converter, two boost converters operate
with 180

phase shift in order to reduce the input current ripple

of the converter. This 180

phase shift can be used to provide

reactive current for realizing ZVS for power MOSFETs. This
auxiliary circuit consists of a HF inductor and a dc-blocking ca-
pacitor. Since there may be a slight difference between the duty
ratios of the two phases, this dc-blocking capacitor is necessary
to eliminate any dc current arising from the mismatch of the
duty ratios of the main switches in the practical circuit.
Fig. 6 shows the key waveforms of the converter for D >
0.5. According to this gure, there are eight operating modes in
one switching cycle of the converter. The operating modes are
explained as follows.
Mode I (t
0
< t < t
1
): This mode starts when the gate pulse
is applied to S
A1
. Once the voltage is applied to the gate, S
A1
is turned ON under zero voltage. Since S
A1
and S
B1
are ON
during this interval, the voltage across the auxiliary inductor
is zero. Thus, the current through the auxiliary circuit remains
constant at I
Aux,p
. During this interval, the switch S
A1
current,
i
SA1
, is given by:
i
SA1
(t) = I
V
I
Aux,p

v
in
L
A
(t t
0
) . (1)
Fig. 5. Proposed ZVS interleaved boost PFC schematic.
Fig. 6. Key waveforms of the converter for D > 0.5.
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3517
Since the two phases have 180

phase shift, the value of t

1
is
given by:
t
1
t
0
= (D 0.5) T
s
. (2)
Therefore, the duty ratio is given by
D = (t
1
t
0
) f
s
+
1
2
. (3)
Inserting (2) into (1), the value of the switch current is calcu-
lated at t
1
I
1
= I
V
I
Aux,p
(t)
v
in
2L
A
f
s

v
2
in
L
A
f
s
V
o
. (4)
This mode ends once the gate voltage has been removed from
S
B1
.
Mode II (t
1
<t <t
2
): This mode is the dead time between the
phase B MOSFETs. During this interval, the auxiliary circuit
current charges the output capacitance of S
B1
and discharges
the output capacitance of S
B2
. In this mode, the average voltage
across the boost inductance L
B
is zero. Therefore, the current
through L
B
remains constant at its peak value. The voltage
across the auxiliary inductor is given by:
v
AUX
(t) =
V
o
(t
2
t
1
)
(t t
1
). (5)
Thus, the current through auxiliary circuit is given by:
i
AUX
(t) = I
Aux,p

V
o
2 (t
2
t
1
) L
AUX
(t t
1
)
2
(6)
t
2
t
1
= t
d
is the dead time between S
B1
and S
B2
. During
this period, the output capacitors of the MOSFETs should fully
charge and discharge in order to guarantee ZVS for S
B1
and
S
B2
. Thus, the dead time is calculated as follows:
I
P
+I
Aux,p

V
o
2L
AUX
t
d
= 2C
So
V
o
t
d
(7)
t
d
=
(I
P
+I
Aux,p
)L
AUX
V
o
+

(I
P
+I
Aux,p
)
2
L
2
AUX
V
2
o
4C
So
L
AUX
(8)
the current through switch S
A1
is calculated as follows:
i
SA1
(t) = I
V
I
Aux,p

v
in
L
A
(t t
0
) +
V
o
2t
d
L
AUX
(t t
1
)
2
.
(9)
This mode ends when the output capacitors completely
charged and discharged. The switch current i
SA1
at this point is
given by:
I
2
= I
V
I
Aux,p

v
in
L
A
(t
d
+t
1
t
0
) +
V
o
2L
AUX
t
d
. (10)
Mode III (t
2
< t < t
3
): Once the output capacitors of S
B1
and S
B2
have been charged and discharged completely, the gate
signal of S
B2
is applied and S
B2
is turned ON under ZVS.
During this interval, the voltage across the auxiliary circuit is
V
o
. The current through the auxiliary inductor, inductor L
A
and switch S
A1
, is given by:
i
AUX
= I
Aux,p

V
o
2L
AUX
t
d

V
o
L
AUX
(t t
2
) (11)
i
LA
(t) = I
V
+
v
in
L
A
(t t
0
) . (12)
i
SA1
(t) = I
V
I
Aux,p

v
in
L
A
(t t
0
)
+
V
o
2L
AUX
t
d
+
V
o
L
AUX
(t t
2
) . (13)
This mode ends once the gate signal of S
B2
has become zero
(t
3
= t
0
+ 0.5 T
s
t
d
). The value of i
SA1
at this point is given
by:
I
3
(t) = I
V
I
Aux,p
+
v
in
2f
s
L
A

v
in
t
d
L
A
+
V
o
2L
AUX
t
d
+
V
o
f
s
L
AUX
(1 D)
2V
o
L
AUX
t
d
. (14)
Mode IV (t
3
<t <t
4
): During this mode, the output capacitor
of S
B2
is charging from zero to V
o
and the output capacitor
of S
B1
is discharging from V
o
to zero. This period is actually
the dead time between S
B2
and S
B1
(t
4
t
3
= t
d
). The auxil-
iary inductor current, the boost inductor current, and the switch
current, during this mode, is given by:
i
AUX
(t) = I
Aux,p
+
3V
o
2L
AUX
t
d

V
o
f
s
L
AUX
(1 D)
V
o
2t
d
L
AUX
(t t
3
)
2
(15)
i
LA
(t) = I
V
+
v
in
L
A
(t t
0
) (16)
i
SA1
(t) = I
V
I
Aux,p

v
in
L
A
(t t
0
)
+
V
o
2L
AUX
t
d
+
V
o
L
AUX
(t t
2
) . (17)
This mode ends once the gate signal is applied to S
B1
. The
value of i
SA1
at this instant is given by:
I
4
(t)=I
V
I
Aux,p
+
v
in
2f
s
L
A
+
V
o
L
AUX
t
d
+
V
o
f
s
L
AUX
(1 D).
(18)
Mode V (t
4
<t <t
5
): This mode starts when the gate signal is
applied to S
B 1
. Once the gate has been applied, S
B 1
is turned ON
under ZVS. Since S
A1
and S
B1
are ON during this period, the
voltage across the auxiliary inductor is zero; hence, the auxiliary
inductor current remains constant at its peak value, I
Aux,p
. The
boost inductor current and the switch current, during this mode,
are given by:
i
LA
(t) = I
V
+
v
in
L
A
(t t
0
) (19)
i
SA1
(t) = I
V
+I
Aux,p

v
in
L
A
(t t
0
) . (20)
3518 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
This mode ends once the gate signal is removed from S
A1
.
The value of i
SA1
at this time is given by:
i
SA1
(t) = I
V
+I
Aux,p

v
in
f
s
L
A
D. (21)
Mode VI (t
5
<t <t
6
): During this mode, the output capacitor
of S
A1
is charging from zero to V
o
and the output capacitor of
S
A2
is discharging from V
o
to zero. This period is actually the
dead time between S
A1
and S
A2
(t
6
t
5
= t
d
). In this period,
the current through the boost inductor L
A
remains constant at
its peak value. The auxiliary inductor current i
AUX
is given by:
i
AUX
(t) = I
Aux,p
+
V
o
2t
d
L
AUX
(t t
5
)
2
. (22)
This mode ends once the output capacitors have completely
been charged and discharged.
Mode VII (t
6
< t < t
7
): During this mode, the voltage across
the auxiliary circuit is V
o
; hence, the current through the auxil-
iary circuit is given by:
i
AUX
(t) = I
Aux,p
+
V
o
2L
AUX
t
d
+
V
o
L
AUX
(t t
6
) . (23)
During this mode, the MOSFET channel S
A2
is conducting
the current to the output. The current through this switch is given
by:
i
SA2
(t) = I
Aux,p

V
o
2L
AUX
t
d
+
V
o
L
AUX
(t t
6
)
+I
P

v
in
V
o
L
A
(t t
6
) . (24)
The peak value of this current is given by:
I
5
(t) = I
Aux,p
+
V
o
2L
AUX
t
d
+I
P
. (25)
This mode ends when i
SA2
reaches zero. Thus t
7
is given by:
t
7
= t
6
+
I
Aux,p
(V
o
/2L
AUX
)t
d
(V
o
/L
AUX
) + (v
in
V
o
/L
A
)
. (26)
Mode VIII (t
7
<t <t
8
): During this mode, the output capacitor
of S
A1
is discharging from V
o
to zero and the output capacitor
of S
A2
is charging from zero to V
o
. In this mode, the current
through L
A
is at its minimum value I
V
and the excess current
from the auxiliary circuit charges and discharges the output
capacitors. The auxiliary inductor current is given by:
i
AUX
(t) = I
Aux,p
+
V
o
2L
AUX
t
d
+
V
o
L
AUX
I
Aux,p
(V
o
/2L
AUX
)t
d
(V
o
/L
AUX
)+((v
in
V
o
)/L
A
)
+
V
o
2L
AUX
(t t
7
)
2
.
(27)
Since this mode is the dead time between S
A1
and S
A2
, t
8
=t
7
+
t
d
. This mode ends once the output capacitors have been charged
Fig. 7. Key waveforms of the converter for D < 0.5.
and discharged completely. Fig. 7 shows the key waveforms of
the circuit for D < 0.5. According to this gure, the modes of
operation are the same for the proposed circuit.
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3519
Fig. 8. Boost inductor valley current, peak current, and auxiliary inductor
current.
III. QUALITATIVE STUDY
In this section, some salient features of the proposed converter
are discussed. According to the waveforms of the converter in
Figs. 6 and 7, all MOSFETs of the interleaved boost converter
are turned ON under zero voltage and the output MOSFETs
are turned OFF at nearly zero current. This implies that the
MOSFETs enjoy having near-zero switching losses. In order
to guarantee ZVS for the MOSFETs, the inductive current of
the auxiliary circuit should be enough to neutralize the input
current and discharge and charge the output capacitors of the
MOSFETs during turn-ON times of S
A1
and S
B1
. Also, the
dead time between the gate pulses should be enough to allow
complete charging and discharging of the output capacitors of
the switches. Therefore, rst the auxiliary inductor should be
designed so as to provide enough inductive current to charge
and discharge the capacitors, then the dead time should be prop-
erly adjusted to have enough time to complete the charge and
discharge. Since the input current helps to charge and discharge
the output capacitors of S
A2
and S
B2
, ZVS is automatically
guaranteed for S
A2
and S
B2
.
Fig. 8 shows the boost inductor valley current, peak current,
and the auxiliary inductor current. In order to guarantee ZVS,
the auxiliary inductor current not only should neutralize the
valley current I
V
, but also should provide enough current to
charge and discharge the output capacitors. The valley current
I
V
and the peak current I
P
are given by:
I
V
(t) =
P
in
V
in
|sin(
l
t)|

V
in
| sin(
l
t)|1 (V
in
| sin(
l
t)|)/V
o
2L
A
f
s
(28)
I
P
(t) =
P
in
V
in
| sin(
l
t)|
+
V
in
| sin(
l
t)|(1 (V
in
| sin(
l
t)|)/V
o
)
2L
A
f
s
. (29)
Fig. 9. Semiconductors current waveforms for the conventional boost PFC
and the proposed interleaved boost PFC.
The peak value of the auxiliary inductor current I
Aux,p
is
given by:
I
Aux,p
(t) =
P
in
V
in
| sin(
l
t)|

V
in
| sin(
l
t)|1 (V
in
| sin(
l
t)|)/V
o
2L
A
f
s
+
2C
So
V
o
t
d
. (30)
Fig. 9 compares the current waveforms of the MOSFET and
boost diode in the conventional boost PFC converter and those
of the MOSFETs in the interleaved boost PFC with the auxil-
iary circuit. According to this gure, there are two main sources
of switching losses in the conventional boost PFC converter.
The rst source of switching losses is the turn-ON losses of the
boost MOSFET and the second source is the reverse recovery
of the output diode. The former one not only deteriorates the
efciency of the converter, but also introduces a lot of switching
noise through the draingate capacitance of the MOSFET to the
control circuit. This leads to an unreliable operation of the con-
verter, while the later one creates a lot of losses in the converter.
Recently, SiC diodes are used to mitigate the reverse-recovery
losses of the output diodes. However, the SiC diodes usually
have a large forward voltage drop for this application (typically
the forward voltage drop in SiC diodes is 2.4 V as compared
to around 1.2 V in Si diodes), which creates extra conduction
losses in the converter during their conduction intervals and ef-
fectively decreases the advantage such diodes have due to zero
reverse recovery, especially at very high output power and low
ac inputs.
According to Fig. 9, the proposed auxiliary circuit can ef-
fectively cancel out the positive current imposed by the input
inductor during the MOSFET turn-ON times and completely
eliminate the turn-ON losses of the boost MOSFET. In ad-
dition, the auxiliary inductor current brings down the current
prior to the output MOSFET turn-OFF times; hence, the output
MOSFET undergoes near zero-current switching (ZCS) turn-
OFF. Therefore, the switching losses are almost zero in the
proposed converter.
3520 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
Fig. 10. Boost inductor currents and auxiliary circuit current.
Fig. 11. Auxiliary circuit maximum current versus duty ratio.
IV. PROPOSED CONTROL SYSTEM
Fig. 10 shows the current through the boost inductors and
the auxiliary circuit current in half line cycle. According to this
gure, the envelope of the auxiliary circuit current should be
slightly higher than the valley current of each boost inductors.
This implies that in order to optimally control the amount of
reactive current through the auxiliary circuit, the peak value
of the auxiliary inductor current should follow the envelope
given by (30), which implies that the envelope of the auxiliary
circuit current should be at its maximumwhen the boost inductor
current is at its maximum. Fig. 11 shows the peak value of the
auxiliary inductor current versus the boost duty ratio. According
to this gure, for duty ratios higher than 0.5, the maximum
value of the auxiliary circuit current decreases as duty ratio
increases. This implies that if the input voltage is low enough
Fig. 12 (a) Duty ratios for different input voltage. (b) Auxiliary circuit maxi-
mum current for different input voltage.
to have duty ratios higher than 0.5 for the whole line cycle,
the envelope of the auxiliary current follows the shape of the
inductor current. In other words, the peak value of the auxiliary
inductor current is maximum at the peak value of the input
voltage, and as the input voltage decreases to zero, the peak value
of the auxiliary inductor decreases to zero too. Fig. 12(a) and (b)
illustrates this phenomenon. These gures show the variation of
the duty ratio and the envelope of the auxiliary circuit current for
different input voltages, respectively. According to this gure,
the auxiliary circuit operates optimally if the duty ratios are
higher than 0.5 during the half line cycle. This condition is
satised for input voltages less than 141 and 400 V
dc
output.
However, for universal input voltage range (85 to 265 V
rms
),
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3521
Fig. 13. Auxiliary circuit maximum current for different loads.
this condition is not satised and duty ratio becomes very small
for higher voltages.
In addition, the peak value of the auxiliary circuit current
should be adjusted based on the load condition in order to op-
timize the circulating current between the two phases of the in-
terleaved boost converter. Fig. 13 depicts the optimal envelopes
of the auxiliary circuit current for different loads. Therefore, in
order to optimize the circulating current, the envelope should be
just enough to overcome the valley current of the boost inductor
in the half cycle.
Considering the aforementioned discussion, there are two
main difculties related to the optimization of the circulating
current in the proposed converter. The rst problem is the op-
eration with duty ratios lesser than 0.5 and the second issue is
optimizing the circulating current for different load conditions.
Fig. 14 shows the block diagramof the proposed control system.
The proposed control system includes an external voltage loop,
internal current loop, and a switching frequency control loop.
Therefore, a frequency loop is added to the control system to
optimize the circulating current of the auxiliary circuit based
on the load and duty ratio of the converter. Such load-adaptive
switching frequency variation has been proved to increase ef-
ciency in ZVS converters [36].
Fig. 15 shows the typical switching frequency variation at
heavier and lighter loads. At heavy loads, the frequency is lower
to provide more reactive current in the auxiliary circuit to over-
come higher values of I
V
and charge and discharge the output
capacitors. Whereas at light loads, the frequency is higher to
reduce the auxiliary circuit current in order to avoid any ex-
tra circulating current between the two phases. The required
auxiliary circuit current for different loads is determined by:
I
Aux,p
= I
ref

i
LA
2
+
2C
So
V
o
t
d
. (31)
The auxiliary circuit current is given by:
I
Aux,p
=
v
in
2L
AUX
f
s
. (32)
The boost inductor ripple is given by:
i
LA
=
v
in
(1 (v
in
/V
o
))
L
A
f
s
. (33)
Inserting (32) and (33) into (31) determines the desired
switching frequency of the converter
f
s1
=
v
in
L
A
+v
in
(1 (v
in
/V
o
))L
AUX
I
ref
+ (2C
So
V
o
/t
d
)
. (34)
Fig. 16 shows the variation of the frequency with respect to
the converter output power. Owing to the change of frequency,
the circulating current is optimized for a very wide range of
operation. Since the converter is used to charge the traction
battery, there is actually a need for very wide range of operating
conditions and the converter has to work at very light loads for
a long period of time also. Thus, this optimization is imperative
in this particular application.
The other issue regarding the auxiliary circuit was the oper-
ation with less than 0.5 duty ratio for input voltage higher than
141 V
rms
. In order to accommodate this issue, another block
is added to the control circuit to modify the frequency for duty
ratios less than 0.5. Fig. 17 illustrates the operation of the auxil-
iary circuit for high input voltage. The auxiliary circuit follows
the sinusoidal waveform from D = 1 to D = 0.5. However, af-
terward, the auxiliary circuit current decreases, which hinders
the auxiliary circuit to provide ZVS condition for the power
MOSFETs. In the proposed control system, the frequency is
modied once the duty ratio has reached 0.5. The frequency
prole and the modied auxiliary circuit current are depicted
in Fig. 17. The peak value of the auxiliary circuit current is
given by:
I
Aux,p
=

V
o
D
2L
AUX
f
s
for D < 0.5
V
o
(1 D)
2L
AUX
f
s
for D 0.5
. (35)
Therefore, the frequency can be modied so as to follow the
sinusoidal reference for the auxiliary circuit current. Frequency
prole as a function of duty ratio is shown in Fig. 18. According
to this gure, the frequency is constant from D = 1 to D =
0.5, and after this point, the frequency is modied to have the
auxiliary current follow the sinusoidal waveform, as shown in
Fig. 18. Therefore, for D < 0.5 (or v
in
> 200 V), the frequency
is given by:
f
s
=
(1 (v
in
/V
o
))
v
in
/V
o
f
s1
. (36)
There are two main points related to the proposed control
system. First, the frequency loop is completely decoupled from
the duty cycle loop. Fig. 19 illustrates the fact that by changing
the frequency of the saw-tooth counter, the duty cycle does not
change (i.e., D
1
= D
2
). Second, the frequency change does
not tamper the operating modes of the converter in terms of
operating under CCMof the input inductors. Since the frequency
is higher for light loads, the control system helps the converter
to work in CCM for wider range of loads. In addition, for higher
3522 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
Fig. 14. Control system block diagram.
Fig. 15. Frequency change for different loads.
input voltage, frequency decreases at the peak value of the input
current. Therefore, reducing the frequency does not bring the
converter into discontinuous conduction mode.
Fig. 16. Switching frequency variation versus load.
V. AUXILIARY INDUCTOR DESIGN
In this section, the design of the auxiliary inductor is explained
in detail. The auxiliary inductor should be designed so as to
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3523
Fig. 17. Typical switching frequency variation for half an input ac line cycle
above 141 V
rms
.
Fig. 18. Switching frequency variation versus duty ratio.
Fig. 19. PWM pulses for different frequencies.
provide enough energy to neutralize the energy in the boost
inductor as well as charge and discharge the output capacitors
of the MOSFETs. Thus, the key design criteria which needs are
as follows.
1) Design the auxiliary inductor to have enough energy to
be able to neutralize the valley current of the boost induc-
tor and charge and discharge the output capacitors of the
MOSFETs.
2) Design enough dead time to provide enough time for the
output capacitors to charge and discharge.
The energy required to neutralize the boost inductor and
charge and discharge the output capacitors of the MOSFETs
is given by:
W =
1
2
L
A

P
in
V
in

V
in
(1 (V
in
/V
o
))
2L
A
f
s

2
+C
So
V
2
o
. (37)
The energy of the auxiliary inductor should be greater or
equal to the energy derived in (37). Therefore, we have:
1
2
L
AUX
I
2
Aux,p

1
2
L
A

P
in
V
in

V
in
(1 (V
in
/V
o
))
2L
A
.f
s

2
+C
So
V
2
o
. (38)
The peak value of the auxiliary circuit is given by:
I
Aux,p
=
V
o
(1 (V
in
/V
o
))
2L
AUX
f
s
. (39)
Inserting (39) into (38) results in the following:
L
AUX

(V
2
in
(1 (V
in
/V
o
))
2
/4f
2
s
)
L
A
((P
in
/V
in
) (V
in
(1 (V
in
/V
o
)) /2L
A
f
s
))
2
+ 2C
S o
V
2
o
.
(40)
The dead time should be designed based on (8), which is
rewritten again:
t
d
=
(I
P
+I
Aux,p
)L
AUX
V
o
+

(I
P
+I
Aux,p
)
2
L
2
Aux
V
2
o
4C
So
L
AUX
. (41)
Therefore, the design procedure is summarized in the follow-
ing steps.
1) Select the minimum switching frequency, which corre-
sponds to the peak value of the input current.
2) Calculate the value of the auxiliary inductance using (40).
3) Choose dead time so as to have enough time to completely
charge and discharge the output capacitors of the MOS-
FETs using (41).
3524 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
TABLE I
CONVERTER SPECIFICATIONS
TABLE II
CONVERTER PARAMETERS
VI. EXPERIMENTAL RESULTS
A3 kWprototype is implemented to verify the performance of
the proposed converter. The converter specications are shown
in Table I and the designed parameters are shown in Table II.
Fig. 20 illustrates the system block diagram. At the input stage,
there is an inrush current protection, which limits the inrush
current of the converter. Since there is usually a big capacitor at
the output of the PFC, the inrush current to charge the capacitor
is very high and a circuit is required to limit this current. The next
block is the electromagnetic interference (EMI) lter, which is
designed to comply with the EMI standard (CISPR25/12) for
EVs [31], [32]. The following block is the input diode rectier.
It recties the input voltage for the two-phase interleaved boost
converter. The interleaved boost converter converts the rectied
input voltage to the intermediate dc-bus voltage. The output
capacitor of the interleaved boost converter is large (1.4 mF)
in order to decrease the 2nd harmonic voltage ripple caused by
the power ripple of the input boost PFC converter. In addition,
there is a differential-mode (DM) lter at the output of the PFC
in order to lter out the DM noise. At the output of this lter,
a clean dc-bus voltage is provided to the full-bridge converter.
Note that another EMI lter is required at the output of the
full-bridge converter in order to provide ltering for the EMI
noise injected by the inverter. Since the inverter is connected to
the high-energy battery, it injects switching noise to the battery
charger.
In order to implement the proposed controller,
TMX320F28335 eZdSP board is employed. This DSP
board has a oating-point DSP, which offers a very exible
environment for advanced mathematical calculations. This DSP
has a 12-bit ADC with a sequencer that is able to convert mul-
tiple analog signals sequentially [33]. It also has six enhanced
PWM (EPWM) modules, which can produce the desired PWM
signals with a very high degree of exibility [34]. The EPWM
channels can be practically used up to 100 KHz. However, for
the higher frequency range, high-resolution EPWM should be
used to achieve a high-resolution PWMsignal and to avoid limit
cycle and instability. The high-resolution module is embedded
in the DSP [35]. Since switching frequency is in the range
of 50240 KHz for the PFC and 220 KHz for the full-bridge
converter, the high-resolution module should be utilized to
produce the PWM pulses. In order to verify the performance
of the proposed converter, two converters are implemented.
The rst one is the conventional interleaved boost PFC and the
second one is the proposed converter.
Fig. 21(a) and (b) shows the prototype of the converter.
Fig. 21(a) shows the control, communication, and protection
circuits, and Fig. 21(b) illustrates the power circuit of the ac/dc
converter.
Fig. 22 illustrates the waveforms of the conventional inter-
leaved boost PFC converter. In Fig. 22, the gate pulse and the
drainsource voltage of the boost MOSFET are depicted. Ac-
cording to this gure, the boost MOSFET is hard switched
during the turn-ON and there are a lot of switching losses plus
switching noise generated by the hard switching.
Fig. 23 shows the waveforms of the proposed converter. Ac-
cording to this gure, the boost MOSFET is turned-ON under
zero voltage. This is due to the negative current provided by
the auxiliary circuit. Basically, this gure shows that the out-
put capacitor of the boost MOSFET is completely discharged
prior to applying the gate signal and once the voltage across
the MOSFET has become zero, the gate signal is applied to the
MOSFET.
Fig. 24 shows the waveforms of the two phases of the pro-
posed interleaved boost PFC converter as well as the auxiliary
circuit current. This gure explains how the auxiliary circuit
provides the reactive current for the both phases at the same
time. The waveforms of the proposed converter for large duty
ratios are shown in Fig. 25. Fig. 26 illustrates that the auxiliary
circuit current changes during a line cycle based on the input
current. The auxiliary circuit current is at its minimum at the
zero crossing points of the input current and it is at its maximum
at the peak of the input current. This implies that the auxiliary
circuit current adaptively changes based on the shape of the
input current and is optimized over the line cycle.
Fig. 27 illustrates the auxiliary circuit current around the input
current zero crossing point and Fig. 28 shows the proposed
converter waveforms around the peak point of the input current.
Fig. 29 shows the input voltage and the input current of the
proposed converter for 30% load and Fig. 30 illustrates the ones
for full load. It can be seen that the input current and input ac
voltage are absolutely in phase, thus, maintaining near unity
(0.999) power factor.
Fig. 31 shows the phase Aboost inductor current and the boost
MOSFET drainsource voltage. The input current and phase A
boost inductor currents are shown in Fig. 32. Figs. 33 and 34
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3525
Fig. 20. AC/DC converter block diagram.
Fig. 21 (a). AC/DC converter prototype (control, communication, and protec-
tion). (b). AC/DC converter prototype (power circuit).
Fig. 22. Conventional interleaved boost PFC waveforms.
depict the transient response of the converter against a 50%
positive step load and a 50% negative step load, respectively.
Fig. 35 shows the efciency curves of the conventional inter-
leaved boost PFC converter as well as the proposed interleaved
boost PFC converter. According to this gure, the proposed
converter shows better efciency for the whole load range com-
pared to the conventional one. The improvement in the efciency
can be attributed to the fact that the proposed converter elimi-
nates two main sources of losses, which are the turn-ON losses
of the boost MOSFETs and the reverse-recovery losses of the
output diodes.
3526 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
Fig. 23. Proposed interleaved boost PFC waveforms.
Fig. 24 Waveforms of two phases of the proposed interleaved boost converter
plus auxiliary circuit current.
Fig. 25. Waveforms of the proposed interleaved boost converter for large duty
ratios.
Fig. 26. Drainsource voltage of the boost MOSFET, auxiliary current, and
input current.
Fig. 27. Auxiliary current around the current zero crossing point.
Fig. 28. Proposed converter waveforms around the peak point of the line cycle.
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3527
Fig. 29. Proposed converter input voltage and input current for 30% load.
Fig. 30. Proposed converter input voltage and input current for full load.
Fig. 31. Phase A boost inductor current and boost MOSFET drainsource
voltage.
Fig. 32. Phase A boost inductor current and input current.
Fig. 33. Transient response of the converter to a 50% positive step load.
Fig. 34. Transient response of the converter to a 50% negative step load.
3528 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
Fig. 35. Efciency curves of the proposed and conventional converters
(v
in
= 220 V
ac
).
VII. CONCLUSION
In this paper, a new interleaved boost PFC converter is pro-
posed, which provides soft switching for the power MOSFETs,
through an auxiliary circuit. This auxiliary circuit provides re-
active current during the transition times of the MOSFETs to
charge and discharge the output capacitors of the MOSFETs. In
addition, the control system effectively optimizes the amount of
reactive current required to achieve ZVS for the power MOS-
FETs. The frequency loop, which is introduced in the control
system, determines the frequency of the modulator based on the
load condition and the duty cycle of the converter. The exper-
imental results and efciency curves show the superior perfor-
mance of the proposed converter compared to the conventional
one.
ACKNOWLEDGMENT
The authors would like to thank Freescale Semiconductor,
Inc., for their technical and nancial support for this research.
REFERENCES
[1] S. M. Lukic, J. Cao, R. C. Bansal, F. Rodriguez, and A. Emadi, Energy
storage systems for automotive applications, IEEE Trans. Ind. Electron.,
vol. 55, no. 6, pp. 22582267, Jun. 2008.
[2] Y.-J. Lee, A. Khaligh, and A. Emadi, Advanced integrated bidirectional
AC/DC and DC/DC converter for plug-in hybrid electric vehicles, IEEE
Trans. Veh. Technol., vol. 58, no. 8, pp. 39703980, Oct. 2009.
[3] A. Emadi, Y. J. Lee, and K. Rajashekara, Power electronics and motor
drives in electric, hybrid electric, and plug-in hybrid electric vehicles,
IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 22372245, Jun. 2008.
[4] T. Nussbaumer, K. Raggl, and J. W. Kolar, Design Guidelines for in-
terleaved single-phase boost PFC circuits, IEEE Trans. Ind. Electron.,
vol. 56, no. 7, pp. 25592573, Jul. 2009.
[5] T. Nussbaumer, M. Baumann, and J. W. Kolar, Comparative evaluation
of modulation methods of a three-phase buck + boost PWM rectier.
Part II: Experimental verication, Power Electron., IET, vol. 1, no. 2,
pp. 268274, Jun. 2008.
[6] T. Nussbaumer and J. W. Kolar, Comparison of 3-phase wide output
voltage range PWM rectiers, IEEE Trans. Ind. Electron., vol. 54, no. 6,
pp. 34223425, Dec. 2007.
[7] R. Giral, L. Martinez-Salamero, and S. Singer, Interleaved converters
operation based on CMC, IEEE Trans. Power Electron., vol. 14, no. 4,
pp. 643652, Jul. 1999.
[8] H. Kosai, S. McNeal, B. Jordan, J. Scoeld, B. Ray, and Z. Turgut,
Coupled inductor characterization for a high performance interleaved
boost converter, IEEE Trans. Magn., vol. 45, no. 10, pp. 48124815,
Oct. 2009.
[9] C. A. Gallo, F. L. Tofoli, and J. A. C. Pinto, A passive lossless snubber
applied to the ACDC interleaved boost converter, IEEE Trans. Power
Electron., vol. 25, no. 3, pp. 775785, Mar. 2010.
[10] Y. Jang and M. M. Jovanovic, Interleaved boost converter with intrinsic
voltage-doubler characteristic for universal-line PFC front end, IEEE
Trans. Power Electron., vol. 22, no. 4, pp. 13941401, Jul. 2007.
[11] F. Musavi, W. Eberle, and W. G. Dunford, A high-performance single-
phase bridgeless interleaved PFC converter for plug-in hybrid electric
vehicle battery chargers, IEEETrans. Ind. Appl., vol. 47, no. 4, pp. 1833
1843, Jul./Aug. 2011.
[12] C. A. Gallo, F. L. Tofoli, and J. A. C. Pinto, Two-stage isolated switch-
mode power supply with high efciency and high input power factor,
IEEE Trans. Ind. Electron., vol. 57, no. 11, pp. 37543766, Nov. 2010.
[13] M. OLoughlin, UCC28070 300-Winterleaved PFCpre-regulator design
review, TI Appl. Rep. SLUA479B, Aug. 2008, revised Jul. 2010.
[14] C.-P. Ku, D. Chen, C.-S. Huang, and C.-Y. Liu, A novel SFVM-M
3
control scheme for interleaved CCM/DCM boundary-mode boost con-
verter in PFC applications, IEEE Trans. Power Electron., vol. 26, no. 8,
pp. 22952303, Aug. 2011.
[15] R. Streit and D. Tollik, A high efciency telecom rectier using a novel
soft-switching boost-based input current shaper, in Proc. Conf. Rec. IEEE
INTELEC, 1991, pp. 720726.
[16] K. M. Smith and K. M. Smedley, A comparison of voltage-mode soft-
switching methods for PWM converters, IEEE Trans. Power Electron.,
vol. 12, no. 2, pp. 376386, Mar. 1997.
[17] C.-J. Tseng and C.-L. Chen, Novel ZVT-PWM converter with active
snubbers, IEEE Trans. Power Electron., vol. 13, no. 5, pp. 861869,
Sep. 1998.
[18] G. Moschopoulos, P. Jain, G. Joos, and Y.-F Liu, Zero voltage switched
PWMboost converter with an energy feedforward auxiliary circuit, IEEE
Trans. Power Electron., vol. 14, no. 4, pp. 653662, Jul. 1999.
[19] T.-W. Kim, H.-S. Kim, and H.-W. Ahn, An improved ZVT PWM boost
converter, in Proc. Conf. Rec. IEEE Power Electron. Spec. Conf., 2000,
pp. 615619.
[20] N. Jain, P. Jain, and G. Joos, Azero voltage transition boost converter em-
ploying a soft switching auxiliary circuit with reduced conduction losses,
IEEE Trans. Power Electron., vol. 19, no. 1, pp. 130139, Jan. 2004.
[21] M. L. Martins, H. A. Grundling, H. Pinheiro, J. R. Pinheiro, and H. L. Hey,
A ZVT PWM boost converter using auxiliary resonant source, in Proc.
Conf. Rec. IEEE Appl. Power Electron. Conf., 2002, pp. 11011107.
[22] C.-M. Wang, A novel zero-voltage-switching PWM boost rectier with
high power factor and lowconduction losses, IEEE Trans. Ind. Electron.,
vol. 52, no. 2, pp. 427435, Apr. 2005.
[23] W. Huang and G. Moschopoulos, Anewfamily of zero-voltage transition
PWM converters with dual active auxiliary circuits, IEEE Trans. Power
Electron., vol. 21, no. 2, pp. 370379, Mar. 2006.
[24] Y. T. Chen, S. M. Shiu, and R. H. Liang, Analysis and design of a
zero-voltage-switching and zero-current-switching interleaved boost con-
verter, IEEE Trans. Power Electron., vol. 27, no. 1, pp. 161173, 2011.
[25] G. Yao, A. Chen, and X. He, Soft switching circuit for interleaved boost
converters, IEEE Trans. Power Electron., vol. 22, no. 1, pp. 8086, Jan.
2007.
[26] B.-R. Lin, H.-K. Chiang, C.-Y. Tung, and C.-Y. Cheng, Implementation
of an interleaved ZVS boost-type converter, in Proc. IEEE Int. Symp.
Ind. Electron., Jul. 58, 2009, pp. 819824.
[27] L. Huber, B. T. Irving, and M. M. Jovanovic, Open-loop control methods
for interleaved DCM/CCMboundary boost PFCconverters, IEEE Trans.
Power Electron., vol. 23, no. 4, pp. 16491657, Jul. 2008.
[28] B. Su and Z. Lu, An interleaved totem-pole boost bridgeless rectier with
reduced reverse-recovery problems for power factor correction, IEEE
Trans. Power Electron., vol. 25, no. 6, pp. 14061415, Jun. 2010.
[29] H. Yao-Ching, H. Te-Chin, and Y. Hau-Chen, An interleaved boost con-
verter with zero-voltage transition, IEEETrans. Power Electron., vol. 24,
no. 4, pp. 973978, Apr. 2009.
[30] P. Das, A. Mousavi, G. Moschopoulos, and P. Jain, A study of AC-
DC ZVS-PWM boost converters with silicon carbide diodes, in Proc.
24th Annu. IEEE Appl. Power Electron. Conf. Expo., Feb. 1519, 2009,
pp. 11581164.
[31] K. Raggl, T. Nussbaumer, and J. W. Kolar, Guideline for a simplied
differential-mode EMI lter design, IEEE Trans. Ind. Electron., vol. 57,
no. 3, pp. 10311040, Mar. 2010.
PAHLEVANINEZHAD et al.: ZVS INTERLEAVED BOOST AC/DC CONVERTER USED IN PLUG-IN ELECTRIC VEHICLES 3529
[32] J. Biela, A. Wirthmueller, R. Waespe, M. L. Heldwein, K. Raggl, and
J. W. Kolar, Passive and active hybrid integrated EMI lters, IEEE
Trans. Power Electron., vol. 24, no. 5, pp. 13401349, May 2009.
[33] Texas Instrument, TMS3202833 analog-to-digital converter (ADC)
module, Rep. no. SPRU812A, Sep. 2007, 2012.
[34] Texas Instrument, TMS3202833, 2823 enhanced pulse width mod-
ulator (ePWM) module, Rep. no. SPRUG04A, Oct. 2008, Revised Jul.
2009.
[35] Texas Instrument, TMS3202833, 2823 high resolution pulse width
modulator, Rep. no. SPRUG02, Feb. 2009.
[36] M. Pahlevaninezhad, J. Drobnik, P. Jain, and A. Bakhshai, Aload adaptive
control approach for a zero voltage switching DC/DC converter used for
electric vehicles, IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 920933,
2011.
Majid Pahlevaninezhad (S07M12) received the
B.S and M.S degrees in electrical engineering from
Isfahan University of Technology, Isfahan, Iran, and
the Ph.D. degree from Queens University, Kingston,
ON, Canada.
He is currently a Postdoctoral Research Associate
in the Department of Electrical and Computer Engi-
neering, Queens University. From 2003 to 2007, he
was a Technical Designer with the Information and
Communication Technology Institute, Isfahan Uni-
versity of Technology, where he was involved in the
design and implementation of high-quality resonant converters. He also collab-
orated with Freescale Semiconductor, Inc., where he was the leader of a research
team working on the design and implementation of the power converters for a
pure electric vehicle from2008 to 2012. He is the author of more than 32 journal
and conference proceeding papers and the holder of 4 US patents. His current
research interests include robust and nonlinear control in power electronics,
advanced soft-switching methods in power converters, plug-in pure electric ve-
hicles, and photovoltaic microinverters.
Dr. Pahlevaninezhad is a member of the IEEE Power Electronics Society and
Industrial Electronics Society. He was a recipient of the distinguished graduate
student award from Isfahan University of Technology.
PritamDas (S09M12) was born in Calcutta, India
in 1978. He received the B.Eng. degree in electronics
and communication engineering from the University
of Burdwan, India. He also received the Masters of
Applied Science degree and the Ph.D. degree, both in
electrical engineering from the University of West-
ern Ontario, London, ON, Canada in 2005 and 2010
respectively.
From 2010 to 2011, he was a Postdoctoral Fel-
low at the Queens Centre for Energy and Power
Electronics Research (ePOWER), Queens Univer-
sity Kingston, Ontario, Canada. Presently, he is with Murata Power Solutions,
Markham, Ontario, where is involved in research and development of front-end
AC-DC converters conforming to 80 Plus Platinum efciency standards. His
research interests include high frequency and high efciency ac-dc and dc-dc
power converters, power factor correction, soft switching techniques, design of
high frequency magnetic components for power converter and modeling and
design of non-linear controllers for ac-dc and dc-dc converters. He is involved
in research on modeling and control of high frequency and high efciency res-
onant and PWM converters for various applications including electric vehicles,
photo-voltaic micro-inverters, data centers, etc. He has published over 33 tech-
nical papers in referred journals and conferences.
Dr. Das is also a reviewer of IEEE TRANSACTIONS ON POWER ELECTRONICS,
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, and IEEE TRANSACTIONS
ON INDUSTRIAL INFORMATICS.
Josef Drobnik (SM93) received his B.Sc., M.Sc.,
and Ph.D. degrees all in electrical engineering from
the Czech Technical University in Prague in 1975,
1977, and 1981, respectively.
He left Czechoslovakia in 1982 for political rea-
sons; since then, he has been working in the eld of
power electronics with steadily increasing responsi-
bilities. From 1982 to 1995, he was in Canada with
Canadian Voice Data Switching, Bell-Northern Re-
search, and Nortel. In 1995, he relocated to the U.S.
to work for GE Corporate R&D, then Intel, and L3
Communications. He is currently with Freescale Semiconductors, Inc., Tempe,
AZ. His positions include Chief Engineer, Technical Advisor, and Director. He
published 46 technical papers and is responsible for 33 U.S. and international
patents. His professional interest includes new power conversion topologies and
integrated magnetic and after silicon semiconductors
Praveen K. Jain (S86M88SM91F02) re-
ceived the B.E. degree (Hons.) from the University
of Allahabad, Allahabad, India, in 1980, and the
M.A.Sc. and Ph.D. degrees from the University of
Toronto, Toronto, ON, Canada, in 1984 and 1987,
respectively, all in electrical engineering.
He is currently a Professor and Canada Research
Chair at the Department of Electrical and Com-
puter Engineering, Queens University, Kingston,
ON, Canada, where he is also the Director of the
Queens Centre for Energy and Power Electronics
Research (ePOWER). Prior to joining Queens University, he was a Professor at
Concordia University (19942000), Technical Advisor at Nortel (19901994),
Senior Space Power Electronics Engineer at Canadian Astronautics Ltd. (1987
1990), Design Engineer at ABB (1981), and Production Engineer at Crompton
Greaves (1980). In addition, he has been a Consultant with Astec, Ballard Power,
Freescale Semiconductor, Inc., General Electric, Intel, and Nortel. He is also
a Founder of CHiL Semiconductor in Tewksbury, MA, and SPARQ System,
Kingston. He has secured over $20M cash and $20M in-kind in external re-
search funding to conduct research in the eld of power electronics. He has
supervised more than 75 graduate students, postdoctoral fellows, and research
engineers. He is the author or coauthor of more than 350 technical papers (in-
cluding more than 90 IEEE Transactions papers) and holds more than 50 patents
(granted and pending).
Dr. Jain is an Associate Editor of the IEEE TRANSACTIONS ON POWER ELEC-
TRONICS and an Editor of the International Journal of Power Electronics. He
is also a Distinguished Lecturer of IEEE Industry Applications Society. He is
a Fellow of the Engineering Institute of Canada and the Canadian Academy
of Engineering. He received of the 2004 Engineering Medal (R&D) from the
Professional Engineers of Ontario. He also received the 2011 IEEE William
Newell Power Electronics Field Award.
Alireza Bakhshai (M04SM99) received the B.Sc.
and M.Sc. degrees from the Isfahan University of
Technology, Isfahann, Iran, in 1984 and 1986, respec-
tively, and the Ph.D. degree from Concordiia Univer-
sity, Montreal, QC, Canada, in 1977.
From 1986 to 1993 and from 1998 to 2004, he
was with the faculty of the Department of Electri-
cal and Computer Engineering, Isfahan University of
Technology. From 1997 to 1998, he was a Postdoc-
toral Fellow at Concordia University. He is currently
with the Department of Electrical and Computer En-
gineering, Queens University, Kingston, ON, Canada. His research interests
include high-power electronics and applications in distributed generation and
wind energy, control systems, and exible ac transmission services.