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Implementing Double Data Rate I/O Signaling in Cyclone Devices

DDR Implementation

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54 views

Implementing Double Data Rate I/O Signaling in Cyclone Devices

DDR Implementation

Uploaded by

blues_mai8288
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Altera Corporation 101

May 2008 Preliminary


10. Implementing Double
Data Rate I/O Signaling in
Cyclone Devices
Introduction
Double data rate (DDR) transmission is used in many applications where
fast data transmission is needed, such as memory access and first-in
first-out (FIFO) memory structures. DDR uses both edges of a clock to
transmit data, which facilitates data transmission at twice the rate of a
single data rate (SDR) architecture using the same clock speed. This
method also reduces the number of I/O pins required to transmit data.
This chapter shows implementations of a double data rate I/O interface
using Cyclone

devices. Cyclone devices support DDR input, DDR


output, and bidirectional DDR signaling.
For more information on using Cyclone devices in applications with DDR
SDRAM and FCRAM memory devices, refer to DDR Memory Support
on page 104.
Double Data
Rate Input
The DDR input implementation shown in Figure 101 uses four internal
logic element (LE) registers located in the logic array block (LAB) adjacent
to the DDR input pin. The DDR data is fed to the first two of four
registers. One register captures the DDR data present during the rising
edge of the clock. The second register captures the DDR data present
during the falling edge of the clock.
Figure 101. Double Data Rate Input Implementation
n_edge_reg
PRN
D Q
PRN
D Q
PRN
D Q
PRN
D Q
p_edge_reg
ddr_l_sync_reg
ddr_h_sync_reg
ddr
clk
ddr_out_l
ddr_out_h
NOT
DFF
DFF
DFF
DFF
C51010-1.2
102 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
The third and fourth registers synchronize the two data streams to the
rising edge of the clock. Figure 102 shows examples of functional
waveforms from a double data rate input implementation.
Figure 102. Double Data Rate Input Functional Waveforms
Double Data
Rate Output
Figure 103 shows a schematic representation of double data rate output
implemented in a Cyclone device. The DDR output logic is implemented
using LEs in the LAB adjacent to the output pin. Two registers are used to
synchronize two serial data streams. The registered outputs are then
multiplexed by the common clock to drive the DDR output pin at two
times the data rate.
Figure 103. Double Data Rate Output Implementation
While the clock signal is logic-high, the output from reg_h is driven onto
the DDR output pin. While the clock signal is logic-low, the output from
reg_l is driven onto the DDR output pin. The DDR output pin can be
any available user I/O pin.
Figure 104 shows examples of functional waveforms from a double data
rate output implementation.
clk
ddr
ddr_out_h
ddr_out_l
data_in_h
clk
ddr
PRN
D Q
PRN
D Q
data_in_l
data1
data0
sel
result
reg_l
reg_h
DFF
DFF
Altera Corporation 103
May 2008 Preliminary
Bidirectional Double Data Rate
Figure 104. Double Data Rate Output Waveforms
Bidirectional
Double Data
Rate
Figure 105 shows a bidirectional DDR interface, constructed using the
DDR input and DDR output examples described in the previous two
sections. As with the DDR input and DDR output examples, the
bidirectional DDR pin can be any available user I/O pin, and the registers
used to implement DDR bidirectional logic are LEs in the LAB adjacent to
that pin. The tri-state buffer (TRI) controls when the device drives data
onto the bidirectional DDR pin.
Figure 105. Bidirectional Double Data Rate Implementation
clk
ddr
data_in_l
data_in_h
clk
PRN
D Q
PRN
D Q
data1
data0
sel
result
PRN
D Q
PRN
D Q
PRN
D Q
PRN
D Q
ddr_out_h
ddr_out_l
ddr_in_l
ddr_in_h
ddr
ddr_wen
NOT
DFF DFF
DFF DFF
DFF
DFF
TRI
104 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Figure 106 shows example waveforms from a bidirectional double data
rate implementation.
Figure 106. Double Data Rate Bidirectional Waveforms
DDR Memory
Support
The Cyclone device family supports both DDR SDRAM and FCRAM
memory interfaces up to 133 MHz.
f For more information about extended DDR memory support in Cyclone
devices, refer to the Cyclone FPGA Family Data Sheet section of the Cyclone
Device Handbook.
Conclusion
Utilizing both the rising and falling edges of a clock signal, double data
rate transmission is a popular strategy for increasing the speed of data
transmission while reducing the required number of I/O pins. Cyclone
devices can be used to implement this strategy for use in applications
such as FIFO structures, SDRAM/FCRAM interfaces, as well as other
time-sensitive memory access and data-transmission situations.
Referenced
Documents
This chapter references the following document:
Cyclone FPGA Family Data Sheet section of the Cyclone Device
Handbook
data_out_h
data_out_l
ddr~result
clk
data_in_h
data_in_l
ddr_wen
ddr
Altera Corporation 105
May 2008 Preliminary
Document Revision History
Document
Revision History
Table 101 shows the revision history for this chapter.
Table 101. Document Revision History
Date and
Document
Version
Changes Made Summary of Changes
May 2008
v1.2
Minor textual and style changes. Added Referenced
Documents section.

January 2007
v1.1
Added document revision history.
May 2003 v1.0 Added document to Cyclone Device Handbook.
106 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1

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