Lecture 10

Design Automation
ENGR 3430 Digital VLSI
Mark L. Chang
Spring 07
181
A Textbook on Design Automation
Sherwani, N. A.
Algorithms for VLSI Physical Design Automation
Many of the figures here come from the book, and:
Scott Hauck, University of Washington
Kia Bazargan, University of Minnesota
182
Full Custom
We get exactly what we want.
183
Standard Cell
Predefined gates with
standard form factor
184
Gate Arrays
185
Programmable Array of Logic
186
Field-Programmable Gate Arrays
187
Physical Design
CAD = Computer Aided Design
Todays circuits are too
complex to do all full custom
CAD is split into two parts:
Synthesis
translating high-level design
into a circuit
Physical Design
translating the circuit into a
layout
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
188
History of CAD
189
Partitioning
Circuits can exceed a chips capacity
Or, want to reclaim some hierarchy in
the design
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
190
Floorplanning
Assign portions of the circuit
to physical regions on the chip
Want to reduce routing delay
and area of design
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
191
Placement
Pick physical location of each gate
Optimize for delay and area
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
192
Global Routing
Determine loose route for each net
Assign a routing region to each net
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
193
Detailed Routing
Find actual geometric layout of each
net within the assigned routing region
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
194
Compaction
Give it that last squeeze
Squish out any free space due
to non-optimality in all
previous algorithms
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
195
Why Partition?
Decomposition of a complex system into smaller
subsystems
Done hierarchically
Partitioning done until each subsystem has manageable size
Each subsystem can be designed independently
Interconnections between partitions minimized
Less hassle interfacing the subsystems
Communication between subsystems usually costly
Partitioning may be necessary at all levels of design
System, Board, Chip, Circuit
196
Partitioning Algorithms
197
Kernighan-Lin
Group Migration
or bisectioning
algorithm
Input graph is partitioned
into two equal parts
Until the cutsize stops improving
Swap pairs of vertices that improve cutsize
Lock them down
If no improvement possible, exchange pairs that increase
cutsize the least
198
Floorplanning
Why?
Early stage of physical design
Determines the location of large blocks
detailed placement easier (divide and conquer!)
Estimates of area, delay, power
important design decisions
Impact on subsequent design steps (e.g., routing, heat
dissipation analysis and optimization)
How?
Many different algorithms
199
Floorplan Classes
Slicing (recursively defined)
A floorplan that can be partitioned
into two slicing floorplans with a
horizontal or vertical cut line
Non-Slicing
Superset of slicing floorplans
Contains the wheel shape too
1234567
167 2345
234 5 1 67
4 3
6 2 7 34
1
3
4
5
2
6 7
Slicing
floorplan
Corresp.
Slicing
tree
Non-Slicing
floorplan
200
Example
Hierarchical floorplan of order 5
Templates
Floorplan and tree
L5 R5
3
8
5
7
3
4
6
8 7
1
2
5
R5
1 6 2
4
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Generic Hierarchical Algorithm
Form a tree with defined fanout restriction
For each node (bottom up) select best grouping
Minimize area, reduce routing delay (estimated)
Cluster nodes based on connectivity
Or, top-down, recursively partition logic
Limit number of nodes in a partition
Form partitions on min-cut lines
Floor planning not always used for standard cell
Fixed cell sizes mean floor planning is just placement
But still used to break up the problem
202
Placement
Why?
Placement is the heart of physical design
Determines routing to the first order
Bad placement means bad everything else
What?
Pick relative location of each gate
Reduce area and wiring delay
How?
Standard-sized cells placed in rows
Estimate routing needs
203
Placement Goals
204
Placement Algorithms
Top Down
Partitioning-based placement
Recursive bi-partioning or quadrisection
Iterative improvement
Simulated annealing
Force-directed
Constructive
Start with a few cells in the center
Place highly connected cells around them
205
Force-Directed
Model
Wires as springs
Solve set of linear equations to find initial placement
Seek to minimize forces on each node
Increase spring constant for critical nodes
Must avoid overlapping cells, or collapsing to a point
Use repelling force between unconnected cells
Do not allow moves that result in an overlap
Use repelling forces from areas of congestion
206
Force-Directed
Model (details):
Cell distances: either
OR:
Forces:
Objective: find x,y coordinates for all cells such that total
force exerted on each cell is zero.
| | | |
j i ij j i ij
y y y x x x ! = " ! = "
2 2
) ( ) (
j i j i ij
y y x x d ! + ! = "
) ( ) (
1 1
ij
n
j
ij
i
y ij
n
j
ij
i
x
y k F x k F " # ! = " # ! =
$ $
= =
207
Annealing
Cooling hot metals to form good crystalline structures
Start at high temperatures atoms move about randomly
Cool metal, leaving enough time for atoms to attract into
crystal lattice
208
Simulated Annealing
Move nodes (gate position assignments) randomly
Initial high temperature allow bad moves to happen
Lower temperature accept fewer bad moves
Slowly cool placement to allow good structure to form
209
Placement Cost Function
Most use Manhattan routing (NSEW, no diagonals)
A
A
A
B
B
C
C
C
Wirelength estimate = 0.5 * (perimeter of bounding box)
210
Placement Cost Function
Most use Manhattan routing (NSEW, no diagonals)
A
A
A
B
B
C
C
C
Wirelength estimate = 0.5 * (perimeter of bounding box)
211
Placement Cost Function
Most use Manhattan routing (NSEW, no diagonals)
A
A
A
B
B
C
C
C
Wirelength estimate = 0.5 * (perimeter of bounding box)
212
Placement Cost Function
Most use Manhattan routing (NSEW, no diagonals)
A
A
A
B
B
C
C
C
Wirelength estimate = 0.5 * (perimeter of bounding box)
213
Placement Cost Function
Most use Manhattan routing (NSEW, no diagonals)
A
A
A
B
B
C
C
C
Wirelength estimate = 0.5 * (perimeter of bounding box)
5
7
8
11
14
10
214
Placement Cost Function
Most use Manhattan routing (NSEW, no diagonals)
A
A
A
B
B
C
C
C
Wirelength estimate = 0.5 * (perimeter of bounding box)
5
7
8
11
14
10
19
12
24
215
SA Cost Function
Simulated Annealing requires a cost function that
captures quality of placement
Smaller cost means better placement
Multiple concerns captured in one metric
Simple example
Might add
Row imbalance penalty
Overlap penalty
Row length
Area estimation
( ) delay path critical c i perimeter semi c placement cost
nets i
_ _ * ) ( ) (
2 1
+ ! " =
#
216
Acceptance Criteria
After we obtain a new placement:
delta = cost(oldPlacement) cost(newPlacement)
if( delta >= 0 )
accept
else if ( random < e
delta/temperature
) // 0 <= random <= 1
accept
else
reject
217
Acceptance Criteria
random < e
delta/temperature
Higher temperatures lots of bad moves accepted
Lower temperatures fewer bad moves tolerated
218
Cooling Schedule
Initial temperature is very high
Most bad moves accepted
Temperature slowly goes to 0, attempting many moves
at each temperature
Run several iterations at temperature=0
Only accept good moves
Greedily quench the system
219
Simulated Annealing Algorithm
220
Practical Issues for SA
Cost function
Cost function must be carefully developed (fractal & smooth)
Cost function evaluation must be fast
Balancing quality and runtime requires lots of testing
Move function
Efficient random node selection
Maybe use area windowing
Cooling schedule
Moves per temp, starting temp, cooling rate, freezing point?
Takes lots of testing
221
Global Routing
Determine loose route for each net
Assign a routing region to each net
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
222
Global Routing
Objectives
Minimize total channel
height
Assign feedthroughs
Minimize maximum wire
length
Minimize maximum path length
223
Problem Formulation
Utilize a grid abstraction so we can apply graph theory
Coarse vs. fine grained
Vertices: routing regions. Edges: existence of route
Optional weighting of edges
t1 t2 t3
t4
t1 t2 t3
t4
1 1 1
1 1 1
2 2 1 1
t1
t3
t4
t2
224
Global Routing Algorithms
Sequential: one net at a time
Concurrent: all nets considered simultaneously
225
Maze Routing
226
Maze Routing
Pros
Simple
Easy to implement
Guaranteed to find an optimal solution
Can incorporate complex cost functions (along edges)
Cons
Not great for multiple-terminal nets
Large memory requirements if not programmed carefully
227
Bidirectional Maze Routing
228
A* (A-Star) Maze Routing
229
Multi-Terminal Maze Routing
230
Minimum Spanning Tree
231
Minimum Steiner Tree