Engineer To Engineer Note EE-192

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Technical Notes on using Analog Devices' DSP components and development tools
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Using C To Create Interrupt-Driven Systems On Blackfin Processors
Contributed by Joe B. May 28, 2003
Introduction
This Engineer-to-Engineer note will describe the
process for implementing an interrupt-driven
general-purpose timer routine for the Blackfin
Processor family using the C programming
language.
The referenced code in this application note was
verified using VisualDSP++ 3.1 for Blackfin
and the project was run on the EZ-KIT Lite
evaluation systems for both the ADSP-BF535
and the ADSP-BF533 Blackfin Processors
(ADDS-BF535-EZLITE, Rev 1.0 and ADDS-
BF533-EZLITE, Rev 1.0).
Timer Programming Model
When coding in a pure assembly environment,
configuration of the timers and use of interrupts
is fairly straightforward, as described in the
Hardware Reference Manuals. However, when
programming in C, using interrupts and
accessing the timer registers requires knowledge
of some of the system header files and an
understanding of the C run-time environment as
it relates to embedded system programming. The
process explained herein describes how to
implement an interrupt-driven timer routine in C,
but the methods employed can be applied to any
C-coded interrupt routines for the Blackfin
processors.
Two test platforms are necessary for this paper
because the demonstration utilizes the on-board
LEDs on the Blackfin evaluation platforms. On
the ADDS-BF535-EZKIT, the four LEDs are
mapped directly to the general purpose flag pins,
whereas, on the ADDS-BF533-EZKIT, the six
LEDs are accessible only through the on-board
flash port, which requires an alternate set of
instructions in the Interrupt Service Routine
(ISR) in order to update the LED display. The
differences in the software will be discussed
later.
Using Features In VisualDSP++
VisualDSP++ 3.1 comes with a set of header
files that makes programming the Blackfin
processors in a C environment simpler. These
headers can be found under the Blackfin include
directory and are named using the cdef prefix
to denote C definitions.
Memory-mapped registers are accessed in C via
a referencing-dereferencing scheme using casted
pointers, like this:
vol at i l e l ong *pI MASK = ( l ong *) I MASK;
IMASK is defined for the ADSP-BF535 in
defblackfin.h and for the ADSP-BF533 in
def_LPblackfin.h to be the address of the
IMASK register in Blackfin address space
(0xFFE02104). If the user wanted to set bit 0 of
the IMASK register in C, a proper 32-bit read-
modify-write would be performed indirectly
through the pointer defined above:
*pI MASK | = 0x1;
Using this convention, the label pIMASK is a
data element of type l ong i nt *, which

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consumes 4 bytes of memory and whose sole
purpose is to hold the address of IMASK so that
the user can indirectly write a 1 to the register by
accessing it through its mapped address. This
convention wastes 4 bytes of memory for every
register accessed in this fashion!
An alternate method of manipulating the IMASK
register without consuming memory for the
pointer is to force a casted pointer in the code to
modify the address directly:
*( vol at i l e l ong *) I MASK | = 0x1;
In the Blackfin C-defines header files, all of the
memory-mapped registers have already been set
up for access in C in a series of #def i ne
statements, like this:
#def i ne pI MASK ( ( vol at i l e l ong *) I MASK)
This method allows the user to use the same C
syntax in their code, *pI MASK | = 0x1, to modify
the registers contents without dedicating
memory for the pointer. Instead, the compilers
pre-processor substitutes the casted pointer
syntax for what appears to be pointer-modifying
code. So, if one knows the name of the register,
one can easily access that register using standard
C code for pointer modification:
*pREGISTER_NAME = VALUE;
These cdef header files were created for each
individual processor based upon the widths of
the registers being represented (i.e., a 16-bit
register uses the shor t i nt type, which the
Blackfin compiler treats as 16-bit data, whereas a
32-bit register is represented as a l ong i nt or i nt
type).
Blackfin Interrupts (Hardware)
The Blackfin family of processors has an
intricate interrupt system that includes core
interrupts, enabled in the IMASK register, and
peripheral interrupts, which are configured in the
System Interrupt Controller (SIC). These
system-level peripheral interrupts are optionally
user-configurable in a set of System Interrupt
Assignment Registers: SIC_IAR0, SIC_IAR1,
and SIC_IAR2. Refer to Chapter 4 (Program
Sequencer) of the appropriate Hardware
Reference Manual (either ADSP-BF535 or
ADSP-BF533) for more information regarding
interrupt priority assignments.
Several peripheral sources can share the same
SIC interrupt assignment. Those sources with
common interrupt assignments share the same
General-purpose interrupt (IVGx). Table 4-8 of
the Hardware Reference Manual depicts the
IVG-Select Definitions, which is where the
values programmed into the specific fields of the
SIC_IARx registers are translated into an IVG
priority. Use the IVG priority detailed here to
determine which IMASK bit to set in the Core
Event Controller (CEC) to enable interrupt
handling for this group of peripherals.
In addition to having a group of interrupt sources
enabled in the CEC, handling for each sources
individual interrupt is enabled separately on the
SIC level in the SIC_IMASK register. For
example, one could set each peripherals IVG
priority to the same level, thus making one group
of 24 potential interrupt sources. If only one of
those peripheral interrupts is enabled in
SIC_IMASK, then the IVG effectively describes
that single interrupt source because that single
source is the only source enabled at the SIC level
to be recognized by the core as a peripheral
interrupt source.
An abridged overview of how to set peripheral
interrupts up correctly goes like this:
1. Enable peripherals individual interrupt in
SIC_IMASK register.
2. Program the interrupt priority levels into the
SIC_IARx registers. This step is optional.
3. Use the values in the SIC_IARx registers
with Table 4-8 of the Hardware Reference
Manual to determine which interrupt group
(IVGx) the peripheral of interest is assigned
to.
4. Set the appropriate IVGx bit in the IMASK
register.

Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 2 of 9

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This example uses the interrupt of the General
Purpose Timer 0 to generate LED activity on the
evaluation boards. Following the process
detailed above, the first step is to configure the
SIC_IMASK register. The Timer0 interrupt is
enabled in SIC_IMASK by setting either bit 14
(ADSP-BF535) or bit 16 (ADSP-BF533):
*pSI C_I MASK = 0x00004000; / / ADSP- BF535
*pSI C_I MASK = 0x00010000; / / ADSP- BF533

For 0.x revisions of the ADSP-BF535,

the active low setting is used to enable
interrupts in SIC_IMASK:
*pSI C_I MASK = ~0x00004000;
This anomaly was fixed in revision 1.0 of
the ADSP-BF535 and doesnt apply to
any other ADSP-BF53x processor.

Once the interrupt is enabled in the SIC, the next
step is to optionally program the interrupt
priority and assign the peripheral interrupt to an
IVG. This example doesnt reconfigure the
interrupt priorities but uses the default values in
the SIC_IARx registers.
According to the reset values of the SIC_IARx
registers, the default value in the Timer0 field of
SIC_IAR1 is 0x4. Table 4-8 of the Hardware
Reference Manual tells us that the value 0x4
maps to IVG11, therefore, IVG11 is the default
core interrupt channel for the Timer0 interrupt.
So, the last step in setting up peripheral
interrupts in the hardware is to enable IVG11 in
the CECs IMASK register.

If this were a Core Timer application, the

steps required to initialize the SIC would
not be needed because the Core Timer
interrupt is a Core Event only.
Once the interrupts are properly configured, the
final step is to have the software in place for
proper interrupt servicing.
Software And Code Flow
The Blackfin processors feature 16 Event Vector
Table (EVT0-15) registers, which hold the vector
addresses of the individual core interrupt
channels. The program will jump to these
addresses whenever an event is latched by ILAT
and enabled in IMASK in the CEC.
In the assembly examples shipped with
VisualDSP++ 3.1, the startup.asm driver sets
up a default vector table using the following
assembler commands:
p0. l = l o( EVT2) ; p0. h = hi ( EVT2) ;
r 0. l = _NHANDLER; r 0. h = _NHANDLER;
[ p0++] = r 0; / / NMI Handl er ( I nt 2)
This code sets up a pointer register (P0) to write
to the EVT2 register and then writes the address
of the _NHANDLER label to EVT2. The result is
that any external Non-Maskable Interrupt (NMI)
detected by the CEC will force an immediate
vector to the address of _NHANDLER, which is the
label associated with the NMIs ISR.
In C, however, the startup.asm is substituted
with the C run-time library. The library function
r egi st er _handl er ( I VGx, I SR_Name)
assigns the name of the ISR function, I SR_Name,
to the core event represented by I VGx by writing
the ISR functions address to the corresponding
EVTx register. The function prototype and
enumeration of interrupt kinds can be found in
the sys\exception.h header file.
Checking the sys\exception.h header file, it can
be seen that the signal number for IVG11 is
i k_i vg11. Therefore, use of this macro in this
example is:
r egi st er _handl er ( i k_i vg11, Ti mer 0_I SR) ;
In addition to setting the EVT11 register to
contain the address of the Ti mer 0_I SR label, this
macro also sets the IVG11 bit in the IMASK
register and globally enables interrupts.
In addition to registering the interrupt handler,
the interrupt routine itself must also be set-up,

Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 3 of 9

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which is accomplished using a second library
function:
EX_I NTERRUPT_HANDLER ( I SR_Name)
The EX_I NTERRUPT_HANDLER macro can be used in
two ways. It must be used as the function
signature for all ISRs. It generates the label
I SR_Name to be used by the r egi st er _handl er
function later in the source code. It also tells the
compiler that the module is an ISR, which means
that processor context must be saved and
restored upon entry and exit, respectively, and
that the final instruction in the assembly
produced by the compiler must be a return from
interrupt (RTI ; ). Basically, the
EX_I NTERRUPT_HANDLER macro hides special
compiler pragma directives from the user.
The EX_I NTERRUPT_HANDLER macro can also be
globally used as a function prototype if the
r egi st er _handl er ( I VGx, I SR_Name) function is
called before the I SR_Name label is defined.

A compiler error will be generated if the

r egi st er _handl er function attempts to
use the I SR_Name label as an argument
before the EX_I NTERRUPT_HANDLER macro
defines the I SR_Name label. If you get
undefined label compiler errors, try
using the EX_I NTERRUPT_HANDLER macro to
prototype the ISR globally.

Once the ISR is registered and all the hardware
considerations have been accounted for, the last
thing needed is an appropriate ISR. For
peripheral interrupts, the ISR code must clear the
IRQ in the peripherals hardware. In most cases,
this is done by performing a write-one-to-clear
(W1C) operation to the associated IRQ bit. For
the Timer0 peripheral, a 1 must be written to the
TIMIL0 location of the Timers Status register in
order to clear the IRQ before the ISR completes
and application code begins running again.
In this example, if the core did not explicitly
clear the IRQ in the Timer0 ISR, the same
interrupt would be immediately latched again
upon completion of the ISR. Even though the
ISR executes, the SIC continues to monitor the
status of the timers IRQ, which generated the
event to begin with. If this IRQ remains active,
the SIC will continue to hold the bit in the SIC
Interrupt Status Register (SIC_ISR) active,
which will result in the interrupt staying latched
in the core (ILAT). Once the core executes the
RTI ; instruction in the ISR, the IMASK register
is restored and the ISR would be triggered again
because the CEC sees that an enabled interrupt is
currently latched.

If several sources share the same IVG

priority, it is up to the user to implement
a software solution to poll each enabled
peripherals IRQ in the group to
determine which source generated the
interrupt request.

The Code Example
The code in Listing 1 at the end of this note was
developed for the ADSP-BF535 EZ-KIT. The
code was then modified to perform the same
functions on the ADSP-BF533 EZ-KIT. The two
critical differences between the two evaluation
platforms are:
1. ADSP-BF533 has a TIMER_ENABLE
register and uses 32-bit timer registers
whereas the ADSP-21535 uses pairs of
registers to represent the upper 16 bits and
lower 16 bits separately
2. ADSP-BF533 EZ-KIT Lite LEDs are
accessed via the on-board flash rather than
the PFx flags, as previously mentioned
In Listing 1, there is a commented pre-processor
directive, #def i ne BF533_PROJ ECT, at the top of
the code that must be uncommented to build a
project to run on an ADSP-BF533 EZ-KIT Lite.

Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 4 of 9

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Throughout the source code, there are several
pre-processor directives based upon whether or
not BF533_PROJ ECT is defined. If BF533_PROJ ECT
is defined, the correct ADSP-BF533 code is built
into the project. Otherwise, the code is built
assuming an ADSP-BF535 project.
This application code initializes Timer0 in
Pulsewidth Modulation (PWMOUT) Mode. It
configures the appropriate LEDs to be outputs,
sets up the timer registers, associates the ISR to
the timer signal, and starts the timer.
The ISR code increments a counter and displays
the counter value in binary on the LEDs. Once
all LEDs are lit, the counter resets to 0. The ISR
also clears the Timer0 interrupt request.
Listing 2 is the C source for the ADSP-BF535
EZ-KIT and Listing 3 is the source code for the
ADSP-BF533 EZ-KIT, without the pre-processor
directives.
mixed.c

/ *****************************************************************************
* Uncomment t he f ol l owi ng pr e- pr ocessor di r ect i ve i f bui l di ng code f or t he *
* ADSP- BF533 EZ- KI T. ADSP- BF535- EZKI T user s do not need t o modi f y t hi s. *
* I ncl udi ng BF533_PROJ ECT changes t he l egacy ADSP- BF535 code t o use t he *
* BF533 header , r edef i ne t he MAX val ue on t he LEDs, use t he BF533 t i mer *
* r egi st er s, and conf i gur e t he f l ash t o use t he LEDs t o out put pat t er ns *
*****************************************************************************/

/ / #def i ne BF533_PROJ ECT / / Uncomment f or BF533- EZKI T Code

#i f def BF533_PROJ ECT
#i ncl ude <cdef BF533. h> / / BF533 Regi st er Poi nt er Def i ni t i ons
#el se
#i ncl ude <cdef BF535. h> / / BF535 Regi st er Poi nt er Def i ni t i ons
#endi f

#i ncl ude <sys/ except i on. h> / / I nt er r upt Handl i ng Header

/ / Pr ot ot ypes
#i f def BF533_PROJ ECT
voi d I ni t _EBI U_Fl ash( voi d) ; / / Fl ash I ni t Code Needed For BF533- EZKI T
#el se
voi d I ni t _Fl ags( voi d) ; / / Fl ags Mapped To LEDs For BF535- EZKI T
#endi f

voi d I ni t _Ti mer ( voi d) ;
voi d I ni t _I nt er r upt s( voi d) ;

/ / Sel ect s Al l LEDs, Al so Used For I SR Compar e For Al l LEDs Li t
#i f def BF533_PROJ ECT
#def i ne MAX_LED_DI SPLAY 0x3F / / 6 LEDs on BF533, al l LI T
#el se
#def i ne MAX_LED_DI SPLAY 0xF / / 4 LEDs on BF535, al l LI T
#endi f

#i f def BF533_PROJ ECT / / Fl ash Regi st er Poi nt er s For Updat i ng BF533 LEDs
#def i ne pFl ashA_Por t B_Di r ( vol at i l e unsi gned char *) 0x20270007
#def i ne pFl ashA_Por t B_Dat a ( vol at i l e unsi gned char *) 0x20270005
#endi f


Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 5 of 9

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EX_I NTERRUPT_HANDLER( Ti mer _I SR)
{
st at i c i nt count =- 1;

i f ( ++count > MAX_LED_DI SPLAY) / / check f or al l LEDs l i t
count =0; / / cl ear al l LEDs on wr ap

#i f def BF533_PROJ ECT
*pTI MER_STATUS = 1; / / Cl ear Ti mer 0 I nt er r upt
*pFl ashA_Por t B_Dat a = 0x0; / / cl ear LEDs
*pFl ashA_Por t B_Dat a = count ; / / wr i t e new LED pat t er n t o Por t B
#el se
*pTI MER0_STATUS = 1; / / Cl ear Ti mer 0 I nt er r upt
*pFI O_FLAG_C = 0xF; / / cl ear LEDs
*pFI O_FLAG_S = count ; / / di spl ay new LED pat t er n
#endi f
} / / end Ti mer _I SR

mai n( )
{
#i f def BF533_PROJ ECT / / I f t hi s i s f or t he BF533- EZKI T
I ni t _EBI U_Fl ash( ) ; / / i ni t i al i ze EBI U f or FLASH i nt er f ace
#el se / / Ot her wi se, i t i s f or a BF535- EZKI T
I ni t _Fl ags( ) ; / / Set Al l 4 LED PFx Fl ags To Out put s
#endi f

I ni t _Ti mer ( ) ; / / I ni t i al i ze t he Ti mer 0 Regi st er s
I ni t _I nt er r upt s( ) ; / / Conf i gur e t he I nt er r upt s

whi l e( 1) ; / / wai t f or ever f or i nt er r upt s
} / / end mai n

#i f def BF533_PROJ ECT
voi d I ni t _EBI U_Fl ash( voi d)
{
*pEBI U_AMBCTL0 = 0x7bb07bb0;
*pEBI U_AMBCTL1 = 0x7bb07bb0;
*pEBI U_AMGCTL = 0x000f ;

*pFl ashA_Por t B_Di r = MAX_LED_DI SPLAY; / / 6 LEDs
} / / end I ni t _EBI U_Fl ash
#el se
voi d I ni t _Fl ags( voi d)
{
*pFI O_DI R = 0xF; / / Conf i gur e PF0- 3 As Out put s
} / / end I ni t _Fl ags
#endi f

voi d I ni t _Ti mer ( voi d)
{
*pTI MER0_CONFI G = 0x0019; / / PWM Mode, Per i od Count ,
I nt er r upt

#i f def BF533_PROJ ECT
*pTI MER0_PERI OD = 0x01000000; / / Conf i gur e Ti mer Per i od
*pTI MER0_WI DTH = 0x00800000; / / Conf i gur e Ti mer Wi dt h
*pTI MER_ENABLE = 0x0001; / / Enabl e Ti mer
#el se
*pTI MER0_PERI OD_HI = 0x0100; / / Conf i gur e Ti mer Per i od

Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 6 of 9

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*pTI MER0_PERI OD_LO = 0x0000;
*pTI MER0_WI DTH_HI = 0x0080; / / Conf i gur e Ti mer Wi dt h
*pTI MER0_WI DTH_LO = 0x0000;
*pTI MER0_STATUS = 0x0100; / / Enabl e Ti mer 0
#endi f
} / / end I ni t _Ti mer

voi d I ni t _I nt er r upt s( voi d)
{
/ / Enabl e t he SI C i nt er r upt
#i f def BF533_PROJ ECT
*pSI C_I MASK = 0x00010000; / / Ti mer 0 Def aul t I RQ I s Bi t 16 on BF533
#el se / / i f usi ng Rev 1. 0 or hi gher of BF535 si l i con, del et e t he ~ bel ow
*pSI C_I MASK = ~0x00004000; / / Ti mer 0 Def aul t I RQ I s Bi t 14 on BF535
#endi f
/ / i nst al l t he handl er ( al so set s I VG11 i n I MASK)
r egi st er _handl er ( i k_i vg11, Ti mer _I SR) ;
} / / end I ni t _I nt er r upt s
Listing 1: mixed.c
BF535_C_IRQ.c
#i ncl ude <cdef BF535. h> / / BF535 Regi st er Poi nt er Def i ni t i ons
#i ncl ude <sys/ except i on. h> / / I nt er r upt Handl i ng Header

/ / Pr ot ot ypes
voi d I ni t _Fl ags( voi d) ; / / Fl ags Mapped To LEDs For BF535- EZKI T
voi d I ni t _Ti mer ( voi d) ;
voi d I ni t _I nt er r upt s( voi d) ;

/ / Sel ect s Al l LEDs, Al so Used For I SR Compar e For Al l LEDs Li t
#def i ne MAX_LED_DI SPLAY 0xF / / 4 LEDs on BF535, al l LI T

EX_I NTERRUPT_HANDLER( Ti mer _I SR)
{
st at i c i nt count =- 1;

i f ( ++count > MAX_LED_DI SPLAY) / / check f or al l LEDs l i t
count =0; / / cl ear al l LEDs on wr ap

*pTI MER0_STATUS = 1; / / Cl ear Ti mer 0 I nt er r upt
*pFI O_FLAG_C = 0xF; / / cl ear LEDs
*pFI O_FLAG_S = count ; / / di spl ay new LED pat t er n
} / / end Ti mer _I SR

mai n( )
{
I ni t _Fl ags( ) ; / / Set Al l 4 LED PFx Fl ags To Out put s
I ni t _Ti mer ( ) ; / / I ni t i al i ze t he Ti mer 0 Regi st er s
I ni t _I nt er r upt s( ) ; / / Conf i gur e t he I nt er r upt s

whi l e( 1) ; / / wai t f or ever f or i nt er r upt s
} / / end mai n

voi d I ni t _Fl ags( voi d)
{

Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 7 of 9

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*pFI O_DI R = 0xF; / / Conf i gur e PF0- 3 As Out put s
} / / end I ni t _Fl ags

voi d I ni t _Ti mer ( voi d)
{
*pTI MER0_CONFI G = 0x0019; / / PWM Mode, Per i od Count , I nt er r upt
*pTI MER0_PERI OD_HI = 0x0100; / / Conf i gur e Ti mer Per i od
*pTI MER0_PERI OD_LO = 0x0000;
*pTI MER0_WI DTH_HI = 0x0080; / / Conf i gur e Ti mer Wi dt h
*pTI MER0_WI DTH_LO = 0x0000;
*pTI MER0_STATUS = 0x0100; / / Enabl e Ti mer 0
} / / end I ni t _Ti mer

voi d I ni t _I nt er r upt s( voi d)
{
/ / Enabl e SI C i nt er r upt , i f usi ng Rev 1. 0 or hi gher of ADSP- BF535 si l i con,
/ / del et e t he ~ bel ow
*pSI C_I MASK = ~0x00004000; / / Ti mer 0 Def aul t I RQ I s Bi t 14

/ / i nst al l t he handl er ( al so set s I VG11 i n I MASK)
r egi st er _handl er ( i k_i vg11, Ti mer _I SR) ;
} / / end I ni t _I nt er r upt s
Listing 2: BF535_C_IRQ.c
BF533_C_IRQ.c
#i ncl ude <cdef BF533. h> / / BF533 Regi st er Poi nt er Def i ni t i ons
#i ncl ude <sys/ except i on. h> / / I nt er r upt Handl i ng Header

/ / Pr ot ot ypes
voi d I ni t _EBI U_Fl ash( voi d) ; / / Fl ash I ni t Code Needed For BF533- EZKI T
voi d I ni t _Ti mer ( voi d) ;
voi d I ni t _I nt er r upt s( voi d) ;

/ / Sel ect s Al l LEDs, Al so Used For I SR Compar e For Al l LEDs Li t
#def i ne MAX_LED_DI SPLAY 0x3F / / 6 LEDs on BF533, al l LI T

/ / Map Fl ash Por t B Regi st er s For LED Access
#def i ne pFl ashA_Por t B_Di r ( vol at i l e unsi gned char *) 0x20270007
#def i ne pFl ashA_Por t B_Dat a ( vol at i l e unsi gned char *) 0x20270005

EX_I NTERRUPT_HANDLER( Ti mer _I SR)
{
st at i c i nt count =- 1;

i f ( ++count > MAX_LED_DI SPLAY) / / check f or al l LEDs l i t
count =0; / / cl ear al l LEDs on wr ap

*pTI MER_STATUS = 1; / / Cl ear Ti mer 0 I nt er r upt
*pFl ashA_Por t B_Dat a = 0x0; / / cl ear LEDs
*pFl ashA_Por t B_Dat a = count ; / / wr i t e new LED pat t er n t o Por t B

} / / end Ti mer _I SR

mai n( )
{

Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 8 of 9

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I ni t _EBI U_Fl ash( ) ; / / i ni t i al i ze EBI U f or FLASH i nt er f ace
I ni t _Ti mer ( ) ; / / I ni t i al i ze t he Ti mer 0 Regi st er s
I ni t _I nt er r upt s( ) ; / / Conf i gur e t he I nt er r upt s

whi l e( 1) ; / / wai t f or ever f or i nt er r upt s
} / / end mai n

voi d I ni t _EBI U_Fl ash( voi d)
{
*pEBI U_AMBCTL0 = 0x7bb07bb0;
*pEBI U_AMBCTL1 = 0x7bb07bb0;
*pEBI U_AMGCTL = 0x000f ;

*pFl ashA_Por t B_Di r = MAX_LED_DI SPLAY; / / 6 LEDs
} / / end I ni t _EBI U_Fl ash

voi d I ni t _Ti mer ( voi d)
{
*pTI MER0_CONFI G = 0x0019; / / PWM Mode, Per i od Count , I nt er r upt
*pTI MER0_PERI OD = 0x01000000; / / Conf i gur e Ti mer Per i od
*pTI MER0_WI DTH = 0x00800000; / / Conf i gur e Ti mer Wi dt h
*pTI MER_ENABLE = 0x0001; / / Enabl e Ti mer
} / / end I ni t _Ti mer

voi d I ni t _I nt er r upt s( voi d)
{
/ / Enabl e t he SI C i nt er r upt
*pSI C_I MASK = 0x00010000; / / Ti mer 0 Def aul t I RQ I s Bi t 16

/ / i nst al l t he handl er ( al so set s I VG11 i n I MASK)
r egi st er _handl er ( i k_i vg11, Ti mer _I SR) ;
} / / end I ni t _I nt er r upt s
Listing 3: BF533_C_IRQ.c
References
[1] ADSP-BF535 Blackfin Hardware Reference. Revision 1.0, November 2002. Analog Devices, Inc.
[2] ADSP-BF533 Blackfin Hardware Reference. Preliminary Revision, March 2003. Analog Devices, Inc.
[3] VisualDSP++ 3.0 C/C++ Compiler and Library Manual for Blackfin Processors. Second Revision,
April 2002. Analog Devices, Inc.
Document History
Version Description
May 28, 2003 by Joe B. Updated interrupt service routine example code.
April 30, 2003 by Joe B. Initial Release


Using C To Create Interrupt-Driven Systems On Blackfin Processors (EE-192) Page 9 of 9