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Introduction To Digital Electronics

This document discusses the structure and operation of MOSFET transistors. It describes the physical structure of NMOS transistors, including the gate, source, drain, and oxide layer. It explains that applying a positive voltage to the gate induces a conducting channel between the source and drain. The document also outlines the different regions of operation for NMOS transistors, including the triode and saturation regions, and presents the corresponding i-v characteristics. PMOS transistors are also introduced.

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LeandroRicardo
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80 views

Introduction To Digital Electronics

This document discusses the structure and operation of MOSFET transistors. It describes the physical structure of NMOS transistors, including the gate, source, drain, and oxide layer. It explains that applying a positive voltage to the gate induces a conducting channel between the source and drain. The document also outlines the different regions of operation for NMOS transistors, including the triode and saturation regions, and presents the corresponding i-v characteristics. PMOS transistors are also introduced.

Uploaded by

LeandroRicardo
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EEE 4343

Dr. Fan - eee4343_note1 11


Introduction to Digital Electronics
Department of Electrical and Computer Engineering
Florida International University
Instructor: Dr. Jeffrey Fan
MOS Field-Effect
Dr. Fan - eee4343_note1 22
Transistors (MOSFETs)
Dr. Fan - eee4343_note1 3
Device Structure
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b)
cross-section.
Typically L = 0.1 to 3 m (channel length), less than 0.1 nanometer, n+ heavily
doped n-type silicon
W = 0.2 to 100 m (channel width), used as resistors or capacitors
Thickness of the oxide layer (t
ox
) is in the range of 2 to 50 nm.
Dr. Fan - eee4343_note1 4
NMOS transistor with a positive voltage applied to the gate (G)
p-substrate for NMOS, depletion region is thin
B (Bulk), S (Source) and D (Drain) grounded
n channel is induced at the top of the substrate beneath the gate.
n type MOS called NMOS ( p type MOS is called ? )
Dr. Fan - eee4343_note1 5
NMOS transistor with v
GS
> V
t
and with a small v
DS
applied. (Vt: threshold voltage)
Device acts as a resistance whose value is determined by v
GS
.
Channel conductance is proportional to v
GS
V
t
and thus i
D
is proportional to (v
GS

V
t
) v
DS
. Induced channel is also called inversion layer.
Dr. Fan - eee4343_note1 6
The i
D
v
DS
characteristics of the MOSFET when the voltage applied
between drain and source, v
DS,
is kept small. The device operates as a
linear resistor whose value is controlled by v
GS
.
vGS Vt: excess gate voltage, effective voltage or overdrive voltage
Dr. Fan - eee4343_note1 7
Operation of the enhancement NMOS transistor as v
DS
is increased.
Induced channel acquires a tapered shape, resistance increases as v
DS
increases.
v
GS
is kept constant at a value > V
t
Pinch-off on channel Tunneling effort
Dr. Fan - eee4343_note1 8
Enhancement-type NMOS transistor operated with v
GS
> V
t
. (threshold voltage)
The voltage at saturation VSDsat = VGS Vt
Triode Region: Active region, overdrive region
Dr. Fan - eee4343_note1 9
Dr. Fan - eee4343_note1 10
Cross-section of a CMOS integrated circuit.
PMOS transistor is formed in a separate n-type region, known as n well.
n-type body is used and the n device is formed in a p well.
SiO2 for isolation
Device Structure and Device Physics
Dr. Fan - eee4343_note1 11
(a) Circuit symbol for the n-channel enhancement-type MOSFET.
(b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it
from the drain and to indicate device polarity (i.e., n channel).
(c) Simplified circuit symbol to be used when the source is connected to the body or
when the effect of the body on device operation is unimportant.
S: Source G: Gate D: Drain B: Bulk
Regions of Operation of the Enhancement NMOS Transistor
Dr. Fan - eee4343_note1 12
Dr. Fan - eee4343_note1 13
The relative levels of the terminal voltages of the enhancement NMOS
transistor for operation
- in the triode region (active region)
- in the saturation region.
Dr. Fan - eee4343_note1 14
(a) An n-channel enhancement-type MOSFET with v
GS
and v
DS
applied and with
the normal directions of current flow indicated.
(b) The i
D
v
DS
characteristics for a device with k
n
(W/L) = 1.0 mA/V
2
.
(c) Triode, Saturation, and Cutoff (vGS Vt < 0) regions
Dr. Fan - eee4343_note1 15
i
D
v
GS
characteristic for an enhancement-type NMOS transistor in
saturation (V
t
= 1 V, k
n
W/L = 1.0 mA/V
2
). Vt: threshold voltage
Dr. Fan - eee4343_note1 16
Large-signal equivalent-circuit model of an n-channel MOSFET
operating in the saturation region.
Acting like a current source (because of saturation)
Dr. Fan - eee4343_note1 17
Large-signal equivalent circuit model of the n-channel MOSFET (NMOS) in
saturation
Incorporating the output resistance r
o
. (acting as a load)
The output resistance models the linear dependence of i
D
on v
DS
Dr. Fan - eee4343_note1 18
Effect of v
DS
on i
D
in the saturation region.
MOSFET parameter V
A
depends on the process technology and, for a given
process (lamda), is proportional to the channel length L.
lamda related to channel length modulation (ideal value = 0)
PMOS Device
Dr. Fan - eee4343_note1 19
(a) Circuit symbol for the p-channel enhancement-type MOSFET. (PMOS)
(b) Modified symbol with an arrowhead on the source lead.
(c) Simplified circuit symbol - source is connected to the body.
(d) The MOSFET with voltages applied and the directions of current flow indicated.
Regions of Operation of the Enhancement PMOS Transistor
Dr. Fan - eee4343_note1 20
Dr. Fan - eee4343_note1 21
The relative levels of the terminal voltages of the enhancement-type
PMOS transistor for operation
- in the triode region
- in the saturation region.
Summary of MOSFET Current Voltage (i-v) Characteristics
Dr. Fan - eee4343_note1 22
NMOS and PMOS in conditions for triode and saturation regions

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