Developing An OS From The

Ground Up
Sayantan Chatterjee
M.Tech (I.T.) 4
th
Semester
West Bengal University of Technology
Roll No: 30008012013
Reg No: 123000410092
Guided By: Mr Santanu Chatterjee
Motivation
Understanding how an OS works.
Understanding the hardware-software
interface.
Gaining skill with coding in C and assembly.
Implementing a concrete and extensible
software.
Features Implemented
VGA text mode display.
Segmentation.
Interrupt and Exception Handling.
Hardware Interrupt Request Handling.
A System Timer.
A Keyboard Driver.
Command Interpreter.
Plethora of string handling, screen output, and
other functions.
Tools Of The Trade
NASM assembler.
GCC cross-compiler.
GNU Linker Script Language LD.
Qemu VMM.
Grub Boot Loader.
Ubuntu Linux.
Cross Compiler
A cross compiler is a compiler that runs on
platform A, but generates codes for platform
B.
My development platform is a Linux machine.
My intended platform is i386-elf format binary
written without the support of any third-party
library functions.
Hence the need of a cross-compiler.
Need For A Linker Script[3]
Traditional OS come with linker script as part of
their tool chain.
AOS needs its own linker script.
Writing a linker script is made easy by GNU linker
language, LD.
A linker script collects the input segments of all
source files in output segments and places them
in memory. It also designates the entry point of
the code from where execution should start.
Loading AOS Kernel With Grub[2]
Grub multi-bootloader can load the kernel image
to the memory and then pass control to it,
provided the kernel follows GNU multi-
bootloader specification.
The kernel should start with a MAGIC value
0xBADB002.
It should next define a FLAGS bit-field.
It should then define a CHECKSUM value which
when added to MAGIC and FLAGS fields should
give 0.
Segmentation[5]
Is a memory management scheme in IA-32.
Total memory is divided into slots called
segments and each segment is used to hold
different types of data like code, system stack,
normal data, etc.
Each application can have their own
segments.
Provides memory protection, privilege levels
and prevention of illegal memory access.
Logical, Linear And Physical Address
Segment Selector
Segment Registers
Code Segment (CS) Register.
Data Segment (DS) Register.
Stack Segment (SS) Register.
General Purpose Registers (ES, FS and GS).
The segment selector values of code, data and
stack segments are loaded into CS, DS and SS
registers for quick access.

Segment Descriptors
Global Descriptor Table
Segment Descriptors form the entries of GDT.
The base address of the GDT is stored in
GDTR.
The LGDT command takes the base address of
GDT and loads it into GDT Register (GDTR).
In addition to the base address of the GDT,
GDTR also holds the maximum size of the
table.
Interrupts[6]
The Intel Developers Manual defines interrupts as
events that indicate a condition exist somewhere in the
system, the processor, or the currently executing
program or task that requires the attention of the
processor.
Exceptions are a form of interrupt which are generated
when the processor detects an error condition while
executing an instruction.
When an interrupt is received or an exception is
detected, the currently running procedure or task is
suspended while the processor executes an interrupt
or exception handler.
Interrupts (contd)
Every interrupt has a number, called vector
number, associated with it.
The vector number is an index into the Interrupt
Descriptor Table (IDT).
Each IDT entry (called interrupt descriptor)
contains information about the handler of the
corresponding interrupt like its location in
memory.
When an interrupt is generated the CPU indexes
into the IDT and runs the interrupts handler.
Interrupts (Contd)
Interrupt Descriptor Table
IDT associates each exception or interrupt vector
with a descriptor for the procedure or task used
to service the associated exception or interrupt.
The base address of the IDT is stored in IDT
Register (IDTR).
LIDT command loads the base address of IDT in
IDTR.
Along with the base address IDTR also holds the
maximum size of IDT.
Interrupt Descriptor
Interrupt Requests[7]
Interrupts raised by peripheral devices are called
Interrupt Requests (IRQs).
The IRQs are handled by PIC chips, also called
8259A in Intel Processors.
There are two PIC chips, master and slave, in the
system.
Each PIC chip can handle up to eight interrupts.
Once a device generates an IRQ, The PIC lets the
CPU know its vector number, with which the CPU
executes the interrupt handler.
Interrupt Requests (Contd)
Programmable Interrupt Controller
Chip
Any IBM PC/AT Compatible computer has 2
chips that are used to manage IRQs.
One 8259 acts as the 'Master' IRQ controller,
and one is the 'Slave' IRQ controller.
The slave is connected to IRQ2 on the master
controller. The master IRQ controller is
connected directly to the processor itself, to
send signals.
PIC (Contd)
IRQ0 to IRQ7 are originally mapped to IDT
entries 8 through 15.
IRQ8 to IRQ15 are mapped to IDT entries 0x70
through 0x78.
IRQ0-7 overlap with architecture defined
exceptions.
The PIC can be programmed to re-map IRQs.
AOS maps IRQ0 to IRQ15 to vector number 32
through 47.
PIC Block Diagram
PIC Interrupt Sequence
One or more of the Interrupt Request lines
(IR7-0) are raised high, setting the
corresponding IRR bits.
The 8259A evaluates these requests and sends
an INT to the CPU, if appropriate.
The CPU acknowledges the INT and responds
with a INTA pulse.

PIC Interrupt Sequence (Contd)
Upon receiving INTA from the CPU, the highest
priority ISR bit is set and the corresponding IRR
bit is reset.
The CPU will initiate a second INTA pulse. During
this pulse, the 8259A releases vectoring data
onto the data bus where it is read by the CPU.
This completes the interrupt cycle. In the AEOI
mode the ISR bit is reset at the end of the second
INTA pulse. Otherwise, the ISR bit remains set
until an appropriate EOI command is issued at the
end of interrupt subroutine.

PIC Ports
Chip Purpose I/O Port
Master PIC Command 0x20
Master PIC Data 0x21
Slave PIC Command 0xA0
Slave PIC Data 0xA1
Initializing The PICs: Code Example
/* ICW1: Initialize the PICs in edge-triggered cascade mode. */
outportb(0x20, 0x11);
outportb(0xA0, 0x11);

/* ICW2: We remap the starting offset of master PIC to entry
* 32 and the slave PIC to entry 40. */
outportb(0x21, 0x20);
outportb(0xA1, 0x28);

/* ICW3: We need to set the IRQ2 line of 8259A to cascade the
* slave chip. The slave chip should also be told that it
* is the second 8259 chip. */
outportb(0x21, 0x04);
outportb(0xA1, 0x02);

/* ICW4: We set both the PICs to 8086/88 mode. */
outportb(0x21, 0x01);
outportb(0xA1, 0x01);

The Programmable Interval Timer[8]
The PIT or system timer is a device that
generates IRQ in a regular interval.
Has three channels:
Channel 0: Connected to IRQ0
Channel 1: Not Used
Channel 2: Connected to Speaker
AOS kernel is concerned with channel 0.
PIT: Working Principle
Is fed an input signal of frequency 1.19MHz.
Has a counter with a preset value which counts
down to 0 with every oscillation of the input
signal.
Once the counter reaches 0 it generates an IRQ0
interrupt.
The frequency of the output signal can be
changed by loading the counter with different
preset values.
The preset values are written to the
corresponding channels data port.
PIT Ports
I/O Port Usage
0x40 Channel 0 Data Port
0x41 Channel 1 Data Port
0x42 Channel 2 Data Port
0x43 Command Port
PIT Command Port
Bits 6
and 7
(Select
Channel)
(00)
Bits 4
and 5
(Access
Mode)
(11)
Bits 1 to
3
(Operatin
g Mode)
(110)
Bit 0
(BCD/Bin
ary
Mode)
(0)
Select Channel: Which
channel to configure.
Access Mode: How to
access data ports.
Operating Mode: Channel
0 should act as a
frequency divider.
BCD/Bin Mode: Whether
the counter counts down
in binary or BCD.
Initializing PIT: Code Example
/* The internal clock rate is 1193180 hz.
* The new rate is decided by dividing 1193180
* by the data we input into the data register. */
size_t divisor = 1193180 / hz;

/* Setup our clock. */
outportb(0x43, 0x36);
outportb(0x40, divisor & 0x0FF); /* Set low byte of
divisor. */
outportb(0x40, divisor >> 8); /* Set high byte of
divisor. */
Applications Of PIT
Is used to keep system time.
Can be used to implement sleep.
Is used in process scheduling.
PS/2 Keyboard Driver[9]
Keyboards communicate with the computer
through the PS/2 controller using serial
communication.
Every key has an associated numerical value
called scancode.
When a key is pressed (or released) the 8-bit
scancode is written to the data register at port
0x60.
Keyboard (Contd)
The MSB of the scancode is used to determine
whether a key is pressed or released. If the MSB
is set then the key is released.
AOS keeps a look-up table (an array of values) of
ASCII codes of keys indexed by their scancodes.
When a key is pressed, the keyboard generates a
IRQ1. The CPU then calls the keyboard handler,
which reads the scancode from port 0x60 and
prints the corresponding ASCII character.
VGA Text Mode Display[10]
Video Graphics Array displays characters to
the screen by loading them from a memory
buffer.
The VGA memory buffer starts at address
0xB8000.
Each buffer entry consists of the ASCII value
of the character to be displayed as well as its
foreground and background color.
VGA (Contd)
Foreground Color (Bits 12
to 15)
Background Color (Bits 8
to 11)
Character (Bits 0 to 7)

VGA (Contd)
The VGA card treats the screen as 80 x 25
array.
In order to print a character at screen location
(x, y) the address in the buffer is calculated as:
index = 0xB8000 + ((y * 80) + x).
Storing the character and its attributes at the
calculated address automatically displays it to
the screen.
Other Features: Command Interpreter
AOS has routines that can interpret keywords
entered by the user.
Whenever the user types in the keyboard, the
keyboard driver stores the character typed in a
command buffer.
Every time a newline is typed, the command
interpreter checks the buffer for specific
keywords.
For now, if the user types time, time elapsed
since booting is displayed.
Other Features: Utility Functions
As AOS can not use third-party library
functions, various C-equivalent utility
functions have been implemented.
Such functions include common string-
handling routines like strlen, strcmp, reverse;
memory access routines like memcopy,
memset, memstew; utility function itoa; and
screen output functions putch, puts and printf.
Future Scope
AOS kernel code is extensible in nature.
Implementing memory allocator/de-allocator
and paging on top of existing code will be
easy.
Once full memory management is in place,
other features like filesystem and process
management can be implemented.
The display system can also be upgraded to
modern graphics.
Conclusion
This project has been an educational and skill
building experience for me.
Has helped me learn about the internal
workings of an OS.
Has made me more proficient with C and
assembly.
Has given me better idea of the
hardware/software interface.
References
Computer History Museum Timeline of Computer History [Online]. Available:
www.computerhistory.org/timeline/?year=1956
GNU Multiboot Specification version 0.6.96 [Online]. Available:
www.gnu.org/software/grub/manual/multiboot/multiboot.html
The University of Utah, Department of Mathematics Using LD, the GNU link-
Command language [Online]. Available :
www.math.utah.edu/docs/info/id_3.html
Carter, Paul A (2006) PC Assembly Language (pp. 8 10) [Online Book]. Available:
cr.yp.to/2005-590/carter.pdf
Intel Corporation (2013) Protected Mode Memory Management, Intel 64 and
IA-32 Architectures Software Developers Manual, Volume 3 [Online Document].
Available: www.intel.com/content/www/us/en/processors/architectures-software-
developer-manuals.html?iid=tech-vt-tech+64-32_manuals
Intel Corporation (2013) Interrupt and Exception Handling, Intel 64 and IA-32
Architectures Software Developers Manual, Volume 3 [Online Document].
Available: www.intel.com/content/www/us/en/processors/architectures-software-
developer-manuals.html?iid=tech-vt-tech+64-32_manuals
References (Contd)
Intel Corporation (2013) 8259A Programmable Interrupt
Controller (8259A/8259A-2) [Online Document]. Available:
http://pdos.csail.mit.edu/6.828/2010/readings/hardware/8
259A.pdf
Intel Corporation 8254 Programmable Interval Timer
[Online Document]. Available:
www.stanford.edu/class/cs140/projects/specs/8254.pdf
Chapweske, Adam (2003) The PS/2 Keyboard Interface
[Online]. Available: www.computer-
engineering.org/ps2keyboard/
Osdevr VGA/SVGA Video Programming [Online].
Available: www.osdevr.net/FreeVGA/vga/vgatext.htm
Thank You