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DSP Algorithms & Architecture Jan 2014

This document contains questions from a DSP Algorithms and Architecture exam. It asks students to answer questions about DSP systems, sampling rates, FIR filters, addressing modes, MAC instructions, and clock generators for the TMS320C54XX processor. Specific questions include explaining the decimation process, determining analog and digital frequencies from a given sampling rate and sample number, explaining data and instruction level parallelism in FIR filters, describing architectural features of the TMS320C54XX, and writing a program to calculate the sum of a series of signed numbers.

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Prasad C M
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0% found this document useful (0 votes)
478 views2 pages

DSP Algorithms & Architecture Jan 2014

This document contains questions from a DSP Algorithms and Architecture exam. It asks students to answer questions about DSP systems, sampling rates, FIR filters, addressing modes, MAC instructions, and clock generators for the TMS320C54XX processor. Specific questions include explaining the decimation process, determining analog and digital frequencies from a given sampling rate and sample number, explaining data and instruction level parallelism in FIR filters, describing architectural features of the TMS320C54XX, and writing a program to calculate the sum of a series of signed numbers.

Uploaded by

Prasad C M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Seventh Semester B.E. Degree Examination, Dec. 20l3lJan.2Ol4
DSP Algorithms and Architecture
Time: 3 hrs.
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Max. Marks:100
Note: Answer FIVEfull questions, selecting
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a. With a.neht',,,block diagram, explain the scheme of a DSP systemrwith typical signals in a
DSP scheme,,,,,.
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(10 Marks)
b. Briefly explain the-,decimation process.
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(04 Marks)
c. An analog signal is"sampled at arate of 8 KHz. If 512 samples of the signal are used to
compute DSP, X(K)l ilelermine the analog and digital frequency spacing between adjacent
X(K) elements. Also, determine analog and digital-ftequencies corresponding to K:64.
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(06 Marks)
a. Investigate to basic features that",should be provided in to DSP architecture to be used to
provided in to DSP architecture to b,ufu$ed to implement to following Nth
-order
FIR filter.
(06 Marks)
b.
With a neat diagram, explain trr" ;r;i.;" level parallelism and pipelining with pipelined
implementation of an 8
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tap FIR filter using eight MACs and parallel implementation of an
8
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Explain the indirect addressing mode.
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a. Explain the maiu'arUhitectural features of TMS 320 C 54 XX processor. (06 Marks)
b. Explain the bit'ionfiguration of PMST register. (08 Marks)
c. With an ex,ample each, explain immediate addressing mode, absolute addressing mode,
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Describe the operation of the following MAC instructions :
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Explain the operations of the following instructions :
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Write a program to find the sum of sum of series of signed numbers as specified
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Assume ARl as pointer to x(i) and AR2 as counter for the numbers.
Briefly explain the clock generator of TMS320C54XX. d.
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