Group 2

EEC 581 Computer Architecture

Project

Jenil Shah : 2619535 Kalpesh Patel :2619912 Jainesh Patel :2619205 Mohammadhadi Khorrami :2505631

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EEC Computer architecture, spring 2014

Title: A Built In self Repair scheme for NOR- type Flash Memory Goal: To improve loss of memory problem, BISR is very effective solution for NOR flash memory. Overview: Now-a-days flash memory is so far become popular non volatile memory because of its compact size and easily erase data property. Due to compact size, It is widely used in portable devices like laptop, MP3 player, cell phone, PDA etc. With the help of IC manufacturing and system on chip (SOC) design methodology, demand and uses of embedded flash memory are increased in those application. In flash memory, it is ordinary to repair and test memories using probe station in wafer test stage. To address this problems , we have effective solution like built in self test (BIST) and built in self repair (BISR). Generally there are three parts in typical BISR design : 1) the built in self test (BIST) module , 2) built in redundancy analysis (BIRA) module , 3) address reconfiguration (AR) module. In this paper, they have give information about BISR design for NOR flash memory based on typical redundancy architecture. IF single spare row is used to repair faulty cell then might be possibility of the block failure. We can address this problem with the help of redundancy architecture. To increase output, designers are inserting more and more spare rooms in flash memory. BISR architecture is made up of BIST/BISD, BIRA, test collar and CAM modules. IN normal mode flash memory is used by PIs and Pos, when at the time of test mode, it is used by tPIs, tPOs. Address input is compared with repaired data stored in CAM, to check whether it is faulty or not. CAM is a kind of flash memory so it can save repaired data at power off. At the time of power on data is retrieved from CAM and stored into small high speed SRAM. They have also used multiplexer and de-multiplexer to avoid using of faulty cell when program command is issued. They have also include flow chart of self repair procedure of a flash memory. At the starting process, repaired data is retrieved first, which is stored in to the CAM. With the help of user defined march algorithm and fault models, BIST/BISD finds faulty cell in the memory. They have also mention BISR process like in test 1BISD/BIST uses the spare element directly. In the Test 2, main memory test is completed and after that BIRA writes repair data in CAM. Conclusion: To analyse the fault information and generate required spare allocation, BIRA works with BISD/BIST. The modified ESP algorithm is nominated to constrain redundancy architecture. There is possibility to address BISR and RA for NAND flash memory , but difficulty is different circuit architecture. Reference : 1 ) Yu-Ying Hsiao, Chao-Hsun Chen A built in self repair scheme for NOR memory, IEEE,2006 flash

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2 )D.K bhavsar An algorithm for row column self repair of RAMs , 1999 pp.311-318 3 ) J.F. Li, J.C. Yeh A built in self repair design for RAMs with 2-D redundancy IEEE Trans ,2005 4 ) J.-C. Yeh, Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, Flash memory built-in self-diagnosis with test mode control, in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs,May 2005, pp. 1520. 5 ) H. Miwa, T. Tanaka, K. Oshima, Y. Nakamura, T. Ishii,A. Ohba, Y. Kouro, T. Furukawa, Y. Ikeda, O. Tsuchiya, R. Hori, and K. Miyazawa, A 140 64Mb AND flash memory with a 0.4 m technology, in Proc. IEEE Int. Solid-State Cir. Conf. (ISSCC), 1996, pp. 3435.

Group 2

EEC Computer Architecture, Spring 2014

Title: Temperature Self-adaptive program algorithm on 65 nm MLC NOR flash memory Overview: This project is about an implementation for improving multi-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. A temperature self- adaptive programming algorithm is proposed to increase according to the on-die temperature. The experimental result show that the program throughput is increased significantly 30% and it is 70 times faster than before. Summary: Multi-level cell (MLC) storage technology is widely used to increase density and lower product cost. NOR flash memory is mainly used for code storage because of its fast random access time. MLC NOR flash memory uses mainly channel hot electrons (CHE) for the programming. This paper proposes an algorithm to improve the program throughput by using the CHE temperature characteristic. The CHE temperature dependence is analyzed with the Lucky electron model. The implementation of temperature self-adaptive programming on both circuit and algorithm perspective, which improves the program throughput by adjusting based upon the temperature. An on-chip temperature detector which is proportional to absolute temperature (PTAT) is used to detect the temperature in real time. Based on the PTAT output, the write state machine (WSM) controls the word-line pump, regulator, and drain voltage generator to generate different output voltage depending on temperature. The proposed temperature self-adaptive programming is implemented in Intel 65 nm flash technology and tested and with the proposed programming algorithm, it can achieve 1.4 Mbps with the same degree of parallelism DOP. Conclusion: This paper has presented the implementation of temperature self-adaptive programming on 65 nm 2 bits/cell MLC technology. Experimental result show that the program throughput increase significantly from 1.1Mbps without temperature self-adaptive programming to 1.4 Mbps with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput. References: 1. Wong G. Flash memory trends. Flash Memory Summit, 2008. http: //web. njit.edu/_rlopes/5.2%20 %20Flash%20Memory% 20Trends FMS.pdf 2. Kim J P, Yang W, Tan H Y. A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme. IEEE J Solid-State Circuits, 2003, 38(2): 329 3. Grossi M, Lanzoni M, Ricc`o B. A novel algorithm for highthroughput programming of multi-level flash memories. IEEE Trans Electron Devices, 2003, 50(5): 1290 4. Taub M, Bains R, Barkley G, et al. A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming. ISSCC Dig Tech Papers, 2005

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EEC Computer Architecture, Spring 2014

Title: Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold SourceSide Injection in Wrapped-Select-Gate SONOS for NOR-Type flash memory Goal: To enhance the programming efficiency of WSG SONOS for NOR-type flash memory Overview: In this paper we used the source side injection technique for high programming efficiency. The major process and the cross sectional images of the WSG-SONOS memory structure are detailed in the paper. Based on the concepts they discussed in the paper, there are three kinds of programming methods for WSG-SONOS devices: normal, DT and body mode. To investigate the physical mechanism of SSI under these three different modes, an ISE TCAD with hot electron and Poisson equation calculation models are used. For DT mode, the selected gate is tied to a well, whereas Vwell in the body mode is fixed at 0.45 V. The power consumption can be lower than DT mode in the body mode during the charging process of programming due to variation of the threshold voltage in the DT mode. Under the same programming conditions a typical bell-shaped distribution is observed in both normal and body modes but not in the DT mode. Across all the three modes, the higher Vwl exhibits a larger programming window. This is because high Vwl not only enhances the collection ability with increasing normal electric field but also raises the hot electron generation rate by increasing the voltage drop across the gap region. This is because, as the wrapped MOSFET overdrive becomes higher, the voltage drop across the neutral gap region decreases, decreasing the efficiency of programming. Furthermore, the DT mode exhibits different behaviour from the normal and body modes. The typical programming characteristics of the DTSSI have a higher memory window while Vsg is still a low voltage. The DT mode processes a larger acceleration electrical field between the WSG and the word gate. Therefore, the hot-electron generation rate can be enhanced. Under DT mode, the devices exhibited increased lateral electric field and current. These changes enhanced the programming efficiency of WSG SONOS for NOR-type flash memory. References: [1] L.Breuil, L.Haspeslagh, P.Blomme, D.Wellekens, J.D Vos, M. Lorenzini and J.V.Houdt, A new scalable self-aligned dual-bit Split gate charge- trapping memory device, IEEE Trans. Electron Devices, vol.52,no.10, pp. 2250-2257, oct-2005 [2] H. Tomiye, T. Terano, K. Nomoto and T. Kobayashi, A novel 2 bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection, in VLSI symp. Tech. Dig., 2002, pp.206-207 [3] C. Y. Lu, T.C. Lu, and R.Liu, Non-volatile memory technology- Today and tomorrow, in Proc. IPFA , 2006, pp. 18-23

Group 2

EEC Computer Architecture, Spring 2014

Title: Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology. Goal: The hybrid floating gate (FG) memory cell concept has been presented in this paper and proposed as a viable solution to extend the NAND Flash memory roadmap below the 20nm technology node. Overview: In this paper a dual-layer (or hybrid) floating gate (HFG), which combines a ntype poly-Si at tunnel oxide interface with a p-type metal at the interpoly dielectric (IPD) interface is proposed for NAND Flash memory development for sub-20-nm technologies. Limitation of the pitch scaling of conventional NAND Flash memory cell is the loss of control gate (CG) to floating gate (FG) sidewall capacitance when the space between neighboring cells becomes so small that the IPD and CG can no longer be wrapped around the FG. This causes severe program saturation. To reduce program saturation without degrading erase performance, HFG is proposed. In this stack, p-type metal at IPD interface increase the tunneling barrier and a thin poly-Si layer at tunnel oxide interface avoids increasing the barrier for tunnel erasing the memory cell. The fabrication process of HFG memory cell using 65-nm CMOS process flow with gate length of 70-nm is described by the author. The superiority of HFG memory cell compared to poly-only FG cell is showed by comparing incremental step pulse programming (ISPP) curves. From the curves it is clear that a memory cell with poly-only FG does not significantly program above the fresh level due to IPD leakage caused by the low cell coupling ratio. On other hand, memory cell with HFG having the same low coupling ratio can be programmed without strongly being affected by IDP leakage. Also the HFG does not affect the erase performance, unlike what would be the case when using a metal-only FG. At the end the effect of the quality of the spacer oxide liner on retention has been investigated, by comparing high-temperature oxide deposition (HTO) and plasma enhanced atomic layer deposition (PLEAD) oxide. References: 1. P. Blomme, A. Cacciato, D. Wellekens, L. Breuil, M. Rosmeulen, G. S. Kar, S. Locorotondo, C. Vrancken, O. Richard, I. Debusschere, and J. Van Houdt, Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology. IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 3, MARCH 2012 2. P. Blomme, M. Rosmeulen, A. Cacciato, M. Kostermans, C. Vranken, S. Van Aerde, T. Schram, I. Debusschere, M. Jurckzak, and J. Van Houdt, Novel dual layer oating gate structure as enabler of fully planar ash memory, in Proc. VLSI Technol. Symp., 2010, pp. 129130. 3. M. Rosmeulen, Multiple layer floating gate non-volatile memory device U.S. Patent 7906806 B2, Mar. 15, 2011

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EEC Computer architecture, spring 2014

Title: HDC: An adaptive buffer replacement algorithm for NAND flash memory-based databases Overview: This paper proposes an adaptive buffer replacement algorithm for NAND flash memory-based databases, which is called HDC. HDC introduces an efficient replacing index for selecting pages to be evicted. This replacing index considers two factors: the hot degree of each page and the cost of writing the victim page back to NAND flash memory. It can adaptively change the weight of each factor according to the cost ratio of NAND flash memory. HDC also introduces an efficient partial update scheme, which only writes the dirty data within the dirty victim page back to NAND flash memory for further reducing the number of write operations and writes the dirty data to the free block with the lowest erase count for improving the wear-leveling degree of NAND flash memory. The experimental results show that HDC outperforms the state-of-the-art algorithms on both these kinds of NAND flash memories. Background and related work: In order to reduce the number of write operations to NAND flash memory and prevent the serious degradation of buffer hit ratio, a number of buffer replacement algorithms have been studied for NAND flash memory by modifying the LRU algorithm in the light of its unique characteristics. CFLRU is the first buffer replacement algorithm customized for NAND flash memory and it divides the LRU list into two regions, which are the clean-first region and working region, respectively. Yoo et al. extended the CFLRU and proposed three buffer replacement algorithms for NAND flash memory, which are CFLRU/C, CFLRU/E, and DL-CFLRU/. Both of CFLRU/C and CFLRU/E only modified the CFLRU in the way of evicting the dirty pages within the clean-first region. The CFLRU/C evicts the dirty page with the lowest access frequency while the CFLRU/E selects the dirty page belonging to the block with the lowest erase count as victim page. The DLCFLRU/E maintains two page lists, which are the clean page list and the dirty page list, respectively. The DL-CFLRU/E first evicts the least recently referenced page within the clean page list. Also has been proposed a buffer replacement algorithm for NAND flash memory, which is called LRU-WSR. The LRU-WSR modified the LRU algorithm by delaying the evictions of not-cold dirty pages from the buffer cache to NAND flash memory. Li et al. proposed an efficient buffer replacement algorithm called CCF-LRU to preferentially evict the page that is cold and clean. All of the above mentioned buffer replacement algorithms are proposed by modifying the LRU algorithm that designed for magnetic disk and evicting the clean pages preferentially under the assumption that the cost of write operation to NAND flash memory is much higher than that of read operation and the cost of read operation can be negligible. Performance evaluation: The experimentalresults show that the proposed HDC outperforms the LRU designed for magnetic disk and other buffer replacement algorithms customized for NAND flash memory in terms of buffer hit ratio, the number of write operations, and runtime.

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References: [1] M. Lin, S. Chen, G. Lv, Z. Zhou, Optimized Linux swap system for flash memory, Electron. Lett. 47 (11) (2011) 641642. [2] M. Lin, S. Chen, G. Wang, Greedy page replacement algorithm for flash-aware swap system, IEEE Trans. Consum. Electron. 58 (2) (2012) 435440. [3] A. Kawaguchi, S. Nishioka, H. Motoda, A flash-memory based file system, in: Proc. Of the USENIX Technical Conference on UNIX and Advanced Computing Systems, 1995, p. 13. [4] M.W. Lin, S.Y. Chen, Y. Lu, Z. Zhou, Garbage collection policy for flash-aware Linux swap system, Electron. Lett. 47 (22) (2011) 12181220. [5] D.P. Bovet, M. Cesati, Understanding the Linux Kernel, 3rd ed., OReilly Media, Sebastopol, CA, USA, 2005. [6] E.J. ONeil, P.E. ONeil, G. Weikum, The LRU-K page replacement algorithm for database disk buffering, in: Proc. of the 1993 ACM SIGMOD International Conference on Management of Data, 1993, pp. 297306. [7] T. Johnson, D. Shasha, 2Q: a low overhead high performance buffer management replacement algorithm, in: Proc. of the 20th International Conference on Very Large Databases, 1994, pp. 439450. [8] S. Jiang, X.D. Zhang, LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache performance, in: Proc. of ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 2002, pp.3142. [9] S. Jiang, F. Chen, X. Zhang, CLOCK-Pro: an effective improvement of the CLOCK replacement, in: Proc. of the USENIX Annual Technical Conference, 2005, pp.323336. [10] S.Y. Park, D. Jung, CFLR U: a replacement algorithm for flash memory, in: Proc. of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2006, pp. 234241. [11] Y.S. Yoo, H. Lee, Y. Ryu, H. Bahn, Page replacement algorithms for NAND flash memory storages, Lect. Notes Comput. Sci. 4705 (2007) 201212. [12] H. Jung, H. Shim, S. Park, S. Kang, J. Cha, LRU-WSR: integration of LRU and writes sequence reordering for flash memory, IEEE Trans. Consum. Electron.54 (3) (2008) 1215 1223. [13] Z. Li, P. Jin, X. Su, K. Cui, L. Yue, CCF-LRU: a new buffer replacement algorithm for flash memory, IEEE Trans. Consum. Electron. 55 (3) (2009) 13511359. [14] X. Tang, X.-F. Meng, Z.-C. Liang, Z.-P. Lu, Cost-based buffer management algorithm for flash database systems, Ruan Jian Xue Bao/J. Softw. 22 (12) (2011)29512964.