CML Microcircuits

COMMUNICATION SEMICONDUCTORS
INN/AIS/3

Marine AIS Processor ICs

AIS-Dedicated Processors for Maritime Safety
. . . . . . for I and Q (Digital) and Limiter-Discriminator (Analogue) Based Systems
www.cmlmicro.com

CML AIS Products

With the high integration on-chip of AIS-specic functions and wide-ranging data-signal processing capabilities, these three dedicated AIS IC products will minimise the nal-product board-area requirement and component count whilst drastically minimising the system software and processing effort; all with a view to a high-performance, low-cost end-product with greatly accelerated time-to-market.

Auxiliary ADCs

Auxiliary DACs

CML AIS Processor

GNSS Engine

AIS and DSC Rx Channel 1

Serial Interface, Control and AIS Formatting

AIS New Fun Rx cti -on on ly I m FI-2 .x age

Host Controller

Radio RF, IF and Detector Stages

AIS and DSC Rx Channel 2

AIS and DSC Tx Channel

Auxiliary System Clocks

Auxiliary Synthesisers

Xtal/Clock Generator

For I and Q based RF Systems CMX910 AIS Class A and B Baseband Processor For Limiter-Discriminator based RF Systems CMX7032 AIS Class B Baseband Processor with RF Synthesisers (FI-1.x) CMX7032 AIS Rx-only Baseband Processor with RF Synthesisers (FI-2.x) CMX7042 AIS Class B Baseband Processor (FI-1.x) With Comprehensive Evaluation and Development Support
EV9100, PE0201, PE0401, PE0001 and DE70321

CML AIS Products for:

Class A and Class B AIS Equipments AIS (Rx Only) Monitors AIS Transmit Modules Aids to Navigation (AToN) Electronic Chart Display and Information Systems (ECDIS) AIS Base Stations

The Marine Automatic Identication System (AIS)

Index . . .
The AIS System CML ICs in AIS Systems CMX910 AIS Class A and B CMX7032/CMX7042 FI-1.x AIS Class B FI-2.x AIS Rx-only Evaluation and Support
Device Conguration

2 3 4 6 8 10
back page

Used extensively as an aid to maritime navigation and safety by ships, aircraft and xed or oating structures, an AIS transponder continually broadcasts the host vessels positional and status information. This enables other similarly equipped vessels in the vicinity to receive, decode and display that information, along with information from other navigational systems (radar, GPS, depth recorders), to provide a comprehensive picture of the maritime trafc in the local area. Using an omni-directional broadcast of formatted wireless-data in the VHF maritime band, an AIS system employs two simultaneous Rx channels and a single, frequency-switched, Tx channel. The AIS system will normally operate in an autonomous continuous mode. Using Self-Organising Time Division Multiple Access (SOTDMA) technology, AIS messages are packed into over-air time slots that are accurately synchronised using either GNSS or local timing information. An AIS system can handle well over 4,500 reports per minute using individual 26.6ms time slots on both Rx channels. Each station transmits and receives over two radio channels to avoid interference problems, and to allow channels to be shifted without communications loss.

The System
The efcient exchange of navigational data between ships and shore stations Autonomous, automatic and continuous operation Employs Time Division Multiple Access (TDMA) techniques Class A: SOLAS vessels Class B: Smaller vessels Operates in the VHF maritime mobile band

Uses two simultaneous AIS channels and one Digital Selcall (DSC) channel AIS Modulation: GMSK - 9600bps DSC Modulation: FSK - 1200bps Transmits: - Static and dynamic vessel information - Voyage related information - Safety messages

Fomatted AIS Data

MMSI number Callsign and Name Type of Vessel Length, Beam and Draught Vessel Position Navigational Status Log (speed) Course and Speed Location of Position Fixing Antenna Compass (course) Time (UTC) Heading GPS (position/timing) Rudder Angle Rate of Turn Keyboard Inputs Cargo Type Destination Estimated Time of Arrival

Tx

Rx

Vessel and Voyage Information

Graphic Display

AIS Classes

AIS System

Printer Alarms

There are currently two maritime-mobile classes of AIS operation: Class A (SOLAS vessels) 3 Rx Channels (AIS 1, AIS 2 and DSC) must be monitored simultaneously DSC is transmitted as required All AIS timing must be sourced from a received GPS (UTC) tick input Class A transmissions take priority over Class B Class A transmissions may use more that one consecutive slot per cycle

Example AIS Information Flow

Self-Organising Time Domain Multiple Access Operation (SOTDMA) SOTDMA technology is at the heart of the Class A and Class B AIS systems operation. AIS messages are packed into over-air time slots in a continuous repeating framework.
1 minute
0 1 2 3 4 5 2245 2246 2247 2248 2249 0 1 2 3 2245 2246 2247 2248 2249 0 1 2 3 2245

The timing of each individual slot within the frame is accurately synchronised using either GNSS-based or local timing information. Each minute in time is divided into 2250 timeslots. Each individual slot carries one vessels data using HDLC packet protocol formats.

Class B (Non-SOLAS AIS vessels) 2 Rx Channels (AIS 1 and AIS 2) must be monitored simultaneously GPS timing is not mandatory - in its absence, timing is obtained from the transmissions of nearby, more accurate AIS transmissions Can only use one slot per cycle - gives way to Class A transmissions

AIS Slot Timing: 2250 Slots every 60 seconds; Slot length = 26.6ms

With regard to the slot cycle (described above), the local AIS system transmits the relevant data in HDLC packet format. At the same time it reserves a future slot in the next frame. This timeslot method and the use of two radio channels, avoids, in the long-term, the cumulative effect of packet collisions. An AIS Class A system will transmit directly in its chosen slot and may use more than one slot period per cycle if required.

An AIS Class B CSTDMA system can only use one slot period and must check its chosen slot for Rx energy before transmitting. As ships join and leave areas they form local area-networks, taking care not to interfere with each other. As they move out of range of a network, they continue to broadcast their positions, all the time listening for other networks to join.

Time Sequence 1 Frame 1 Slot AIS Data Rate

1 Frame = 1 minute 2250 slots 26.6ms 9600bps - GMSK

CML ICs in AIS Systems

AIS IC Product Selector - B u i l t o n F i r m AS I C Te c h n o l o g y CMX910 (Rx/Tx)
Modulation AIS Support On-Chip AIS Data Handling Modes On-chip AIS Data Formatting AIS Signal Timing Peripheral Timing Rx Modes Tx Modes RF Channel Bandwidth Rx Interface Tx Interface Auxiliary ADCs and DACs Auxiliary System Clocks RF Synthesisers Control Interface AIS Tx System Format Compatibility Device Conguration via: Supply Requirements Packages 64-lead LQFP (L9) 64-no lead VQFN (Q1) EV9100 EvKit GMSK and FSK A and B AIS Burst and Raw HDLC and NRZI Slot and Sample Sequenced, timed control of external circuits AIS and DSC AIS and DSC 12.5 and 25 kHz I and Q I and Q 5 x 10-bit (Mux) ADCs 5 x 10-bit DACs None None C-BUS and Expansion Port SOTDMA CSTDMA Conguration File

Designed for implementation in both the simple, traditional, limiter-discriminator and the more versatile digital (I and Q) based AIS systems, CML currently offers three exible AIS compatible ICs: CMX910 AIS Baseband Processor for I and Q based Systems CMX7032 AIS Data Processor with RF Synthesiser for Limiter-Discriminator based systems (FI-1.x), or AIS Rx-only Data Processor with RF Synthesiser for Limiter-Discriminator based systems (FI-2.x) CMX7042 AIS Data Processor for Limiter-Discriminator based systems (FI-1.x) AIS Transponders Feature-rich, each offers two simultanous Rx channels and one Tx channel, a channel which can be frequency-switched in line with AIS regulations. High on-chip integration with AIS and DSC specic data manipulation and frame-formatting allows the ICs to handle the majority of the computationally intensive tasks normally carried out by the host. Using a serial data/command interface (C-BUS) these products use a simple transactionoriented command/response protocol to address specic registers within the IC, with data buffering on chip. Accurate timing, obtained from a GNSS source, is maintained to provide both AIS related and system timings. In addition to AIS signal and data handling, these products offer a range of auxiliary functions for peripheral communications, including ADCs, DACs and synthesised system clocks. AIS Rx Only New to the product roadmap is the AIS Rx-only conguration of the CMX7032 using FI-2.x. Designed to operate virtually stand-alone, this conguration requires no host control.

CMX7032 (FI-1.x) (Rx/Tx + RF)

GMSK and FSK B AIS Burst and Raw HDLC and NRZI Sample 2 x System Clocks AIS and DSC AIS 25kHz Limiter-Discriminator Two-Point Modulation/ I and Q 4 x 10-bit (Mux) ADCs 4 x 10-bit DACs 2 x System Clocks 2 x Individual (100 to 600 MHz) C-BUS SOTDMA CSTDMA Function Image 64-lead LQFP (L9) 64-no lead VQFN (Q1) PE0201 EvKit PE0001 Interface Card DE70321 DemoKit

CMX7032 (FI-2.x) (Rx-only + RF)

GMSK A and B Processes dual (Rx) channel AIS data to an NMEA data stream output NA 2 x System Clocks AIS NA NA Limiter-Discriminator NA NA 2 x System Clocks 2 x Individual (100 to 600 MHz) RS232 NA Function Image 64-lead LQFP (L9) 64-no lead VQFN (Q1) PE0201 EvKit DE70321 DemoKit

CMX7042 (FI-1.x) (Rx/Tx)

GMSK and FSK B AIS Burst and Raw HDLC and NRZI Sample 2 x System Clocks AIS and DSC AIS 25kHz Limiter-Discriminator Two-Point Modulation/ I and Q 4 x 10-bit (Mux) ADCs 4 x 10-bit DACs 2 x System Clocks None C-BUS SOTDMA CSTDMA Function Image 48-lead LQFP (L4) 48-lead VQFN (Q3) PE0401 EvKit PE0001 Interface Card

Thunderer
Wavelove
HMT Dorset

HMT Hercules

Pipkin

HMT Forcefull

3.0 to 3.6 V
Name: Callsign: MMSI: IMO: Status: Dest: ETA: Type: Speed/Dir: Size: LONE WONSILD OULD2 219420000 8802791 Underway FAWLEY Jul12 10:00 Tanker 12.7 kts / 295 84m x 14m x 4m

Yazicatann

Evaluation

Wild Girl

An AIS Display Example

CMX910 AIS Baseband Processor for I and Q based Systems

Designed specically for all current modes of AIS operation, the CMX910 offers a highly integrated IC capable of performing all of the required data-handling, formatting, timing, distribution and control functions under the control of the host. Provided on-chip are both of the mandated GMSK Rx channels and a single Tx channel. Selectable to 12.5 and 25 kHz channel modes for AIS, the CMX910 accommodates, in Rx and Tx, both full AIS data packet assembly and disassembly and a basic raw data facility. Both AIS (GMSK) and DSC (FSK) I and Q modulated signalling modes are available. A third, parallel (Rx) decode path, accommodates the DSC (FSK) signalling from an external modem for Class A AIS applications. Integration of all AIS functions, including versatile synchronisation and slot and sample timing and control facilities is available. Control and interfacing, including upgraded data-streaming, are via the C-BUS serial interface, with a host-controlled expansion port for the addition of an external FX/MX604 modem IC. The provision of the C-BUS expansion port, an RF device enabling port and a number of auxiliary uncommitted ADCs and DACs, simplifies the system hardware implementation, further reducing the overall equipment cost and size. One of the on-chip DACs has an additional, programmable (RAMDAC) ramp-mode (up or down) feature which is particularly useful for controlling the output prole of the transmitter-power at the beginning and end of a transmit slot to prevent interference to other users by controlling the power-prole of the radios PA. Similarly, a bank of multiplexed analogue-todigital converters provides monitor facilities to the IC and to the system.

12.5kHz

Rx and Tx On-Chip Signal Paths Simultaneous Reception - Two AIS or One AIS, One DSC Differential I and Q Signalling Two Parallel I and Q Rx Paths One I and Q Tx Path Additional FSK (DSC) Decode Path - 1200bps Demodulator Interface Channel Filtering
Tx/Rx
Filter

Rx 1 Q Rx 1 I CS

25kHz
Coupler

VCO

Rx1 1st IF 45MHz

VCO

PLL

PLL

12.5kHz
LNA
Split

Rx 2 Q Rx 2 I

25kHz

CMX910 (part)

VCO

Rx2 1st IF 45MHz

VCO

Host System/s

PLL

PLL

25kHz

Ceramic Filter
Rx3 2nd IF 455kHz

LimiterDiscriminator

FSK Modem (FX/MX604)

FSK Rx Data
Exp 0

VCO

Rx3 1st IF 55MHz

VCO

Carrier Detect

PLL Rx 1 PLL Rx 2 PLL Rx 3

C-BUS Expansion Ports

Exp 1 Exp 2 Exp 3 Exp 4 Exp 5

Expand CS

AIS Data Handling NRSI Coding HDLC Processing - System Flags - Training Sequence - Bit-Stufng AIS and Raw Data Modes CRC Generation and Checking Supports Carrier Sensing (CSTDMA) Operations Integrated Rx and Tx Buffers Flexible Sample and Slot Timing from GNSS-Based (UTC) Source
ADCs
RSSI

I/Q Rx 1

PLL

PLL

I/Q Rx 2 Tx PLL

UTC Sync
PA
Driver

Tx Q Tx I

GPS Module

TxRamp Profile

PA

Tx Rx 1 Rx 2 Rx 3

BPF Filter

Ref. Clock

24MHz VCO

DACs

Enab 0

Enab 2

Enab 4 Enab 5

CMX910 (part)

Enab 1

Enab 3

Timed Device Enable Outputs

VCO

PLL

VCO

CMX910 Peripheral Operations

CMX910 Functions
DVDD
Multiplexed Auxiliary ADC Inputs

3.0 to 3.6 volt Input

Auxiliary DAC Outputs

Features Half-Duplex GMSK, FSK and DSC capabilities Flexible signal channels - Two simultaneous Rx - One Tx - Optional-FSK interface
Chip-Select

IOVDD

Digital 2V5 Regulator

MUX

10-bit DAC

10-bit DAC

10-bit DAC

10-bit DAC

10-bit DAC

DVSS

Sample and Hold

10-bit ADC

Aux DACs

DAC RAM

VBIAS

Bias Generator

5-Input MUX Aux ADC

C-BUS Serial Interface

Supplementary Rx DSC-only data path for external FSK demodulator

Differential I and Q Tx Outputs

I Tx Q

I Q
GF(M)SK/FSK Modulator and Filters

AIS Burst

Message Buffer

HDLC/ NRZI Encoder

Tx FIFO
Tx Channel

Receive Data
Serial Clock
Command Data

AIS formatted data and raw data modes Slot/Sample counter with UTC timing interface I and Q (Tx and Rx) radio interface High performance GMSK encoding/decoding Supports Carrier-Sensing Channel Access (CSTDMA) operation Supports Self Organising Time Domain Multiple Access (SOTDMA) operations

C-BUS Interface

AIS Raw or FSK

Differential I and Q Rx Inputs

I Rx1 Q

I Q
GF(M)SK/FSK Demodulator and Filters
FSK

HDLC/ NRZI Decoder

Message Buffers

AIS Burst

Rx1 FIFO
AIS Raw

Expansion Chip-Select

Rx Channel 1

I Rx 2 Q

I Q
GF(M)SK/FSK Demodulator and Filters
FSK

HDLC/ NRZI Decoder

Message Buffers

AIS Burst

Rx2 FIFO
AIS Raw

Rx Channel 2

Exp 5 Exp 4 Exp 3 Exp 2 Exp 1 Exp 0

For selection of additional C-BUS or general purpose peripherals

Auxiliary ADC and DAC functions - 5 (10-bit) DACs - 5-Input MUX (10-bit) ADC C-BUS (SPI compatible) serial control interface with expansion port RF device-enable facilities Message progress-reports to host Optimum co-channel and adjacent-channel performance Low-power (3.0 to 3.6 V) operation with Sleep and Dynamic powersave EV9100 EvKit support for evaluation, experimentation and design-in Compact package styles

C-BUS Expansion Port

Internal

AVDD

Analogue 2V5 regulator

Device Enable Port

Reset and Clock Control

FSK Retiming

External

FSK FIFO

Slot and Sample Timer

Interrupt Generator

3.0 to 3.6 volt input

Ref. Clock

Reset

FSK Mute FSK Rx Data FSK Detect

Enab 5 Enab 4 Enab 3 Enab 2 Enab 1 Enab 0

UTC Sync

Slot Clock

Auxiliary Functions C-BUS Expansion Port - Select and Address Peripheral C-BUS (SPI) ICs External (RF) Device Enable Port - The Timed Operation of Peripheral System Functions Multiplexed Auxiliary ADC Inputs - External System Signal Monitoring (RSSI, Temperature, RF Power, Battery Voltage) Auxiliary DAC Outputs - External System Control - RAM DAC Tx Power Proling

IOVDD

AVSS

Interrupt

Enable outputs for timed control of peripheral circuits

CMX910 Functional Diagram Package Styles CMX910L9 64 Lead LQFP CMX910Q1 64 No-Leads VQFN

Power and Control

3.0 to 3.6 Volt Low-Power Requirement Serial Data/Command Interface with On-Chip Registers Raw and Formatted AIS Data Handling Full AIS Data Formatting (HDLC and NRSI coding) AIS Sample Timing On-Chip

CMX7032 AIS Class B Baseband Processor with RF Synthesisers CMX7042 AIS Class B Baseband Processor

(FI-1.x) (FI-1.x)

Two highly integrated data signalling processor ICs, both of which full the requirements of the Class B marine Automatic Identication System (AIS) transponder market. Comprising two parallel limiter-discriminator Rx paths and one I and Q or two-point modulation Tx path, these ICs are half-duplex in operation. The Rx paths are congurable to AIS or DSC operation, the Tx path is congurable to AIS only. Both products provide AIS (Rx/Tx) raw and formatted data processes and DSC Rx raw and de-formatted data.
DAC 4
Ref Adjust

Provision of a number of auxiliary ADCs and DACs, two auxiliary system clocks and integrated Rx/Tx data buffers further simplify the system hardware design. Both products are identical in functionality, with the exception that the CMX7032 provides two on-chip RF synthesisers and the CMX7042 none, which enables it to be supplied in a smaller, more compact package. These devices are built on CMLs proprietary FirmASIC component technology. On-chip sub-systems are congured by a Function Image: a data le that is uploaded during device initialisation and which denes the devices function and feature set. The Function Image can be loaded automatically from an external EEPROM or from the host Controller over the C-BUS serial interface. The devices functions and features can be enhanced or altered by subsequent Function Image releases, facilitating in-eld upgrades.

ref osc

DAC 3 Serial Clock MOD 2 XTAL IN

PLL

Slot Clock CS Command Data Rx Data MOD 1 IRQ RAMDAC DAC 2 Tx Enable

PA

VCO
PA Ramping

Rx and Tx On-Chip Signal Paths Simultaneous Reception - Two Parallel AIS Paths
Host System/s

PA Bias

Auxiliary Functions Multiplexed Auxiliary ADC Inputs - External System Signal Monitoring (RSSI, Temperature, RF Power, Battery Voltage) Auxiliary DAC Outputs - External System Control - RAMDAC Tx Power Proling Synthesised System Clocks RF Synthesisers (CMX7032)

Limiter-Discriminator Rx Interfaces One I and Q or Two-Point Modulation Tx Output

Switch

RF1 In
Filter Tuning

VCO
LO 1

CP1 Out
System Clock 1

Filter

Coupler

Tx/Rx

XTAL

AIS Data Handling NRSI Coding HDLC Processing - System Flags - Training Sequence - Bit-Stufng AIS Formatted and Raw Data Modes CRC Generation and Checking Supports Carrier Sensing (CSTDMA) Operations Integrated Rx and Tx Buffers Sample Counter Timing from GNSS-Based (UTC) Source

Rx1

Rx 1 RSSI1

CMX7032 (part)

LNA

Split

2 LOs

n d

RSSI2

Rx2
LO 2

Rx 2

VCO

CP2 Out RF2 In

Power and Control 3.0 to 3.6 Volt Low-Power Requirement Serial Data/Command Interface with On-Chip Registers Raw and Formatted AIS Data Handling Full AIS Data Formatting (HDLC and NRSI coding) AIS Sample Timing On-Chip

RF Power Detect

ADC 1
PSU/Battery Monitor

ADC 2

Rx DSC Operations Rx1 or Rx2 Channels Available for Rx DSC operation Raw or Formatted Modes 6db/octave De-emphasis Rx Filter 1200 Baud FSK Data Raw Mode: - 16-bit Words Directly to C De-formatted: - Dot Pattern and Phasing Detection - Decoded Character and Error Bits to C

CMX7032 (FI-1.x) Peripheral Operations

CMX7032 and CMX7042 AIS Processors for Limiter Discriminator-Based Systems

Tx Enable Slot Clock
Multiplexed Auxiliary ADC Inputs
RSSI 1 RSSI 2 ADC 1 ADC 2
Aux DACs

3.0 to 3.6 volt Input

Features
Auxiliary DAC Outputs

IOVDD
DVSS
VBIAS
Single or Two-Point Mod Tx Outputs

Digital 2V5 Regulator

Bias Generator

DVDD

MUX

10-bit ADC

DAC RAM

GPIO
MUX
10-bit ADC

C-BUS Serial Interface

Chip-Select

Receive Data

Mod 1

AIS Raw

Serial Clock

Tx
Mod 2

MUX

GMSK Modulator

AIS Burst

Message Buffer

HDLC/ NRZI Encoder

Tx Channel

Command Data

Registers
AIS Raw

Rx1
GMSK Demodulator

AIS Burst

HDLC/ NRZI Decoder

Power Control

Message Buffer

Rx Channel 1
Internal Systems Control

BIAS
MUX

FSK Demodulator

Message Buffer

FSK Rx Channel

System Clock 1

Rx 2
GMSK Demodulator

System Clock 2
AIS Burst

Synthesised System Clocks

HDLC/ NRZI Decoder

Message Buffer

Rx Channel 2

BIAS

Synthesiser 1
AIS Raw

AVDD

Analogue 2V5 regulator

Sample Timer

Interrupt Generator

Main Clock Digital PLL

Synthesiser System Connections

Boot Control

EEPROM SPI Port

Synthesiser 2

Xtal Clock

3.0 to 3.6 volt input

Interrupt

Xtal/Clock I/O

Boot Enable 1 and 2

SPI Port for FI Load

CMX7032 and CMX7042 (FI-1.x Congured) Functional Diagram

Built on FirmASIC technology Half-duplex GMSK and FSK capabilities Flexible signal channels - Two simultaneous Rx - One Tx AIS 25kHz channel - 9.6kbps GMSK with a BT of 0.4 and a modulation index of 0.5 Rx DSC - 1200Baud FSK with frequency modulation (1300Hz - 2100Hz) around a 1700Hz sub-carrier Rx/Tx AIS formatted data and raw data modes Rx DSC de-formatted data and raw data modes Sample Counter/Timer Limiter-Discriminator Rx interface Selectable I and Q or Two-Point Modulation Tx outputs Two auxiliary synthesised system clocks Two independent RF synthesisers (CMX7032) Conguration by Function Image le upload High performance GMSK encoding/decoding Supports Carrier-Sensing Channel Access (CSTDMA) Operation Supports Self Organising Time Domain Multiple Access (SOTDMA) operation C-BUS serial control interface Auxiliary ADC and DAC functions - 4 (10-bit) DACs - 2 x 2-Input MUX (10-bit) ADCs Message progress-reports to host Optimum co-channel and adjacent-channel performance Low-power (3.0 to 3.6 V) operation with Sleep and Dynamic powersave PE0001, PE0201 and PE0401 support for evaluation, experimentation and design-in Compact package styles Package Styles CMX7032L9 CMX7042L4 64 Lead LQFP 48 Lead LQFP CMX7032Q1 64 No-Leads VQFN CMX7042Q3 48 No-Leads VQFN

10-bit DAC

10-bit DAC

10-bit DAC

10-bit DAC

C-BUS Interface

Rx Inputs

FI-1.x
Series Variants This block diagram illustrates the functions available from the CMX7032 and CMX7042 ICs using Function Image 1.x. Functions in black are common to both products; functions in red on the diagram are specic to the CMX7032.

IOVDD

AVSS

CMX7032 AIS Rx-only Baseband Processor with RF Synthesisers (FI-2.x)

Congured by the AIS Rx-only Function Image (FI-2.x), the CMX7032 offers the core of a simple Automatic Identication System receiver. With its two separate on-chip GMSK-based receiver channels interfaced to a limiter-discriminator driven RF system, the CMX7032 will automatically demodulate and decode incoming baseband AIS signals, providing them separately at the Tx Data output as NMEA 0183 HS formatted data. Further peripheral support is provided by the ICs dual RF synthesisers and programmable clock generators. A dedicated enabling output is available to the system LNA control function. In addition, to enable a complete local-surface picture, provision is made to handle GPS data via the Rx Data input; processes are allocated to pass-through the (GPS) positional data when the IC is not busy with the AIS signal processing. Designed for stand-alone operation, this IC requires no host micro-controller: the conguration Function Image is loaded from a peripheral EEPROM. Provision is made to allow user conguration of the EEPROM contents prior to loading to the memory. Rx and Tx On-Chip Signal Paths Simultaneous Reception on Two AIS Channels Dual GMSK Demodulators Fixed Modulation Format Compatibilty: - AIS 25kHz Channels - GMSK: 9600bps, BT = 0.4, 2.4kHz Deviation Gain-adjustable Matching and Input Stages

VCO

CP1OUT Synth RF1 In

Ceramic Filter
EEPROM

Power and Control 3.0 to 3.6 Volt Low-Power Requirement - RFVDD: 2.25 to 2.7 Volts Full AIS Rx Data handling (HDLC and NRSI Decoding) Host-less Control: - Function Image (2.x) loaded from System EEPROM - User Conguration Options on Memory Contents GPS Pass-through Facility via Rx Data Input

Disc.

Xtal Filter

FM Discriminator (SA58640)

Rx1 In

Burst Detect
x2

Indicator (LED)

Auxiliary Functions External LNA Enable Port

LNA Enable
GPS Receiver

SAW Filter

LNA

SAW Filter

Splitter

19.2MHz Osc.

Xtal/Clock RxD

Two Integer-N RF Synthesisers - Minimal Reference Spurs for Low Phase-Noise - Charge Pump: High/Low Soft Selectable Current Setting Nominal Current is User Dened Synthesised System Clocks Valid AIS Burst Received Output (LED)

/2 x3

RS232 Driver

TxD
Chart Plotter or PDA or PC

Burst
Xtal Filter
FM Discriminator (SA58640)

CMX7032 (part)

Rx1 In

AIS Data Handling AIS Burst Mode with Full AIS Frame Formatting - NRSI Decoding - HDLC Processing - Training Sequence - System Flags - Bit De-stufng AIS and Raw Data Modes CRC Checking Supports Carrier Sensing (CSTDMA) Operations Four 160 Byte Rx Data Buffers - Automatic Storage of 4 x 5-Slot AIS Bursts (Two Per Channel)

Ceramic Filter

Disc.

RF2 In Synth
VCO

CP2OUT

CMX7032 (FI-2.x) Rx-only Peripheral Operations

CMX7032 AIS Rx-only Processor

DVDD
3.0 to 3.6 volt Input

LNA Enable

Features
Internal Systems Control

IOVDD DVSS VBIAS

Digital 2V5 Regulator

FI Configured Output

Bias Generator

Rx Data
Detector Buffer UART

Rx1

AIS GMSK Rx 1 GMSK Demodulator NRZI Decoder HDLC Decoder Message Buffer

Tx Data Burst Detected

NMEA-0183 Arbiter and Formatter
System Clock 1 System Clock 2

Rx Inputs

BIAS
MUX

Rx2

AIS GMSK Rx 2 GMSK Demodulator NRZI Decoder HDLC Decoder Message Buffer

Synthesised System Clocks

Built on FirmASIC technology AIS Rx-only Dual GMSK demodulators AIS data output in RS232 - NMEA 0183 HS format National Marine Electronics Association (NMEA) Optimum Rx co-channel performance Congurable by Function Image (FI-2.x) Automatic FI loading from EEPROM for host-less operation FI congured output for LNA operation Two RF synthesisers Two auxiliary system clock generators Limiter-Discriminator Rx interface PE0201 EvKit and DE70321 DemoKit support for evaluation, experimentation and development design-in Compact package styles

BIAS

Synthesiser 1

Main Clock Digital PLL

Synthesiser System Connections

Boot Control

AVDD

Analogue 2V5 regulator

EEPROM SPI Port

Synthesiser 2

Xtal Clock

Package Styles
Boot Enable 1 and 2 SPI Port for FI Load

3.0 to 3.6 volt input

Xtal/Clock I/O

CMX7032L9

64 Lead LQFP

FI-2.x

IOVDD

AVSS

CMX7032Q1 64 No-Leads VQFN

CMX7032 (FI-2.x Congured) Rx-only Functional Diagram

AIS New Fun Rx cti -on on ly I FI-2 ma ge .x

Evaluation and Demonstration Support

To facilitate evaluation and experimentation, and to reduce design time, the following pcb-based products are available for the evaluation of these AIS ICs: CMX910 CMX7032 CMX7042 CMX7032 EV9100 Evaluation Kit PE0201 Evaluation Kit and PE0001 Evaluation Kit Interface Card PE0401 Evaluation Kit and PE0001 Evaluation Kit Interface Card DE70321 AIS Rx/Tx and Rx-only Demonstration and Development Kit (offers downloadable design-support les)

EV9100 Evaluation Kit The EV9100 EvKit is available for the evaluation, experimentation and design-in of the CMX910 AIS Baseband Processor IC. Comprising a digital/analogue pcb with an on-board CMX910 device, the evkit provides access to the CMX910s baseband signal, control and data interfaces as well as its auxilliary ADC and DAC functions. The evkit also provides an FX604 FSK modem and associated circuitry to allow evaluation of the CMX910s external FSK interface. Target CMX910 IC On Board Auxiliary ADC and DAC Interface Digital/Analogue PCB with Low Noise Floor Differential and Single-ended Baseband Interface FX604 modem IC tted for Additional (DSC) Rx Channel C-BUS Serial Control and Data Interface 19.2MHz Device Clock On-board Access to all CMX910 Signals, Commands and Data Interfaces to RF Daughter-board with all Necessary Signals On-board Power Regulaton and Distribution

PE0201 Evaluation Kit The PE0201 Evaluation Kit is designed to assist in the evaluation and application development of the CMX703x range of FirmASIC products, in this case, the CMX7032. In the form of a populated PCB the PE0201 comprises a target IC, appropriate supporting components and circuitry, including an on-board 460MHz VCO operating in conjunction with one of the ICs on-chip synthesisers. Target CMX703x IC On Board Evaluates Both RF and Baseband Capabilities On-Board 460MHz VCO Command and Control by PC via the PE0001 EvKit Interface Card or by Users own C Development Application or Environment Socketed EEPROM Option for Function Image Operations In-circuit Serial Flash Programming On-board Access to all CMX703x Signals, Commands and Data On-board Regulators Operate from a Single 5 Volt Supply

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PE0401 Evaluation Kit The PE0401 Evaluation Kit is designed to assist in the evaluation and application development of the CMX704x range of FirmASIC products, in this case, the CMX7042. In the form of a populated PCB the PE0401 comprises a target IC complete with appropriate supporting components and circuitry. Target CMX704x IC On Board Command and Control by PC via the PE0001 EvKit Interface Card or by Users own C Development Application or Environment Socketed EEPROM Option for Function Image Operations In-circuit Serial Flash Programming On-board Access to all CMX703x Signals, Commands and Data On-board Regulators Operate from a Single 5 Volt Supply

PE0001 Evaluation Kit Interface Card The PE0001 EvKit Interface Card is a global interface system for use with evaluation kits for CMLs new generation ICs, including products based on FirmASIC technology. Supplied with a PC GUI, and in the form of a populated PCB, the PE0001 provides a graphical way of addressing all of the relevant EvKits target ICs via the C-BUS interface. Global Interface Card for CMLs New Generation IC Evaluation Kits C-BUS Read, Write and Reset Operations to Target IC 8051 Controller Based Operation Physical Mating Interface for Wide Range of Target EvKit Boards Power Drawn from Target EvKit or Standalone PC GUI, Firmware and Hardware Provided - Updates available from CML website Function Image Handling for FirmASIC -based Projects 4Mbit of Re-programmable Flash Memory PC Control and Communications via RS232 Interface

DE70321 AIS Demonstration, Evaluation and Development Kit The DE70321 DemoKit is a complete AIS Class B (IEC 62287) technology demonstrator aimed at speeding manufacturers design and development of AIS Class B transponders and AIS receiver products using the CMX7032 AIS Class B Baseband Processor with RF Synthesisers IC. This compact PCB-based product measures 100mm x 112.5mm. This design is a exible platform to allow users to congure and evaluate with two build options: Class B Transceiver (using CMX7032 FI-1.x) Dual Channel Rx-only (using CMX7032 FI-2.x) Shipped Pre-loaded with FI-2.x - Dual Rx-only Demonstrator A Complete Bill of Materials (BOM) Layout Schematics Design Files

Further Design Support is available from the My CML Technical Portal:

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Device Conguration

The operational set-up of each product is carried out at the initial power-up of the IC.

The CMX910 requires the uploading of a small conguration data le. The CMX7032 and CMX7042 (FI-1.x) FirmASIC products require the uploading of the relevant Function Image data le from either the host C or attendant EEPROM.

Host Controller [1]

FLASH Memory

The CMX7032 (FI-2.x) FirmASIC product only requires the uploading of the relevant Function Image data le from an attendant EEPROM. EEPROM contents may be customised prior to loading to the memory.
Function Image Data File
TM

Full instructions for these processes are given in the ICs datasheet; the required data les are available from the MyCML technical portal on the CML website.
Bias

Reg.

Function Images (CMX7032 and CMX7042) Data Files for IC Conguration Downloadable from My CML Technical Portal Loaded to IC at Power-Up Loaded from C via C-BUS[1] or On-Board EEPROM[2]

Optional EEPROM [2]

EEPROM SPI Port

Boot Control

Xtal Oscillator

C-BUS Interface
Registers

Main Clock Digital PLL

Power Control
Internal Systems Control

CMX7032 and CMX7042 Function Image File Handling Arrangements

C-BUS

Infinite Capabilities . . .

FirmASIC

The CMX7032 and CMX7042 products are built on CMLs FirmASIC technology. CMLs proprietary FirmASIC component technology reduces cost, time to market and development risk, with increased exibility for the designer and end application. FirmASIC combines Analogue, . . . Maximum Flexibility Digital, Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family. Specic functions of a FirmASIC device are determined by uploading its Function Image during device initialisation. New Function Images may be later provided to supplement and enhance device functions, expanding or modifying end-product features without the need for expensive and time-consuming design changes. FirmASIC devices provide signicant time to market and commercial benets over Custom ASIC, Structured ASIC, FPGA and DSP solutions. They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specic Standard Products (ASSPs).

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Design Resources
Design and application support is available from: www.cmlmicro.com/

COMMUNICATION SEMICONDUCTORS

Shanghai Tel: +86 21 63174107 and +86 21 63178916 Fax: +86 21 63170243 [email protected] www.cmlmicro.com A CML Microsystems Plc Company 2007 CML Microcircuits

Technical Datasheets My CML Technical Portal Function Image File Downloads Application Notes Evaluation and Development Kits AIS Class B Transceiver Reference Design Files Frequently Asked Questions Application Support via Local Support Desks

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