1

ON-CHIP VARIATION ANALYSIS

USING PRIMETIME :-
A CASE STUDY
Sandeep Kolte
Sabeesh Balagangadharan
Vikas Mahendiyan
2
Agenda
What is OCV ?
Causes ?
Analysis using Primetime.
A Case study
lssue
Work Around.
Conclusion.
3
Introduction
What is OCV ?
On Chip Variation.
Delay variation due to PVT changes across the chip.
Why OCV Analysis?
To increase reliability
To Reduce yield issue.
To avoid post silicon surprise
4
Causes
Process
Difference in instruments from one fab to other fab .
Due to mask variations.
Etching variation.
Voltage
On board voltage supply.
Power line routing.
Temperature
Chip lR drop.
Wire self heating.
Other
EDA tools support.
PLL jitter.
5
Let`s Analyze the problem.
Side effects
Difference in timing correlation with the silicon.
Timing paths getting affected.
Single operating condition analysis Best case for Hold Check and worst
case for setup check not enough for the STA signoff.
What next ?
Need to account for the timing variance.
How ?
By adding the frequency margin for the setup.
By adding the uncertainty for the hold check.
But will affect all the path evenly irrespective the placement, logic,
clock paths etc.
On Chip analysis using the Primetime.
6
OCV using Primetime
- A case study.
Design Overview
ARM based SoC
Embedded ROM
0.15 micron four - layer metal technology
1.5 M gate-count, 300 K placeable instances
Six Clock domains.
Three Different Frequency ratios.
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OCV using Primetime
Primetime sets of commands/variables for the OCV analysis.
set_timing_derate [-min min_path_derate]
[-max max_path_derate] [-clock] [-data] [-net_delay]
[-cell_delay] [-cell_check]
set_operating_condition analysis_type on_chip_variation.
report_crpr [-from from_latch_clock_pin] [-to to_latch_clock_pin]
[-clock clock] [-type check]
timing_remove_clock_reconvergence_pessimism.
timing_clock_reconvergence_pessimism.
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Apply derating factor
Eg. Applying the 12 % OCV.
set_derate_timing -clock min 0.88 max 1.12
For Hold Check
Clock to the destination register is made slower by 12%.
Clock to the launching register is made faster by 12%.
For Setup Check
Clock to the destination register is made faster by 12%.
Clock to the launching register is made slower by 12%.
OCV using Primetime
9
OCV using Primetime
Consider Example
D
Q
ll1
cts1
cts2
cts3
cts+
U
D
Q
ll2
D
Q
ll3
in2
in3
in1
clk
out2
out1
U9
U8
10
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: min
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.011 * 0.011 r
cts1/Y (CTS) 0.300 * 0.311 r
cts2/A (CTS) 0.011 * 0.322 r
cts2/Y (CTS) 0.300 * 0.622 r
FF1/CLK (DFF) 0.012 * 0.634 r
FF1/Q (DFF) 0.186 * 0.820 r
U9/A (AND) 0.010 * 0.830 r
U9/Y (AND) 0.079 * 0.909 r
U8/B (AND) 0.012 * 0.921 r
U8/Y (AND) 0.070 * 0.991 r
FF2/D (DFF) 0.011 * 1.002 r
data arrival time 1.002
Hold Check without OCV
11
Hold Check without OCV
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.011 * 0.011 r
cts1/Y (CTS) 0.300 * 0.311 r
cts2/A (CTS) 0.011 * 0.322 r
cts2/Y (CTS) 0.300 * 0.622 r
cts3/A (CTS) 0.020 * 0.642 r
cts3/Y (CTS) 0.300 * 0.942 r
FF2/CLK (DFF) 0.010 * 0.952 r
clock reconvergence pessimism 0.000 0.952
FF2/CLK (DFF) 0.952 r
library hold time 0.026 * 0.978
data required time 0.978
---------------------------------------------------------------
data required time 0.978
data arrival time -1.002
---------------------------------------------------------------
slack (MET) 0.024
12
Hold Check with OCV
Hold Report after applying 12% derating for the only clock.
set_timing_derate clock min 0.88 max 1.12
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: min
Min Clock Paths Derating Factor : 0.880
Max Clock Paths Derating Factor : 1.120
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.010 * 0.010 r
cts1/Y (CTS) 0.264 * 0.274 r
cts2/A (CTS) 0.010 * 0.283 r
cts2/Y (CTS) 0.264 * 0.547 r
FF1/CLK (DFF) 0.011 * 0.558 r
FF1/Q (DFF) 0.186 * 0.744 r
U9/A (AND) 0.010 * 0.754 r
U9/Y (AND) 0.079 * 0.833 r
U8/B (AND) 0.012 * 0.845 r
13
Hold Check with OCV
U8/Y (AND) 0.070 * 0.915 r
FF2/D (DFF) 0.011 * 0.926 r
data arrival time 0.926
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.012 * 0.012 r
cts1/Y (CTS) 0.336 * 0.348 r
cts2/A (CTS) 0.012 * 0.361 r
cts2/Y (CTS) 0.336 * 0.697 r
cts3/A (CTS) 0.022 * 0.719 r
cts3/Y (CTS) 0.336 * 1.055 r
FF2/CLK (DFF) 0.011 * 1.066 r
FF2/CLK (DFF) 1.066 r
library hold time 0.026 * 1.092
data required time 1.092
---------------------------------------------------------------
data required time 1.092
data arrival time -0.926
---------------------------------------------------------------
slack (VIOLATED) -0.166
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OCV using Primetime
Analysis of Pessimism added due to clock derating.
CTS1 and CTS2 are common cells in the clock network paths.
Should not be having different delay at the same time.
Need to remove this extra added pessimism.
Use CRPR variable.
Let's Consider only cell delay for analysis purpose.
0.300 ns
0.300 ns
0.300 ns
Delay
without
derating
0.300 ns
0.300 ns
Delay
without
derating
CTS3
CTS2
CTS1
Clock
Path for
FF2
0.336 ns
0.336 ns 0.264 ns CTS2
0.336 ns 0.264 ns CTS1
Delay with
derating
Delay with
derating
Clock Path
FF1
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What is CRPR ?
CRPR is to remove the derating factor applied on the common
clock path.
This is to reduce the pessimistic approach applied by the
different delay assumed for the same timing arc for network
delay calculation.
set timing_remove_clock_reconvergance_pessimism true
Default set to false.
Other variable
set timing_crpr_threshold_ps 20
To remove the pessimism on opposite edges.
set timing_clock_reconvergence_pessimism same_transition.
Default is set to true.
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Hold Check with OCV and
CRPR enable
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: min
Min Clock Paths Derating Factor : 0.880
Max Clock Paths Derating Factor : 1.120
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.010 * 0.010 r
cts1/Y (CTS) 0.264 * 0.274 r
cts2/A (CTS) 0.010 * 0.283 r
cts2/Y (CTS) 0.264 * 0.547 r
FF1/CLK (DFF) 0.011 * 0.558 r
FF1/Q (DFF) 0.186 * 0.744 r
U9/A (AND) 0.010 * 0.754 r
U9/Y (AND) 0.079 * 0.833 r
U8/B (AND) 0.012 * 0.845 r
U8/Y (AND) 0.070 * 0.915 r
FF2/D (DFF) 0.011 * 0.926 r
data arrival time 0.926
17
Hold Check with OCV and
CRPR enable
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTSB) 0.012 * 0.012 r
cts1/Y (CTSB) 0.336 * 0.348 r
cts2/A (CTSB) 0.012 * 0.361 r
cts2/Y (CTSB) 0.336 * 0.697 r
cts3/A (CTSB) 0.022 * 0.719 r
cts3/Y (CTSB) 0.336 * 1.055 r
FF2/CLK (DFF) 0.011 * 1.066 r
clock reconvergence pessimism -0.149 0.917
FF2/CLK (DFF) 0.917 r
library hold time 0.026 * 0.943
data required time 0.943
---------------------------------------------------------------
data required time 0.943
data arrival time -0.926
---------------------------------------------------------------
slack (VIOLATED) -0.017
18
Clock network delay with OCV enable.
Final pessimism added.
OCV using Primetime
0.336 ns
0.336 ns
0.336 ns
DeIay
with
derating
0.264 ns
0.264 ns
DeIay
with
derating
0.300 ns
0.300 ns
0.300 ns
DeIay
without
derating
0.300 ns
0.300 ns
DeIay
without
derating
CTS3
CTS2
CTS1
CIock
Path
for FF2
0.336 ns
0.300 ns 0.300
ns
CTS2
0.300 ns 0.300
ns
CTS1
CRPR
enabIe
CRPR
enabIe
CIock
Path FF1
-0.166 ns
with cIock
derating
0.024 ns
without
derating
-0.017 ns VlOL
CRPR enabIe
19
OCV using Primetime
Sufficient pessimism got added.
Pessimism added proportional to the clock network latency.
More accurate than specifying the common uncertainty to all the clocks.
Take care of cell placement and net routing into account.
TCL script can be used for further optimization in the design
compiler or physical compiler.
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Is it an Issue ?
Wrong CRPR calculation while OCV using Primetime version
T-2002.09
lnability in tracing full common clock network path.
lssue when the clock is getting diverted to multiple places.
For the start and end register having same clock path till end is
traced properly.
21
OCV using Primetime
Consider Example 2.
D
Q
ll1
cts1
cts2
cts3
cts+
U1
D
Q
ll2
D
Q
ll3
in2
in3
in1
clk
out2
out1
clkn
in3
U2
U3
U3
in+
U+
'LYHUJHQFH SW.
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Hold Check for Ex2.
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: min
Min Clock Paths Derating Factor : 0.880
Max Clock Paths Derating Factor : 1.120
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.009 * 0.009 r
cts1/Y (CTS) 0.264 * 0.273 r
U4/A (MUX) 0.009 * 0.282 r
U4/Y (MUX) 0.168 * 0.450 r
U5/A (AND) 0.008 * 0.458 r
U5/Y (AND) 0.071 * 0.529 r
FF1/CLK (DFF) 0.011 * 0.539 r
FF1/Q (DFF) 0.106 * 0.645 r
U2/A (AND) 0.014 * 0.659 r
U2/Y (AND) 0.056 * 0.715 r
U3/A (AND) 0.015 * 0.730 r
U3/Y (AND) 0.049 * 0.779 r
FF2/D (DFF) 0.010 * 0.789 r
data arrival time 0.789
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Hold Check for Ex2.
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTSB) 0.011 * 0.011 r
cts1/Y (CTSB) 0.336 * 0.347 r
U4/A (MUX) 0.011 * 0.358 r
U4/Y (MUX) 0.214 * 0.572 r
U5/A (AND) 0.010 * 0.582 r
U5/Y (AND) 0.091 * 0.673 r
cts3/A (CTS) 0.011 * 0.684 r
cts3/Y (CTS) 0.336 * 1.020 r
FF2/CLK (DFF) 0.011 * 1.032 r
clock reconvergence pessimism -0.124 0.908
FF2/CLK (DFF) 0.908 r
library hold time 0.030 * 0.938
data required time 0.938
---------------------------------------------------------------
data required time 0.938
data arrival time -0.789
---------------------------------------------------------------
slack (VIOLATED) -0.149
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Hold Check for Ex2.
Using report_crpr command to get the common network path
report_crpr from FF1/CLK to FF2/CLK type hold clock CLK
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Common Point: U5/A
Common Clock: CLK
Launching edge at common point: RISING
Capturing edge at common point: RISING
Arrival times at common point Early Late CRP
---------------------------------------------------------------
Rise 0.46 0.58 0.12
Fall 0.46 0.57 0.11
---------------------------------------------------------------
clock reconvergence pessimism 0.12
Not tracing common path completely.
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Work Around.
Selectively disabling the divergence point.
i.e. set_disable_timing U1/A
New Report after disabling the path,
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: min
Min Clock Paths Derating Factor : 0.880
Max Clock Paths Derating Factor : 1.120
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTSB) 0.009 * 0.009 r
cts1/Y (CTSB) 0.264 * 0.273 r
U4/A (MUX) 0.009 * 0.282 r
U4/Y (MUX) 0.168 * 0.450 r
U5/A (AND) 0.008 * 0.458 r
U5/Y (AND) 0.071 * 0.529 r
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Work Around.
FF1/CLK (DFF) 0.011 * 0.539 r
FF1/Q (DFF) 0.106 * 0.645 r
U2/A (AND) 0.014 * 0.659 r
U2/Y (AND) 0.056 * 0.715 r
U3/A (AND) 0.015 * 0.730 r
U3/Y (AND) 0.049 * 0.779 r
FF2/D (DFF) 0.010 * 0.789 r
data arrival time 0.789
clock CLK (rise edge) 0.000 0.000
clock source latency 0.000 0.000
CLK (in) 0.000 0.000 r
cts1/A (CTS) 0.011 * 0.011 r
cts1/Y (CTS) 0.336 * 0.347 r
U4/A (MUX) 0.011 * 0.358 r
U4/Y (MUX) 0.214 * 0.572 r
U5/A (AND) 0.010 * 0.582 r
U5/Y (AND) 0.091 * 0.673 r
cts3/A (CTS) 0.011 * 0.684 r
cts3/Y (CTS) 0.336 * 1.020 r
FF2/CLK (DFF) 0.011 * 1.032 r
clock reconvergence pessimism -0.144 0.887
FF2/CLK (DTN12) 0.887 r
library hold time 0.030 * 0.917
data required time 0.917
---------------------------------------------------------------
data required time 0.917
data arrival time -0.789
---------------------------------------------------------------
slack (VIOLATED) -0.128
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Work Around.
After disabling diverging point.
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by CLK)
Common Point: U5/Y
Common Clock: CLK
Launching edge at common point: RISING
Capturing edge at common point: RISING
Arrival times at common point Early Late CRP
---------------------------------------------------------------
Rise 0.50 0.64 0.14
Fall 0.50 0.63 0.14
---------------------------------------------------------------
clock reconvergence pessimism 0.14
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Case Study
Data for one of the Clock domain.
0
50
100
150
200
250
300
0.3-0.2 0.2-0.1 0.1-0
Before
After
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Conclusion
lrrespective of liking, OCV analysis is a must to get your chip to
market.
Easy and Efficient way to take care of almost all the variation.
One issue with tool, But work around available thanks to
Synopsys support group.