Static Timing Analysis

Selva Kumar R. [email protected]

Overview
Even though a digital circuit may be logically correct, one needs to know how it will perform on physical implementation Timing analysis is required To meet a performance specification To evaluate how the design operates Timing Analysis : Point-point analysis of design without stimulus vectors
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Session Topics
Timing Paths Clock Skew Timing Constraints Slack

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Timing Analysis
A N bit input design to be verified completely requires a 2N test patterns The approach of generating 2N patterns and applying them at different time & sequence is impractical The complexity of analysis of netlist is reduced by breaking the process into two steps One of functional verification Other of timing Verification The process of verifying the netlist through test benches and test patterns after P&R is known as Dynamic Timing Analysis Requires input from user / verification engineer
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Dynamic Timing Analysis

Dynamic timing analysis / simulation guarantees 100% coverage Though this guarantee comes at a cost of time
Time of generation of patterns Time of application of patterns etc

It is design specific One method cannot be used to all designs Hence for each design a unique test bench needs to be created A generalized approach is required so that verification process is speeded up
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STA What is Static Timing Analysis?

Static Timing Analysis is a method of calculating the expected timing of a digital circuit without requiring simulation. STA is method of analyzing and validating the timing performance of a design.
Advantages: Much faster than gate-level simulation. Exhaustive Proper circuit functionality is not checked. Vector generation NOT required.
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What is Timing Analysis?

D Data QB Clk Q Output OutputBar

What are our circuit timing requirements?

Clk 0 Data 100 200 300 400 500

Setup Requirement Hold Requirement Data Cannot Change Within These Windows
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Timing Terminologies
Setup Time : Time for which data should be stable at the input of the ff before the arrival of clock (active edge) at the ffs clock pin Hold Time : Time for which data should be stable at the input of the ff after the arrival of clock (active edge) at the ffs clock pin

THOLD TSETUP
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Metastability
For any flop to work its setup time and hold time requirements should be met

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STA Process
STA happens in three steps Circuit is broken down to sets of timing paths Delay of each path is calculated Path delays are checked to see if timing constraints have been met

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Timing Paths
Timing refers to the time taken by data to travel from one point to the other The point at which data is expected to originate is considered a start point
Input Port Clock Pin of sequential elements

The location at which data considered as the stop point

Output Port Data Pin of sequential elements
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terminates

is

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Three Steps in Timing Analysis

Circuit is broken down into sets of timing paths. Delay of each path is calculated. Path delays are checked to see if timing constraints have been met.

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What is a Timing Path?

A Timing Path is a point-to-point path in a design which can propagate data from one flip-flop to another. Each path has a startpoint and an endpoint Startpoints: Input ports, Clock pins of flip-flops Endpoints: Output ports, Data input pins of flip-flops
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Timing Terminologies
Critical Path : Theoretically path which has maximum delay Arrival Time : Time taken by data to reach a end point from a specific start point. Depends on complexity of logic through which data traverses Required Time : Time at which data is required at a particular end point. Depends on the requirements / specifications Slack : Difference in required time and arrival time. For a design to work the slack value should always be positive
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Timing Paths
Depending on the logic through which data propogates a design can be considered to comprise of 4 paths

input > reg : Data from Input port to the first flip-flop reg > reg : Data from one flip-flop to another ff reg > out : Data from last flip-flop to output port input > output : Data from Input Output with no
sequential components in between

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Timing paths
Input Reg Reg Input -> -> -> -> Reg Reg Output Output

Input / Output also called as Pad / Pin Reg can be any of - flop, latch, RAM etc Reg also called as clock / setup
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Input > Reg

Path which starts at any input port and ends at the data pin of any sequential element that is first encountered Is controlled by the capture clock Data may start independently but must reach the sequential element before clock reaches the element

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Reg > Reg

Path which starts at the clock pin of a ff or enable pin of latch and ends at the data pin of any sequential element that is next encountered

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Reg > Reg

Path which starts at the clock pin of a ff or enable pin of latch and ends at the data pin of any sequential element that is next encountered Is controlled by both the launch as well as capture clock Data leaves the first sequential element on the clock and then races forward to reach the next sequential element before clock / enable reaches the element

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Reg > Out

Path which starts at the clock pin of a ff or enable pin of latch and ends at the output port of the design Clock launches the data after which data runs uncontrolled

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Input > Output

Path which starts at any input port and ends at any output port without traversing through any sequential element Clock has no role to play in this path Is seen mainly in purely combinational circuits practically rare in designs

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Timing Paths Example

How many start points are there in the circuit How many end points are there in the circuit How many paths are there in the circuit

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Anatomy Of A Sequential Path

Flip Flop

Combinational Logic

Flip Flop

Tclock-to-Q

Tlogic

Tsetup

One clock cycle

Tcycle = Tclock to Q + Tcombo + Tsetup

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Propagation Delay
Delay of a cell depends on many factors such as
Operating Conditions Functionality of the cell Type of Inputs

Based on the factors above a cell can propagate data either quickly or slowly Depending on the kind of analysis being done at any point of time one needs to consider either minimum delays or maximum delays

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Real world effects

All parameters vary based on PVT which stands for Process, Voltage, Temperature. Higher voltage usually speeds things up. Higher temperature usually slows things down. Process variation is more difficult to quantify. Most datasheets specify maximum delays.

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Delay Types
Assume the and gate shown below has a maximum delay of 3 ns at max operating conditions and for a 0-1 transition Let the and gate have a delay of 0.6 ns at minimum operating conditions and for a 1-0 transition Which is the delay to be considered for analysis?

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Clock Skew
Clock feeds multimillion flip-flops Theoretically clock should arrive at same instance at all flip-flops Practically impossible

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Clock Skew

Clock Skew: The maximum difference in arrival time of the clock signal to each register in the design

Clock arrival time at 1.1ns clock Skew = 1.3ns - 1.1ns = .2ns

Clock arrival time at 1.3ns

It is also defined as the difference in time that a single clock signal

takes to reach two different registers.

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Clock Skew
Variation in arrival of clock at clock pin of subsequent / consecutive flip-flops is known as skew

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Clock Jitter
The difference in arrival of clock at different flip-flops could be due to Jitter cycle to cycle variation in clock period
due to aging of oscillator, anomalies in the pll etc

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Clock Skew
Skew can be considered to be of two types When clock arrives earlier than expected
generally known as negative skew When clock arrives later than expected generally known as positive skew

+ve skew can occur when data & clock travel in same direction -ve skew can occur when data & clock travel in opposite directions
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Positive & Negative Skew

In CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay (b) Negative skew R2 D Q tCLK2 delay R3 D Q tCLK3 CLK Combinational Logic R2 D Q tCLK2 delay Combinational Logic R3 D Q tCLK3

In

Combinational Logic

Combinational Logic

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Positive Skew
TCLK + CLK1 1 CLK2 T CLK 3

2 + th

+ve skew Tclk + >= tcq1 + tcombo + t su2 (th2 + ) < tcq1 + tcombo Launching edge arrives before the receiving edge

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Negative Skew
TCLK - CLK1 1 TCLK 3

CLK2

-ve skew Tclk - >= tcq1 + tcombo + t su2 (th2 - ) < tcq1 + tcombo Receiving edge arrives before the launching edge

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Timing Terminologies
Critical Path Theoretically path which has maximum delay Arrival Time : Time taken by data to reach a particular end point from a specific start point. Depends on complexity of logic through which data traverses Required Time : Time at which data is required at a particular end point. Depends on the requirements / specifications Slack : Difference in required time and arrival time. For a design to work the slack value should always be positive :

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Maximum Frequency
For a circuit to meet its specifications the minimum time period or maximum frequency at which it works should be identified The frequency of operation of a circuit depends on the logic of the paths Each of the four kinds of paths have different required times

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Frequency Calculations

Arrival Time = TCOMBO, Max Required Time = TCP + TClock_Delay - TSETUP

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Frequency Calculations

Arrival Time : TClk-Q + TCombo, MAX Required Time = TCP + TClock_Skew - TSETUP
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Frequency Calculations

Arrival Time : TCombo, MAX Required Time : Explicit Timing Constraint (If Specified)
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Frequency Calculations

Arrival Time = TClk-Q + TCombo, MAX Required Time = Explicit Timing Constraint (If Specified)

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Problem 1
Find The maximum Frequency for the circuit shown in figure below

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Solution Methodology
Step One : Find the total number of paths in the design Step Two : Identify the paths that are constrained by clock Step Three : Identify the arrival times of all the paths identified in step 2 above Step Four : Identify the required time equations of all paths identified in step 2 Step Five : Equate the arrival times and required times of all relevant paths to obtain the time periods Step Six : Select the maximum applicable clock frequency from the clocks identified in step 5

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Solution
Three paths in the design
Input Reg Reg Reg Reg Out

Reg Out path not constrained hence can be discarded for timing calculation Relevant Paths are Input Reg and Reg Reg Input Reg Path
Arrival Time = 3 Required Time = CP + 0.5 + 0.6 -Tsetup= CP + 1.1 0.65 Equating the 2, CP = 3 1.1 + 0.65 = 2.55
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Solution
Reg Reg Path
Arrival Time = 0.5 + 0.6 + 1.4 + 4 = 6.5 Required Time = 0.5 + 0.7 + 0.8 + CP 0.75 = CP +
1.25 Equating the two, CP = 6.5 1.25 = 5.25

Two time periods available from the calculations 5.25, 2.55. Though first path can work if clock time period is 5.25 the second path can not work if clock time period is 2.55 Hence the maximum clock frequency at which the circuit can work is 1/5.25
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Problem 2

Paths from Q1 to Q1: None Paths from Q1 to Q2: TW max tPDFF +tJKsu = 20 +10 = 30 ns TW max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns Paths from Q2 to Q1: TW max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns Paths from Q2 to Q2: TW max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns

TW 47 ns
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Problem 3
Find the maximum applicable clock frequency for the circuit shown in figure below

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Problem 4
For the circuit shown in figure below find the maximum applicable clock frequency

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Problem 5
For the circuit shown in figure below find the maximum applicable clock frequency

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Failure / Data loss Due To Large Skew

A Ain
Flip Flop

B Aout Combinational Logic Bin

Flip Flop

clk delay

If new data (Ain) gets to point B before clock does, system will fail by simply skipping over old data For this illustration - ignore tsetup
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Clock arrives at point A

A Ain
Flip Flop

B Aout Combinational Logic Bin

Flip Flop

clk delay

T = 0ns

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Data arrives at comb logic input

A Ain
Flip Flop

B Aout Combinational Logic Bin

Flip Flop

clk delay

T = tclk-to-Q

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Data Exits Comb Logic

A Ain
Flip Flop

Aout

Combinational Logic

B new Bin Flip Bin

Flop

clk delay

T = tclk-to-Q + tlogic

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Clock Reaches B
A Ain
Flip Flop

Aout

Combinational Logic

B new Bin Flip Bin

Flop

clk delay

T = tclk-to-Q + tlogic

T = t

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Failure!!!
A Ain
Flip Flop

Aout

Combinational Logic

B new Bin Flip Bin

Flop

New Bin

clk delay

What happened to old Bin??? If tclk-to-Q+tlogic < t it fails

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Example 1
D Q

CK

TW max tPFF + tsu

For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns
TW max (max tPLH + tsu, max tPHL + tsu) TW max (25+20, 40+20) = 60
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Example 2
D Q

CK

TW max tPFF + max tPINV + tsu

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Example 3
0

D Q Q

Q0

MUX
1

D Q

Q1

CK

TW max tPFF + max tPMUX + tsu

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False paths Paths that physically exist in a design but are not
logic/functional paths These paths never get sensitized under any input conditions
Mux 1 A B1 B B2 C C1 C2 Mux 2 OUT

Total 4 timing paths PATH 1 A-C-C1-C2-OUT PATH 2 A-C-OUT PATH 3 B-B1-B2-C-C1-C2-OUT PATH 4 B-B1-B2-C-OUT Only path1 and 4 above are valid logic paths as select line for the 2 muxes are the same

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Multicycle Path
Multicycle paths are paths which intentionally require more than one clock cycle to propagate. This information cannot possibly be inferred by the timing tool, so it must be specified by the designer so the analyzer can mark the path and correctly compute the timing. A start point, end point and/or "through" point is specified, along with the number of allowed clock cycles.

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