San Jos State University Department of Electrical Engineering EE118, Digital Design I, Section 01, Fall 2011

Instructor: Office Location: Telephone: Email: Office Hours: Class Days/Time: Classroom: Prerequisites: Chang Choo ENG253 (408) 924-3980 [Link]@[Link] M,W, 9:30am-10:30am, T, 9:30am-12pm M,W, 10:30am-11:45am ENG341 EE98

Course Description Boolean algebra and number systems. Combinational and sequential circuits. Realization of logic blocks with standard integrated circuit packages. Design of counters, dividers, registers, arithmetic logic units and algorithmic state machines. Course Goals and Student Learning Objectives To provide a thorough background, at the introductory level, of the logical (mathematical) and electrical basis for digital system design. Major building blocks for designing digital systems will be examined and used which include gates, MUXes, DEMUXes, decoders, encoders, comparators, various arithmetic blocks, flip-flops, counters, registers, RAMs/ROMs, PLDs and FPGAs. Students will also learn to design digital circuits using schematic and Hardware Description Language (HDL), particularly, Verilog. This course is the gateway to all other digital system courses in the curriculum.

GE/SJSU Studies Learning Outcomes (LO), if applicable

LO1. Demonstrate an understanding of the fundamentals of Electrical Engineering, including its mathematical and scientific principles, analysis and design.

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LO2

Demonstrate the ability to apply the practice of Engineering in real-world problems.

Course Content Learning Outcomes Upon successful completion of this course, students will be able to: LO3. The ability to understand the number system, including binary, octal and hexadecimal numbers, and 2s complement number representation. LO4. The ability to understand Boolean algebra and to apply various Boolean theorems to prove Boolean identities and to simplify Boolean functions. LO5. The ability to understand the transistor-level structure of TTL and CMOS logic gates and their electrical and timing characteristics. LO6. The ability to construct the K-map from a Boolean expression and to find the minimal SOP/POS forms. LO7. The ability to understand Quine-McCluskey algorithm, i.e., to construct the Q-M table, to perform matching iterations to find PIs, and to find essential PIs by either detecting dominance relations or using Patrick function to corresponding Boolean expression. LO8. The ability to design moderately complex arithmetic and logic circuits including carry lookahead adder, BCD adder, comparator, multiplier, and to evaluate the resulting performance in terms of gate count and propagation delay. LO9. The ability to understand the working of MSI devices including decoders, encoders, and multiplexers, and to design various logic circuits using them. LO10. The ability to analyze cross-coupled gates and to identify any metastability. LO11. The ability to understand the behavior, timing issues, and internal structure of various flip-flops (RS, JK, D and T) and registers. LO12. The ability to identify and prevent various hazard and timing problems. LO13. The ability to analyze and design various flip-flop-based state machines (synchronous sequential circuits), including counters and one-hot controller. LO14. The ability to understand how PLA, ROM, and modern FPGA work and how to use them to design complex logic circuits. LO15. The ability to understand the basics of HDL language, to write a HDL program for various logic circuits and to test their functionality and timing.

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LO16. The ability to use CAD software, tools, and instruments to design, debug, test, and evaluate the performance of various logic circuits. LO17. The ability to work in a group. In the lab, students are typically divided into 2-person groups. All lab modules, except the final project, are group efforts graded as a team. LO18. The ability to prepare technical documents. There are a number of lab modules in this course. Students are required to submit a comprehensive lab report for each lab module. Lab reports are graded both for technical content and presentation.

ABET outcomes The letters in parentheses in each of the course learning objectives above refer to ABET (Accreditation Board for Engineering and Technology) criterion 3 outcomes satisfied by the objective. These are listed below as a reference:

Program objectives (a) an ability to apply knowledge of mathematics, science, and engineering (b) an ability to design and conduct experiments, as well as to analyze and interpret data (c) an ability to design a system, component, or process to meet desired needs (d) an ability to function on multi-disciplinary teams (e) an ability to identify, formulate, and solve engineering problems (f) an understanding of professional and ethical responsibility (g) an ability to communicate effectively (h) the broad education necessary to understand the impact of engineering solutions in a global and societal context (i) a recognition of the need for, and an ability to engage in life-long learning (j) a knowledge of contemporary issues (k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. (l) one or more technical specialties that meet the needs of Silicon Valley companies

Course learning objectives 1-15 15-16 1~7

Level of support Advanced Advanced Advanced Moderate Advanced Not supported Advanced Not supported Introductory Introductory Advanced Advanced

1~8

11,12

10 10 8 1~12

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Required Texts/Readings
Textbook

C.Y. Choo, Digital Logic Design, Manuscript, August 2011 (Draft 7.1). Available from Maple Press, 481 E. San Carlos St. between 10th and 11th St. (Tel:408-297-1000)

Other Readings

J.F. Wakerly, Digital Design: Principles and Practices, 4th ed., Prentice Hall, 2006 (A former textbook. A comprehensive textbook with many practical and advanced design problems). M.M. Mano, Digital Design, 3rd ed., Prentice Hall, 2002 (One of the student-friendly textbooks for its plain style). R.H. Katz, Contemporary Logic Design, Benjamin/Cummings, 1994 (One of former textbooks in SJSU). E.L. Johnson and M.A. Karim, Digital Design: A Pragmatic Approach, PWS-Kent, 1987 (Contains an excellent list of suggested readings for further study at the end of each chapter; out of print unfortunately). F. J. Hill and G. R. Peterson, Introduction to Switching Theory and Logical Design, 3rd ed., John Wiley & Sons, 1981 (A classical textbook. Your professors used this book when they were students.). Xilinx, ISE Student Edition 8.2i, Prentice Hall, 2006 (Xilinx schematic capture and simulation software; Lab PCs have this software installed, with Modelsim attached to the textbook; also may be downloaded from Xilinx website: [Link]

Classroom Protocol Students are expected to participate actively in class. Students will turn their cell phones off or put them on vibrate mode while in class. They will not answer their phones in class. Website Class information, notices, course materials, FAQs (selected course-related e-mails between students and instructors) will be posted on the web: [Link] In addition, all the changes on the tentative list of homework problems (see below), as well as solutions to homework, will be available on the web. Students are urged to visit the web site at least twice a week. Tutoring Session
Weekly tutoring sessions will be provided by Tutor (TBA). The sessions will be on Friday in IEEE Room.

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Laboratory
Students are required to take a laboratory section concurrently with the lecture. Administrative details of the laboratory will be given out by your lab instructor.

Dropping and Adding Students are responsible for understanding the policies and procedures about add/drops, academic renewal, etc. Information on add/drops are available at [Link] Information about late drop is available at [Link] . Students should be aware of the current deadlines and penalties for adding and dropping classes. Assignments and Grading Policy There are 3 midterm exams and a final exam. Exams cover the assigned reading materials and class lectures. There will be no make-up exams (only in very special circumstances, both written excuse and official proofs are required for extraordinary exams). Exam solutions will be discussed in class after the exam dates and posted on the web site of the course. Homework will be given as follows. Homework solutions will be posted on the website immediately after the due date.

HW No.
1 2 3 4 Exercise Problems 1.1, 1.6, 2.1, 9.2, 9.6, 9.8 (Show the truth table and find the output functions), 8.1, 8.3, 8.4, 8.5, 8.6 7.1, 7.2, 7.3, 9.1(1)(3) 5.1(1)(3)(6), 5.3, 6.1, 11.1, 11.3(1), 11.9(1)(2), 11.11(1)(2), 11.13(1)(2), 11.15, 11.16 3.1, 3.3, 3.5(1)(2), 3.6(1)(3), 4.1, 4.3, 13.1 (p.123), 13.3 (p.124), 14.2(1) (p.130), 14.3(1) (p.130), 19.1 (p.153), 19.3 (p.153), 39.1 (p.362), 39.3 (p.362) 21.1, 21.3(1)(2), 22.1, 23.1, 23.2 24.1, 24.4, 25.1, 25.2, 25.4, 25.5. 25.1, 25.2, 25.4, 25.5, 26.1, 26.2 27.1, 27.3, 27.13, 27.5, 27.6 40.1, 40.2, 28.2, 28.4, 28.5, 29.1

5 6 7 8 9 10

TBA
11

TBA

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Grades
Laboratory Three Midterms Final Homework 25% 15% each 25% 5%

All 3 midterm exams should be taken.

Grading Percentage Breakdown 90% and above 80% - 89% 70% - 79% 60% - 69% Below 60% A B C D F

University Policies
Academic integrity

Students should know that the Universitys Academic Integrity Policy is availabe at [Link] Your own commitment to learning, as evidenced by your enrollment at San Jose State University and the Universitys integrity policy, require you to be honest in all your academic course work. Faculty members are required to report all infractions to the office of Student Conduct and Ethical Development. The website for Student Conduct and Ethical Development is available at [Link] Instances of academic dishonesty will not be tolerated. Cheating on exams or plagiarism (presenting the work of another as your own, or the use of another persons ideas without giving proper credit) will result in a failing grade and sanctions by the University. For this class, all assignments are to be completed by the individual student unless otherwise specified. If you would like to include in your assignment any material you have submitted, or plan to submit for another class, please note that SJSUs Academic Policy F06-1 requires approval of instructors.
Campus Policy in Compliance with the American Disabilities Act

If you need course adaptations or accommodations because of a disability, or if you need to make special arrangements in case the building must be evacuated, please make an appointment with me as soon as possible, or see me during office hours. Presidential Directive 97-03 requires that students with disabilities requesting accommodations must register with the DRC (Disability Resource Center) to establish a record of their disability.

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EE Department honor code The Electrical Engineering Department will enforce the following Honor Code that must be read and accepted by all students. I have read the Honor Code and agree with its provisions. My continued enrollment in this course constitutes full acceptance of this code. I will NOT: Take an exam in place of someone else, or have someone take an exam in my place Give information or receive information from another person during an exam Use more reference material during an exam than is allowed by the instructor Obtain a copy of an exam prior to the time it is given Alter an exam after it has been graded and then return it to the instructor for regrading Leave the exam room without returning the exam to the instructor.
Measures Dealing with Occurrences of Cheating

Department policy mandates that the student or students involved in cheating will receive an F on that evaluation instrument (paper, exam, project, homework, etc.) and will be reported to the Department and the University. A students second offense in any course will result in a Department recommendation of suspension from the University.

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EE118: Digital Design I, Fall 2011, Class Schedule

Date

Topics

Textbook Homework Reading

Lab (Click
here to go to Lab page)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

8/24(W) Introduction 8/29(M) Binary Logic, ICs 8/31(W) Boolean Algebra I 9/7(W) Boolean Algebra II Combinational 9/12(M) Circuit Analysis 9/14(W) K-Map I 9/19(M) K-Map II Test I 9/21(W) Number Systems, 9/26(M) Binary Arithmetic 9/28(W) Hazards Introduction to 10/3(M) Verilog Comparators, 10/5(W) Multilevel Circuits 10/10(M) Decoder, Encoder 10/12(W) Multiplexer 10/17(M) Flip-Flops I 10/19(W) Flip-Flops II 10/24(M) Test II 10/26(W) Flip-Flops III Analysis of 10/31(M) Synchronous Sequential Circuits I Analysis of Synchronous Sequential Circuits II Counter Verilog for Sequential Circuits Parallel and Shift Registers Datapath & Controller Design I Test III Datapath & Controller Design II

Introduction; Lab A
Lab C

8-9 8-10 11 11 3-6

#1

#2 #3

Lab C (contd) Lab B

Lab D 14, 19, 13 39, 21, 22, 23 25 25 26

#4

Lab E

#5

Midterm
Lab F Lab G

#6 27 27

18

40

#7

11/2(W)
19 20 21

Lab G (contd)

11/7(M) 11/9(W) 11/14(M)

29 28 30

#8

Lab H

22

#9 30

Lab I

11/16(W) 11/21(M)
23

Lab J

11/23(W)

24 25
26 27

11/28(M) 11/30(W) 12/5(M) 12/7(W) 12/12(M)

RAM, ROM, Memory Decoding Circuits PLA, PLD, FPGA FPGA Architecture Review Final (0945-1200)

#10 #11

Lab Final