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PROGRAM - 1 REALIZATION OF LOGIC GATES Aim

To write a VHDL Code for realizing Gates AND, OR, NOT, NAND, NOR, XOR, XNOR and to verify the results.

:-

AND GATE
Program:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and2; architecture data_flow of and2 is begin c<=a and b; end data_flow; architecture behavioral of and2 is begin process(a,b) begin if a='1' and b='1' then c<='1';

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else c<='0'; end if; end process; end behavioral; architecture structural of and2 is component andx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end component; begin A1:andx port map(a,b,c); end structural; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end andx; architecture andx of andx is begin z<=x and y; end andx;

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OR GATE
Program:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end or2; architecture data_flow of or2 is begin c<=a or b; end data_flow; architecture behavioral of or2 is begin process(a,b) begin if a='0' and b='0' then c<='0'; else c<='1'; end if; end process; end behavioral; architecture structural of or2 is ASR COLLEGE OF ENGINEERING

component orx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end component; begin A1:orx port map(a,b,c); end structural; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end orx; architecture orx of orx is begin z<=x or y; end orx;

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NOT GATE
Program:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in STD_LOGIC;

b : out STD_LOGIC); end not1; architecture data_flow of not1 is begin b<=not a; end data_flow; architecture behavioral of not1 is begin process(a) begin if a='0' then b<='1'; else b<='0'; end if; end process; end behavioral;

architecture structural of not1 is ASR COLLEGE OF ENGINEERING

component notx is Port ( x : in STD_LOGIC; y : out STD_LOGIC); end component; begin A1:notx port map(a,b); end structural; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity notx is Port ( x : in STD_LOGIC; y : out STD_LOGIC); end notx; architecture notx of notx is begin y<=not x;

end notx;

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NAND GATE

Program:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nand2; architecture data_flow of nand2 is begin c<=a nand b; end data_flow; architecture behavioral of nand2 is begin process(a,b) begin if a='1' and b='1' then c<='0'; else c<='1'; end if; end process; ASR COLLEGE OF ENGINEERING

end behavioral; architecture structural of nand2 is component nandx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end component; begin A1:nandx port map(a,b,c); end structural;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nandx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end nandx; architecture nandx of nandx is begin z<=x nand y; end nandx;

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NOR GATE

Program:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nor2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nor2; architecture data_flow of nor2 is begin c<=a nor b; end data_flow; architecture behavioral of nor2 is begin process(a,b) begin if a='0' and b='0' then c<='1'; else c<='0'; end if; end process; ASR COLLEGE OF ENGINEERING

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end behavioral; architecture structural of nor2 is component norx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end component; begin A1:norx port map(a,b,c); end structural;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity norx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end norx; architecture norx of norx is begin z<=x nor y; end norx;

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XOR GATE

Program:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xor2; architecture data_flow of xor2 is begin c<=a xor b; end data_flow; architecture behavioral of xor2 is begin process(a,b) begin if a=b then c<='0'; else c<='1'; end if; end process; ASR COLLEGE OF ENGINEERING

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end behavioral; architecture structural of xor2 is component xorx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end component; begin A1:xorx port map(a,b,c); end structural;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end xorx; architecture xorx of xorx is begin z<=x xor y; end xorx;

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XNOR GATE

Program:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnor2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xnor2; architecture data_flow of xnor2 is begin c<=a xnor b; end data_flow; architecture behavioral of xnor2 is begin process(a,b) begin if a=b then c<='1'; else c<='0'; end if; ASR COLLEGE OF ENGINEERING

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end process; end behavioral; architecture structural of xnor2 is component xnorx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end component; begin A1:xnorx port map(a,b,c); end structural;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnorx is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end xnorx; architecture xnorx of xnorx is begin z<=x xnor y; end xnorx;

Result: Thus logic gates are implemented using VHDL

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PROGRAM-2 PARITY ENCODER

Aim:- To write a program for implementing parity encoder Apparatus:- 1. PC 2. XILINX SOFTWARE Program:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PARITY IS PORT ( DIN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); P : OUT STD_LOGIC); END PARITY; ARCHITECTURE BEHAVIORAL OF PARITY IS SIGNAL T: STD_LOGIC:='0'; BEGIN PROCESS (DIN,T) BEGIN T<=DIN (0); FOR I IN 1 TO 7 LOOP T<=T XOR DIN (I); END LOOP; P<=T; END PROCESS; END BEHAVIORAL;

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---The output wave form for the parity generator is shown in below

Result: Thus parity encoder was implemented using VHDL

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PROGRAM-3 SYNCHRONOUS RAM

Aim:- To write a program for implementing Synchronous RAM Apparatus:- 1. PC 2. XILINX SOFTWARE Program:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY RAM16X4 IS PORT(DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0); R_WRB,ENBAR:IN BIT; Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END RAM16X4; ARCHITECTURE BEH OF RAM16X4 IS TYPE TRAM IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL RAMDATA:TRAM; BEGIN PROCESS(R_WRB,ADDR,DATA,RAMDATA,ENBAR) BEGIN IF(ENBAR='0') THEN IF (R_WRB='0') THEN RAMDATA(CONV_INTEGER(ADDR))<=DATA; END IF;

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END IF;END PROCESS; PROCESS(R_WRB,ADDR,DATA,RAMDATA,ENBAR) BEGIN IF(ENBAR='0') THEN IF (R_WRB='1') THEN Q<=RAMDATA(CONV_INTEGER(ADDR)); ELSE Q<="ZZZZ"; END IF; END IF; END PROCESS; END BEH; --The output waveform for the Synchronous RAM is shown in below figure

Result: Thus synchronous RAM was implemented using VHDL

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PROGRAM-4 ALU
Aim:- To write a program for implementing ALU Apparatus:- 1. PC 2. XILINX SOFTWARE Program:Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; Entity ALU2 is Port ( S : in STD_LOGIC_VECTOR (2 downto 0); A,B : in STD_LOGIC_VECTOR (3 downto 0); F : out STD_LOGIC_VECTOR (3 downto 0)); End ENTITY ALU2; Architecture Behavioral of ALU2 is Begin PROCESS(S,A,B) BEGIN CASE S IS WHEN "000" =>F<=A AND B; WHEN "001" => F<=A OR B; WHEN "010"=> F<= NOT A; WHEN "011"=> F<= A XOR B; WHEN "100"=> F<=A+B;

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WHEN "101"=> F<=A-B; WHEN "110"=>F<=A+"0001"; WHEN "111"=> F<=A-"0001"; WHEN OTHERS => F<="0000"; END CASE; END PROCESS; End Behavioral; --The truth table for the 4-bit ALU is shown in below S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 OPEARATION AND OR NOT XOR ADDITION SUBTRACTION INCREMENT DECREMENT

----The output wave form for the ALU is shown in below

Result: Thus ALU was implemented using VHDL

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PROGRAM-5 TRAFFIC LIGHT CONTROLLER AND SEQUENTIAL LOGIC CIRCUITS

Aim:- To write a program for implementing traffic light controller and sequential logic circuits Apparatus:- 1. PC 2. XILINX SOFTWARE Program:Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity TRF is Port ( CLK,RST : in STD_LOGIC; RED,YELLOW,GREEN:OUT STD_LOGIC); End TRF; Architecture Behavioral of TRF is SIGNAL COUNT:INTEGER RANGE 0 TO 10:=0; SIGNAL STATE:INTEGER RANGE 0 TO 2:=0; Begin PROCESS (CLK,RST) BEGIN IF (RST='1') THEN STATE<=0; RED<='1'; GREEN<='0'; YELLOW<='0';

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COUNT<=0; ELSIF CLK'EVENT AND CLK='1' THEN CASE STATE IS WHEN 0=> IF (COUNT=5) THEN COUNT<=0; STATE<=1; ELSE COUNT<=(COUNT+1); RED<='1'; GREEN<='0'; YELLOW<='0'; END IF; WHEN 1=> IF (COUNT=5) THEN COUNT<=0; STATE<=2;

ELSE COUNT<=COUNT+1; RED<='0'; GREEN<='1'; YELLOW<='0'; END IF; WHEN 2=> IF (COUNT=2) THEN COUNT<=0;
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STATE<=0; ELSE COUNT<=COUNT+1; RED<='0'; GREEN<='0'; YELLOW<='1'; END IF; WHEN OTHERS=> STATE<=0; COUNT<=0; END CASE; END IF; END PROCESS; End Behavioral;

--The output wave form for the traffic light controller is shown in below

Result: Thus traffic light controller and sequential logic circuits was implemented using VHDL

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PROGRAM-6 PATTERN DETECTION USING MOORE MACHINE

Aim:- To write a program for implementing pattern detection using Moore machine Apparatus:- 1. PC 2. XILINX SOFTWARE Program:-

module moore(x,clk,rst, ab); input x,clk,rst; output [1:0] ab; reg [1:0] state; parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11; always @(posedge clk or negedge rst) if(~rst) state=s0; else case(state) s0: if(~x) state=s1; else state=s0; s1: if(x) state=s2; else state=s3;
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s2:

if(~x) state=s3; else state=s2;

s3:

if(~x) state=s0; else state=s3;

endcase assign ab=state; endmodule

---The output for the moore machine is shown in below

Result: Thus pattern detection using Moore machine was implemented using Verilog

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Part - B

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PROGRAM-1
FULL ADDER
Aim:- To write a program for implementing Full adder Apparatus:- 1. PC 2. XILINX SOFTWARE

Program:library IEEE; use IEEE.std_logic_1164.all; entity adder is port (a b : in std_logic; : in std_logic;

cin : in std_logic; sum : out std_logic; cout : out std_logic); end adder;

-- description of adder using concurrent signal assignments architecture rtl of adder is begin sum <= (a xor b) xor cin; cout <= (a and b) or (cin and a) or (cin and b); end rtl;

-- description of adder using component instantiation statements

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use work.gates.all; architecture structural of adder is signal xor1_out, and1_out, and2_out, or1_out : std_logic; begin xor1: xorg port map( in1 => a, in2 => b, out1 => xor1_out); xor2: xorg port map( in1 => xor1_out, in2 => cin, out1 => sum); and1: andg port map( in1 => a, in2 => b, out1 => and1_out); or1: org port map( in1 => a, in2 => b, out1 => or1_out); and2: andg port map( in1 => cin, in2 => or1_out, out1 => and2_out);

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or2: org port map( in1 => and1_out, in2 => and2_out, out1 => cout); end structural;

------------------------------------------------------------------------- N-bit adder -- The width of the adder is determined by generic N -----------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity adderN is generic(N : integer := 16); port (a : in std_logic_vector(N downto 1);

b : in std_logic_vector(N downto 1); cin : in std_logic; sum : out std_logic_vector(N downto 1); cout : out std_logic); end adderN;

-- structural implementation of the N-bit adder architecture structural of adderN is component adder port (a : in std_logic;

b : in std_logic;

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cin : in std_logic; sum : out std_logic; cout : out std_logic); end component;

signal carry : std_logic_vector(0 to N); begin carry(0) <= cin; cout <= carry(N);

-- instantiate a single-bit adder N times gen: for I in 1 to N generate add: adder port map( a => a(I), b => b(I), cin => carry(I - 1), sum => sum(I), cout => carry(I)); end generate; end structural;

-- behavioral implementation of the N-bit adder architecture behavioral of adderN is begin p1: process(a, b, cin) variable vsum : std_logic_vector(N downto 1);

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variable carry : std_logic; begin carry := cin; for i in 1 to N loop vsum(i) := (a(i) xor b(i)) xor carry; carry := (a(i) and b(i)) or (carry and (a(i) or b(i))); end loop; sum <= vsum; cout <= carry; end process p1; end behavioral;

Result:- Thus Full adder was implemented using VHDL

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PROGRAM-2
RS,D LATCH, COCK DIVIDER Aim:- To write a program for implementing RS,D LATCH, CLOCK DIVIDER Apparatus:- 1. PC 2. XILINX SOFTWARE Program:Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SR_Latch is Port ( S,R : in STD_LOGIC; Q : inout STD_LOGIC; Q_n : inout STD_LOGIC); end SR_Latch;

architecture SR_Latch_arch of SR_Latch is begin process (S,R,Q,Q_n) begin Q <= R NOR Q_n; Q_n <= S NOR Q; end process;

end SR_Latch_arch;

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-- The output wave form for the clock divider is shown in below figure

Dlatch :-

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity D_Latch is GENERIC (DELAY : time :=2 ns); Port ( Din : in STD_LOGIC; clock : in STD_LOGIC; Q : out STD_LOGIC; Q_n : out STD_LOGIC); end D_Latch;

architecture D_Latch_arch of D_Latch is signal Q_tmp:STD_LOGIC; begin PROCESS (Din,clock) BEGIN if (clock = '1') then
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Q_tmp <= Din after DELAY; end if; END PROCESS; Q <= Q_tmp; Q_n <= NOT Q_tmp; end D_Latch_arch;

Clock divider:Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity CLKDIV is GENERIC (N:POSITIVE:=8); Port ( CLK,RST : in STD_LOGIC; CLK_DIV : BUFFER STD_LOGIC); End CLKDIV; Architecture Behavioral of CLKDIV is Begin PROCESS (CLK,RST) VARIABLE COUNT:NATURAL; BEGIN IF RST='0' THEN COUNT:=0; CLK_DIV<='0'; ELSIF CLK'EVENT AND CLK='1' THEN

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COUNT:=COUNT+1; IF COUNT=N THEN CLK_DIV<=NOT CLK_DIV; COUNT:=0; END IF; END IF; END PROCESS; End Behavioral; -- The output wave form for the clock divider is shown in below figure

Result: Thus RS,D latch, clock divider was implemented using VHDL

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PROGRAM-3 STATIC AND DYNAMIC RAM

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PROGRAM-4
ROM
Aim:- To write a program for implementing ROM Apparatus:- 1. PC 2. XILINX SOFTWARE

Program:library ieee; use ieee.std_logic_1164.all;

entity ROM is port ( address : in std_logic_vector(3 downto 0); data : out std_logic_vector(7 downto 0) ); end entity ROM;

architecture behavioral of ROM is type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0); constant my_Rom : mem := ( 0 => "00000000", 1 => "00000001", 2 => "00000010", 3 => "00000011", 4 => "00000100", 5 => "11110000", 6 => "11110000", 7 => "11110000",

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8 => "11110000", 9 => "11110000", 10 => "11110000", 11 => "11110000", 12 => "11110000", 13 => "11110000", 14 => "11110000", 15 => "11110000"); begin process (address) begin case address is when "0000" => data <= my_rom(0); when "0001" => data <= my_rom(1); when "0010" => data <= my_rom(2); when "0011" => data <= my_rom(3); when "0100" => data <= my_rom(4); when "0101" => data <= my_rom(5); when "0110" => data <= my_rom(6); when "0111" => data <= my_rom(7); when "1000" => data <= my_rom(8); when "1001" => data <= my_rom(9); when "1010" => data <= my_rom(10); when "1011" => data <= my_rom(11); when "1100" => data <= my_rom(12); when "1101" => data <= my_rom(13);

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when "1110" => data <= my_rom(14); when "1111" => data <= my_rom(15); when others => data <= "00000000"; end case; end process; end architecture behavioral;

Result: Thus ROM was implemented using VHDL

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