In this lecture:

Lecture 7: Signed Numbers & • Representation of signed numbers

Arithmetic Circuits • Two’s complement
• Sign extension
Dr Pete Sedcole • Addition of signed numbers
Department of E&E Engineering • Multiplication by -1
Imperial College London • Multiplication and division by integer powers of 2
http://cas.ee.ic.ac.uk/~nps/
• Adder and subtractor circuits
(Floyd 2.5 – 2.7, 6.1 – 6.2, 6.4 – 6.6) • Comparators
(Tocci 6.1 – 6.5, 6.10 – 6.11, 9.1 – 9.2, 9.4) • Decoder
• Encoders

E1.2 Digital Electronics 1 7.1 6 November 2008 E1.2 Digital Electronics 1 7.2 6 November 2008

Review of binary representation Binary coded decimal revision

• We have already seen (in lecture 2) how to represent numbers in

binary • In BCD, each digit of a decimal number is coded using
• Review example: 4-bit binary
(179)10 = (10110011)2 = (B3)16 = (263)8 • The 4-bit binary words are then joined
• Example: (987)10
hex: 1011 0011 9 1001
B 3
8 1000
7 0111
octal: 10 110 011
2 6 3 • So 987 in decimal becomes 1001 1000 0111 in BCD

E1.2 Digital Electronics 1 7.3 6 November 2008 E1.2 Digital Electronics 1 7.4 6 November 2008
 Summary The basics of signed numbers
Decimal Binary HEX BCD Octal • So far, the numbers are assumed to be positive
0 00000 0 0000 0000 0
1 00001 1 0000 0001 1 – There is no sign (+ or -) in the representations, so these
2 00010 2 0000 0010 2 numbers are called unsigned
3 00011 3 0000 0011 3 • How can we represent signed numbers?
4 00100 4 0000 0100 4
• Solution 1: Sign-magnitude
5 00101 5 0000 0101 5
6 00110 6 0000 0110 6 – use one bit to represent the sign, and the remaining bits to
7 00111 7 0000 0111 7 represent the magnitude
8 01000 8 0000 1000 10
9 01001 9 0000 1001 11 7 6 0
sign = 0 → +ve +27 = 00011011
10 01010 A 0001 0000 12 sign magnitude
sign = 1 → -ve -27 = 10011011
11 01011 B 0001 0001 13
12 01100 C 0001 0010 14
13 01101 D 0001 0011 15
• Problems:
14 01110 E 0001 0100 16 – need to handle sign and magnitude separately
15 01111 F 0001 0101 17 – two values for zero (e.g., 00000000, 10000000)
16 10000 10 0001 0110 20
– not convenient for arithmetic
E1.2 Digital Electronics 1 7.5 6 November 2008 E1.2 Digital Electronics 1 7.6 6 November 2008

Two’s complement Using 2’s complement for signed numbers

• Using 2’s complement we can represent positive and negative
• Solution 2 is to represent negative numbers by taking the numbers
magnitude, inverting all bits, and adding one.
• We call this signed two’s complement form
• This is called two’s complement • In order to do this, we change the meaning of the left-most bit (MSB)
– The MSB has a negative weighting in 2’s complement form
Positive number +27 = 0001 1011 this is called
one’s
Invert all bits 1110 0100 Example for 8-bit numbers:
complement
Add 1 -27 = 1110 0101 27 26 20
unsigned number b7 b0
• Taking the two’s complement again give the original number: -27 26 20
signed 2’s complement b7 is also known
-27 = 1110 0101 b7 b0
as the sign bit
Invert all bits 0001 1010
Add 1 0001 1011 = +27 x = −bn −1 2 n −1 + bn − 2 2 n − 2 + " + b1 21 + b0 20

E1.2 Digital Electronics 1 7.7 6 November 2008 E1.2 Digital Electronics 1 7.8 6 November 2008
 Examples
The following numbers are in
Binary Decimal Why use two’s complement?
2’s comp unsigned
signed two’s complement form:
0111 7 7 • The major advantage of using two’s complement form is that
0101, 1011, 0111, 1100 0110 6 6 subtraction can be performed by addition using the 2’s complement
0101 5 5 of the subtrahend
What are the decimal values?
0100 4 4
minuend
2’s complement form Decimal 0011 3 3
+ 27 0001 10112
Example: 27 – 17
-8 4 2 1 0010 2 2
using normal – 17 0001 00012 subtrahend
0 1 0 1 5 0001 1 1
subtraction
1 0 1 1 -5 0000 0 0 10 0000 10102
0 1 1 1 7 1111 -1 15
1 1 0 0 -4 1110 -2 14
1101 -3 13
27 – 17 using two’s + +27 0001 10112 If a 1 is carried
Note that the range of 4-bit numbers is 1100 -4 12 over from the
complement + -17 1110 11112
different for unsigned and 2’s complement: 1011 -5 11 MSB, it is ignored
addition +10 0000 10102
1010 -6 10
4-bit unsigned 0 … +15 1001 -7 9
4-bit 2’s complement -8 … +7 1000 -8 8
E1.2 Digital Electronics 1 7.9 6 November 2008 E1.2 Digital Electronics 1 7.10 6 November 2008

Sign extension Sign extension

• In digital electronics, we usually have a fixed number of digits in How can we convert an 8-bit 2’s complement form number to 16 bits?
representing numbers
-27 26 20
– typically 8, 16, 32, 64 bits
duplicate the s
• Sometimes this is true for decimal numbers in “real life” sign bit
– e.g.: dates are often written with leading zeros: 05/01/2008
-215 +27 26 20
• We need to be able to extend a number to one using more bits
s s s s s s s s s
• For unsigned numbers this is easy:
just add zeros to the left-hand side This is called sign extension
• For sign-magnitude numbers
add zeros to the left-hand side of the magnitude Examples of 4-bit to 8-bit conversion:
(keep the sign bit at the front) +2 0010 → 00000010
-6 1010 → 11111010
E1.2 Digital Electronics 1 7.11 6 November 2008 E1.2 Digital Electronics 1 7.12 6 November 2008
 Signed addition Multiplication by -1
• The same hardware can be used for addition of unsigned numbers
and for two’s complement signed numbers • Taking the two’s complement of a number A gives –A
• Why? Consider 4-bit numbers: • So to find -1 x A
– To an adder circuit, a two’s complement negative number x – invert all the bits
looks like x + 16 (and 16 = 100002)
– add 1
– The result of x + y will be 16 more than it should be
– But: if we ignore the carry out of the MSB, the result will be
• There is one exception:
correct – providing it is in the range of -8 to +7.
– the maximum negative number
• What if x + y is not within -8 to +7?
– e.g.: -8 in a 4-bit system – because we cannot represent +8 in
– Sign-extend to n+1 bits
4-bit two’s complement form
– Use an n+1 bit adder

E1.2 Digital Electronics 1 7.13 6 November 2008 E1.2 Digital Electronics 1 7.14 6 November 2008

• Shifting right by N bits divides the number by 2N:

– The bit that “falls off the end” is the remainder
Multiplication and division by 2N – Sign-extension must be maintained for 2’s complement form
• Decimal:
• In decimal, multiplying a number by 10 is easy:
(486)10 divided by 10 gives 48 remainder 6
– shift all the digits one place to the left
• Unsigned:
– put a zero in the least-significant digit (110101)2 divided by 2 gives 011010 remainder 1
• In binary, multiplication by 2N is also easy: (53)10 (26)10
– shift all bits to the left by N places
– fill the LSBs with zeros (110101)2 divided by 4 gives 001101 remainder 01
(53)10 (13)10
• Example:
Binary Decimal • Signed 2’s complement:
0000 1101 13 (110101)2 divided by 2 gives 111010 remainder 1
0001 1010 26 (-11)10 (-6)10
0011 0100 52 (110101)2 divided by 4 gives 111101 remainder 01
0110 1000 104 (-11)10 (-3)10
E1.2 Digital Electronics 1 7.15 6 November 2008 E1.2 Digital Electronics 1 7.16 6 November 2008
 Binary adder circuits
Summary of signed and unsigned numbers • Revision of the binary addition process:
1 1 Carry
A 0 1 1 1 A = A3A2A1A0
Unsigned Signed (two’s complement)
+B 0 1 1 0
MSB has a positive weighting MSB has a negative weighting S 1 1 0 1
e.g.: +8 in a 4-bit system e.g.: -8 in a 4-bit system
• LSB column has 2 inputs and 2 outputs:
The carry-out from the MSB of an n- To avoid overflow, must – inputs A0 B0
bit adder can be used as an extra bit sign-extend to n+1 bits and use an – outputs S0 C1
to avoid overflow n+1 bit adder
• Other columns have 3 inputs, 2 outputs:
To increase the number of bits, add To increase the number of bits, sign-
zeros on the left-hand side extend by duplicating the MSB – inputs Ak Bk Ck
– outputs Sk Ck+1
Inverting all bits and adding 1 Inverting all bits and adding 1 • We use a “half adder” circuit for the LSB column
converts X to (2N - X) converts X to -X
• We use a “full adder” circuit for all other columns

E1.2 Digital Electronics 1 7.17 6 November 2008 E1.2 Digital Electronics 1 7.18 6 November 2008

Full adder
Half adder
A B Cin S Cout
A B S C 0 0 0 0 0
• Truth table 0 0 0 0 0 0 1 1 0
0 1 1 0 0 1 0 1 0
1 0 1 0 Truth table 0 1 1 0 1
1 1 0 1 1 0 0 1 0
1 0 1 0 1
• Boolean equations S = AB + AB = A ⊕ B 1 1 0 0 1
1 1 1 1 1
C = AB
S = A.B.Ci + A.B.Ci + A.B.Ci + A.B.Ci
A = A ⊕ B ⊕ Ci
&
• Implementation B
≥1 S
A
&
C
Boolean equations Co = ABCi + A BCi + ABCi + ABCi
(could also implement B
S with an XOR gate) A & = AB + ACi + BCi
B
= AB + Ci ( A + B )
E1.2 Digital Electronics 1 7.19 6 November 2008 E1.2 Digital Electronics 1 7.20 6 November 2008
 Complete circuitry for a full adder
FA implementation using only NAND gates

A
A
& &
B
Ci
B

A A C
& & & out
B
Ci Ci
& S
A B
& &
B
Ci
C i

A
&
B
Ci

E1.2 Digital Electronics 1 7.21 6 November 2008 E1.2 Digital Electronics 1 7.22 6 November 2008

Full adder from half adders Full adder from half adders

A B HA1S HA1C Cin HA2S HA2C S Cout

0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 0 1 0
0 1 1 0 0 1 0 1 0
0 1 1 0 1 0 1 0 1
1 0 1 0 0 1 0 1 0
1 0 1 0 1 0 1 0 1
1 1 0 1 0 0 0 0 1
1 1 0 1 1 1 0 1 1

A+B HA1S+Cin

E1.2 Digital Electronics 1 7.23 6 November 2008 E1.2 Digital Electronics 1 7.24 6 November 2008
 Parallel adder
• Uses 1 full adder per bit: n full adders for n-bit numbers A 4-bit parallel binary adder
• The carry output signal from one stage propagates to the carry input
of the next stage
• The full n-bit calculation takes a while:
n times the delay of one stage

E1.2 Digital Electronics 1 7.25 6 November 2008 E1.2 Digital Electronics 1 7.26 6 November 2008

Parallel subtraction using a parallel adder

Comparators
• Subtraction can be achieved by adding the negative of the number
– e.g.: 6 – 3 = 6 + (-3)
• In two’s complement, the negative is formed by inverting all the bits
and then adding 1 1-bit comparator
– Note that adding 1 can be achieved by using the carry-in of the
first stage
The output is 1 when the inputs are equal
An Bn A1 B1 A0 B0
1

A B Ci A B Ci A B Ci
A – B:
2-bit comparator
Co ∑ Co ∑ Co ∑

The output is 1 when A0 = B0 and A1 = B1

Sn S1 S0
E1.2 Digital Electronics 1 7.27 6 November 2008 E1.2 Digital Electronics 1 7.28 6 November 2008
 4-bit comparator Decoders

• A decoder detects the

presence of a specific
combination of bits
• Detects one of three conditions
• Only one output will be HIGH at
any one time: • In this example, X will only
be HIGH if:
– A greater than B (A > B)
A0 = 1
– A equal to B (A = B)
A1 = 0
– A less than B (A < B)
A2 = 0
A3 = 1

E1.2 Digital Electronics 1 7.29 6 November 2008 E1.2 Digital Electronics 1 7.30 6 November 2008

4-bit decoder truth table 4-bit decoder

• Binary input
• ‘Decimal’ outputs
• Outputs are active low
• Only one output is active at a
time

E1.2 Digital Electronics 1 7.31 6 November 2008 E1.2 Digital Electronics 1 7.32 6 November 2008
 BCD-to-decimal decoder BCD-to-7 segment display decoder

• LCD or LED displays often show digits a

made up of 7 segments or lines f b
• Use a decoder to translate 4-bit BCD g
numbers into 7 control signals (one for
each segment) e c
• This is called a BCD/7SEG decoder d

E1.2 Digital Electronics 1 7.33 6 November 2008 E1.2 Digital Electronics 1 7.34 6 November 2008

BCD/7SEG decoder truth table BCD/7SEG

a a
f b f b
g g

e c e c
d d

E1.2 Digital Electronics 1 7.35 6 November 2008 E1.2 Digital Electronics 1 7.36 6 November 2008
 Decimal-to-BCD encoder

E1.2 Digital Electronics 1 7.37 6 November 2008