High Step Up Ratio DC DC Converters Part - I
High Step Up Ratio DC DC Converters Part - I
Part I
Speaker: G. Spiazzi
P. Tenti, L. Rossetto, G. Spiazzi, S. Buso, P. Mattavelli, L. Corradini Dept. of Information Engineering DEI University of Padova
Seminar Outline
Why we need high step-up ratio converters?
Application fields
Step-down inverters require an input voltage higher than the maximum line voltage peak
3
Example of Microinverter
Utility grid
Microinverter structure
200-300W High Step-Up Microinverter single pv panel for single panel DC-DC
Modularity Reduction of partial shading effects Dedicated Maximum Power Point Tracker (MPPT)
4
UD rD + L rS S Switch model
Io
+
rL
Ui
Ro Uo
1 1 1 M= = F(d,Uo ,Ro ) 1 d 1 + rD (1 d) + rS d + rL + UD 1 d 2 Uo Ro (1 d)
5
ideal Mmax
Ro
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
6
0 0
Duty-cycle
1 0.95
0.9
0.85
Ro
0.8
0.75
0.7 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
7
Duty-cycle
ig Ld im Ug S
1:n21 Lm D2 + + C2 U2 Uo D1 + C1 U1
It can be seen as a flyback converter with a non dissipative snubber: D1 and C1 deliver to the output the energy stored in the transformer leakage inductance Ld
8
1:n21
im ig t iD1
iD2 t0 t1 t2 t3
t t
t4=Ts-t0
Advantages: ZCS turn on Soft diode turn off Reduced switch voltage stress
9
iD2
t t t
iD3 t0 t1 t2 t3 t4 t5 t6
U1
t7=Ts-t0
12
iD1
ig Ld Ls im Ug Lm
+ + +
Cr C2 U2 Uo S C1
+
iD2
t t t
iD3 t0 t1 t2 t3 t4 t5 t6
U1
t7=Ts-t0
13
iD2
t t t
U2 Uo
iD3 t0 t1 t2 t3 t4 t5 t6
C1
U1
t7=Ts-t0
iD2
t t t
U2 Uo
iD1 S
iD3 t0 t1 t2 t3 t4 t5 t6
D1 + C1 U1
t7=Ts-t0
15
iD1
ig Ld Ls im Ug Lm
+ + +
Cr C2 U2 Uo iD1 D1 + C1 U1
iD2
t t t
iD3 t0 t1 t2 t3 t4 t5 t6
t7=Ts-t0
16
iD2
t t t
iD3 t0 t1 t2 t3 t4 t5 t6
t7=Ts-t0
17
iD2
t t t
iD3 t0 t1 t2 t3 t4 t5 t6
C1
U1
t7=Ts-t0
18
Converter Parameters
Input voltage: Output voltage: Nominal output power: Switching frequency: Magnetizing inductance: Primary leakage inductance: Secondary leakage inductance: Ug = 25-35 V Uo = 400 V Po = 300 W fs = 100 kHz Lm = 20 H Ld = 0.4 H Ls = 2 H
19
M1
5.6 5.2 4.8 4.4 4 0.8
Uo M= Ug
U1 M1 = Ug
0.5
0.6
0.7
Duty-cycle
20
Uo M= Ug
No parasitic components
0.6 0.65 0.7
21
Duty-cycle
Experimental Results
Ug = 35 V, Uo = 400 V, Po = 300 W
ux [100V/div] uDS [50V/div
ig [2.5A/div]
Peaking due to a small dip in the converter input voltage due to fast current rise time
22
Experimental Results
Ug = 35 V, Uo = 400 V, Po = 300 W
ig im ux uDS ux uDS
t
Impk
ig iD1 t0 t1 t2 iD2 t t t t3 t4 t5 t6
ig
iD3 t0 t1 t2 t3 t4 t5 t6
t7=Ts-t0
23
Experimental Results
Ug = 25 V, Uo = 400 V, Po = 300 W
ig
Ld im Lm
Ls D3 C2 iD3
+ +
U2 Uo
C1
U1
ig [5A/div]
Measured Efficiency
Po = 300 W
fs = 100kHz
0.95
Po = 200 W
fs = 100kHz
0.94 0.93
0.94
fs = 200kHz
0.93
fs = 200kHz
0.92 25
27
29
31
33
35
27
29
31
33
35
Ug [V]
Ug [V]
25
Measured Efficiency
fs = 100 kHz
Ug = 35V
0.95
0.94
Ug = 25V
0.93
0.92 100
150
200
250
300
Po [W]
26
U2
D3 ig Ug Ld im Lm S
C3
U3 Uo
D1 + C1 U1
27
U2
ig Ld
1:n21 im Lm
is Ls
Cr x D + 2 + C2 U2 D3 Uo
D3 C3 ig Ug Ld im Lm S
U3 Uo
Ug S
D1 + C1 U1
D1 + C1 U1
Similar behavior with a higher degree of freedom in controlling the switch voltage stress
28
Converter Waveforms
BOOST section in DCM and FLYBACK section in CCM
Igpk Impk
ig
ur + Cr D2 x Np ig Ug Ld im Lm S D3 + C2 U2 is Ns + C3 U3 Uo D1 + C1 U1 +
Imvl
im
Im1 Im2
Ls
t
Impk
iD1
Im1/n21
-is(t2)
iD2
is(t5)
t t t
Im2/n21
iD3 t0 t1 t2 t3 t4
iD3(t3)
t5 t6
t7=Ts-t0
29
Experimental Prototype
Design example:
From the design constraints: M= Uo / Ug=400/35=11.42 Input voltage: M1= U 1/ Ug=75/35=2.143 Ug = 2535V Output voltage: Numerically solving: Uo = 400V d = 0.519, n21 = 4.589 Nominal output power: M2 = U 2/ Ug = 4.823 Po = 300W M3 = M-M1-M2 = U 3/ Ug = 4.454 Switching frequency: fs = 100kHz M 150V rated mosfet Boost output: calculated voltage U1 = 75V gains (continuous 25 Magnetizing inductance: curves) and simulation Lm = 20H results (dotted) 20 Primary leakage inductance: Ld = 0.4H 15 Secondary leakage 10 inductance: Ls = 2H
Based on desired current ripple and DCMCCM mode at nominal power
M1
5 4 3 2 1 0.8
30
5 0.4
0.5
0.6
0.7
Duty-cycle
Experimental results
ux
uDS
ux: 100V/div; uDS: 20V/div; ig: 5A/div
ig
Np ig
ux ux uDS uDS
Ug
Ld
t6
31
Converter efficiency
The converter efficiency was measured as a function of input voltage, at Po=300W,Fig.1, and at Ug=[25V,35V] and variable output power, Fig. 2
Efficiency
Efficiency
0.96
Ug = 35V
0.95
0.95
0.94
0.94
Ug = 25V
0.93 25
27
29
31
33
35
0.93 100
150
200
250
300
Ug [V]
Po [W]
Fig.1
Fig.2
32
Np ig Ug Ld
ig id Ld i C UAC + AC m SAC Lm D2 Np + Cr ur Ls io + C2 U2 + is Uo Ro
Ug
D1
Ns + C1 U1
33
34
Converter Operation
Hp: negligible capacitor voltage ripples
id
im(t0) Imvl id(t0) Impk
im t
iSAC
Ug
t iD2
Ug
Ns + C1 U1
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t
Converter Operation
Hp: negligible capacitor voltage ripples
id
im(t0) Imvl id(t0) Impk
im t
iSAC
Ug
t iD2
Ug
Ns + C1 U1
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t
36
Converter Operation
Hp: negligible capacitor voltage ripples
id
im(t0) Imvl id(t0) Impk
im t
iSAC
Ug
t iD2
Ug
D1
Ns + C1 U1
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t
Converter Operation
Hp: negligible capacitor voltage ripples
id
im(t0) Imvl Impk
im t
id(t0)
i C UAC + AC m SAC
iSAC t iD2
Ug D1
Ns + C1 U1
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t
Converter Operation
Hp: negligible capacitor voltage ripples
id
im(t0) Imvl Impk
im t
Ld Lm Np
id(t0)
i C UAC + AC m SAC
iSAC t iD2
Ug
Ns + C1 U1
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t
Converter Operation
Hp: negligible capacitor voltage ripples
id
im(t0) Impk
im
Imvl
iSAC t iD2
Ug
t iD1 t3 t4 t5 t6=Ts-t0 t
t0 t1 t2
40
Converter Parameters
Input voltage: Output voltage: Nominal output power: Switching frequency: Magnetizing inductance: Primary leakage inductance: Ug = 25-35 V Uo = 400 V Po = 300 W fs = 100 kHz Lm = 20 H Ld = 0.4 H
Experimental Results
Ug = 35 V, Uo = 400 V, Po = 300 W (2s/div)
uD1 [100V/div]
Peaking due to a small dip in the converter input voltage due to the fast current rise time
42
Experimental Results
Ug = 35 V, Uo = 400 V, Po = 300 W (2s/div)
uD1 [100V/div]
43
Experimental Results
Ug = 35 V, Uo = 400 V, Po = 300 W (2s/div)
Ld C UAC + AC SAC Lm D2 + Cr ur Ls + D1 C1 + C2 + Uo Ro
Ug
id [5A/div]
44
im
id(t0)
iSAC t iD2
Ug
id [5A/div]
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t t6 = t0 t1 t2
45
im
id(t0)
iSAC t iD2
Ug
id [5A/div]
t iD1 t0 t1 t2 t3 t4 t5 t6=Ts-t0 t
46
t3 t4 t5
id [5A/div]
[200ns/div]
47
id [2A/div]
48
Measured Efficiency
Power stage only
Ug = 35V
0.95 0.94
Po = 300 W
0.94
Ug = 25V
0.93
0.93
0.92
0.92 100
150
200
250
300
0.91 25
27
29
31
33
35
Po [W]
Ug [V]
49
Comments
There are different topologies presented in literature whose behavior is very similar to the Integrated Boost-Flyback converter. These topologies have a drawback of a discontinuous input current waveform, that make the use of such converters for higher power levels at least problematic. For high power applications, a continuous input current represents a very nice feature
50