Electronic Design Automation: Its Importance and Challenges

Susmita Sur-Kolay
Advanced Computing and Microelectronics Unit

Indian Statistical Institute

Agenda
V SI design cycle ! a glimpse A "limpse o# EDA Algorithms Architectural Synthesis: Scheduling Allocation $hysical Synthesis: %loorplanning &outing 'e( technologies pose #resh challenges

Evolution o# Very arge Scale Integration in Microelectronics

Year 1947
of transistor 1 !

1950
Discrete Components

1961 SSI

1966 MSI

1971 LSI

1980 VLSI

1990 ULSI

2000

2010

Technology Invention Number of Transistors per chip Typical Products

SI DSM

1 $%nction &ransistor an' 'io'e

10 Lo(ic (ates) *"ip! f"ops

100 ! 1000 Co%nters MU+ ,''ers

1000 ! 20000 8088) -,M) -.M

20000! 1 mi""ion 16 / 02 1it 2 D-,M

1!6 mi""ion

10 # 20 4i""ions mi""ion

,SIC DS2 Virt%a" -ea"it3) MCM

SoC) M%"ti! Core s3stems

"ordon Moore)s %irst a( *Intel+ ,-./0 : 1 transistors per chip (ill dou2le every year3 Why? bigger circuits on a chip smaller transistors switch faster

4rends and Challenges

High Performance VLSI Chips in early 9 s DEC 21064 microprocessor
Process !echnology " #$% m C&'S (rchitecture " )* bit +ISC 'perating ,re-#" .% /% &H0 Pea1 Performance " * &IPS2 . &,L'PS !ransistor Count " 3#)4 million 5ie si0e " 36#9mm 7 3)#4 mm Pac1age" *63 pin P8(

In late 9 s
3 /. million within . years an9 3 million in % years 3 8H0 in . years an9 ./6 8H0 in % years . mm 7 . mm 9ie Low power

!o9ay
':er a billion transistor chip ,eature si0e )%nm2 *% nm2 6. nm ### ,ew 8H0 operating fre-uency 4/3 layers of Cu interconnect &ulti to many P cores2 65 !hermal issues 5esign for &anufacturability

5esi9erata " +easonable 9esign time an9 cost

Computer/(i9e9 5esign (utomation

8asic Components in V SI Circuits

9 Active Electronic Devices
! 4ransistors ! ogic gates and cells ! %unction 2loc:s
$ad Metal, Via Metal5

Data $ath $ A

I67

9 Interconnects
ocal signals "lo2al signals Cloc: signals $o(er6ground nets 9 Circuit can 2e represented as a hypergraph ! ! ! !

&7M6 &AM

A6D Converter

&andom logic

V SI Design Cycle
9 9 9 9 9 9 9 System speci#ications %unctional design ogic design Circuit design $hysical ayout design %a2rication and $ac:aging
Wafer DI$ *Dual Inline $ac:age0 $"A *$in "rid Array0

, ; <(= > C? @<5>A<B>C??D 8 ; BC > (5

4esting
A4$" *Automatic 4est $attern "enerator0 D%4 *Design #or 4esta2ility0 8IS4 *8uilt-In Sel# 4est0

Domains ; evels o# &epresentation

$hysical Design

A CM7S Inverter

8asic CM7S Design &ules

5iffusion +egion Wi9th Polysilicon +egion Wi9th 5iffusion/5iffusion Spacing Poly/Poly Spacing Polysilicon 8ate A7tension Contact A7tension &etal Wi9th . . 6 . . 6

&ecent trends: <ield-a(are D%M calls #or ,/== design rules + so restrictive design rules are 2ecoming popular

History of Alectronic 5esign (utomation

Year
1950-1965 1965-1975 Manual Design Layout Editors Automatic routers for Printed Circuit oard !PC " Efficient Partitioning Algorit#m Automatic %lacement tools &ell defined %#ases of design of circuits 'ignificant t#eoretical de(elo%ment in all %#ases Performance dri(en %lacement and routing tools Parallel algorit#ms for %#ysical design Logic synt#esis )ig# Le(el 'ynt#esis *esting +ormal ,erification Design for Manufactura-ility !D+M" *#ree-dimensional .Cs Design Tools

1975-19$5

19$5-%resent

Agenda
V SI design cycle ! a glimpse A "limpse o# EDA Algorithms Architectural Synthesis: Scheduling Allocation $hysical Synthesis: %loorplanning &outing 'e( technologies pose #resh challenges

Common Com2inatorial 7ptimi>ation Methods

9 9 9 9 9 "reedy Divide and Con?uer Dynamic $rogramming 'et(or: %lo( Mathematical $rogramming *e3g3+ linear programming+ integer linear programming0

4he most important tas: o#ten is to #ind the right pro2lem #ormulation

EDA Algorithms #or @igh evel System Synthesis

9 Main 4as:s
! Control - Data %lo( Scheduling
9 4ime-constrained: to minimi>e resource units 9 &esource-constrained: to minimi>e num2er o# control steps

! &esource Allocation
9 8inding o# %unctional Units+ Storage+ Interconnection

9 Interdependent 2ut each optimi>ation pro2lem itsel# is hard

! solve se?uentially and then iterate i# re?uired

An eAample o# Data %lo( "raph

(hile *A B a0 do A, :C A D dAE u, :C u - *F G A G u G dA0 - * F G y G dA0E y, :C y D *u G dA0E A :CA,E u :C u,E y :C y,E end(hile

8ree9y / (S(P versus (L(P *as soon as possi2le0 :: *as late as possi2le0

Multi-core schedulingH

Data $ath Allocation

9 9 "oal : Minimi>e the amount o# hard(are+
! i3e3+ #unctional units+ memory elements+ communication paths

Su2tas:s:
! ! ! ! Unit Selection ! types and num2ers %unctional Unit 8inding - mapping operations onto #unctional units Storage 8inding ! register allocation to varia2les Interconnection 8inding - providing interconnection 2et(een 2uses and multipleAers

72Iective: #or a given schedule+ minimize

! total interconnect length ! total register+ 2us driver+ multipleAer cost ! critical path delays

9 Su2tas:s are hard+ tac:led one a#ter another 9 Interdependent ! su2tas: ordering

Storage 2inding 2y Cli?ue $artitioning

A, A. AF A,= A/ AN AM AA5 AK A, A5 AF AK A/ A. AM AN A- A,= A,,

s1 s2 s3 s4

A,,

A,

A5

i#etimes o# varia2les

Compatibility graph" non/o:erlap of lifetimes &egister Allocation 2y Cli?ue partitioning JA,+ A5+ AK+ A.+ A,=L+JAF+ A/+ AML+JAN+ A-+ A,,L r, C OA,+ ANP r5 C OA5+AF+ A-P rF C OAK+A/+ A,,P rK C OA.+AMP r/ C OA,=P

Agenda
V SI design cycle ! a glimpse A "limpse o# EDA Algorithms Architectural Synthesis: Scheduling Allocation $hysical Synthesis: %loorplanning &outing 'e( technologies pose #resh challenges

@ierarchical Design
9 Several 2loc:s a#ter partitioning: 9 'eed to:
! $ut the 2loc:s together3 ! Design each 2loc:3

Which step first?

9 @o( to put the 2loc:s together (ithout :no(ing their shapes and the positions o# the I67 pinsH 9 I# (e design the 2loc:s #irst+ those 2loc:s may not 2e a2le to #orm a tight pac:ing3

%loorplanning
4he #loorplanning pro2lem is to plan the positions and shapes o# the modules at the 2eginning o# the design cycle to optimi>e the circuit per#ormance:
! ! ! ! ! chip area total (irelength delay o# critical path routa2ility others+ e3g3+ noise+ heat dissipation+ etc3

%loorplanning vs3 $lacement

9 8oth determines 2loc: positions to optimi>e the circuit per#ormance3 9 %loorplanning:
! Details li:e shapes o# 2loc:s+ I67 pin positions+ etc3 are not yet #iAed *2loc:s (ith #leAi2le shape are called so#t 2loc:s03

9 $lacement:
! Details li:e module shapes and I67 pin positions are #iAed *2loc:s (ith no #leAi2ility in shape are called hard 2loc:s03

9 Input:

%loorplanning $ro2lem

! n rectangular 2loc:s (ith areas A1, ... , An ! 8ounds ri and si on the aspect ratio o# 2loc: 8i ! 'etlist+ i3e3+ sets o# 2loc:s to 2e connected * set o# hyperedges
o# circuit hypergraph0

9 7utput:
! 4opology
9 #or each 2loc:+ co-ordinates *Ai+ yi0

! Si>ing
9 #or each 2loc: (idth (i and height hi such that hi (i C Ai and ri hi6(i si

9 72Iective:
! 4o optimi>e the circuit per#ormance3

8ounds on Aspect &atios

I# there is no 2ound on the aspect ratios+ can (e pac: everything tightlyH
- SureQ

8ut (e don5t (ant to layout 2loc:s as long strips+ so (e re?uire ri hi6(i si #or each i3

8ounds on Aspect &atios

9 Re can also allo( several shapes #or each so#t 2loc::

9 %or hard 2loc:s+ the orientations can 2e changed:

72Iective %unction
A commonly used o2Iective #unction is a (eighted sum o# area and (irelength: cost C A D (here A is the total area o# the pac:ing+ is the total (irelength+ and and are appropriate constants3

Rirelength Estimation
9 EAact (irelength o# each net is not :no(n until routing is done3 9 In #loorplanning+ even pin positions are not :no(n yet3 9 Some possi2le (irelength estimations:
! Center-to-center estimation ! @al#-perimeter estimation

9 Slicing %loorplan: 7ne that can 2e o2tained 2y repetitively su2dividing *slicing0 rectangles hori>ontally or vertically3

Slicing and 'on-Slicing %loorplan

9 'on-Slicing %loorplan: 7ne that may not 2e o2tained 2y repetitively su2dividing alone3 9 7tten * SSS-N50 pointed out that slicing #loorplans are much easier to handle3

4op-do(n and 8ottom-up approaches eAist

%loorplan 4opology "eneration

A floorplan is said to 2e hierarchical order o# k+ i# it can 2e o2tained 2y recursively partitioning a rectangle into at most k parts3 A :-ary 5 F K hierarchical , #loorplan tree . /
, M F N F N N K 5 . / M N F K N -

Order ?

K F

4opology "eneration 2y "raph Duali>ation

Input : A set o# rectangular 2loc:s A set o# reali>ations+ i3e3+ *(idth+ height0 pairs+ #or each 2loc: AdIacency graph #or the 2loc:s Requirements : 4opology generation --- ocation o# each 2loc: (ithin a rectangular envelope such that no t(o 2loc:s overlap Si>ing --- An appropriate si>e+ i3e3+ (idth and height+ o# each 2loc: O !ecti"es : Minimi>e area o# the rectangular envelope &educe net-length #or critical nets

&ectangular Duali>ation
, 5

, F / / K AdIacency "raph K

5 F

"eometric Dual o# AdIacency "raph

&ectangular Duali>ation
,

A %or2idden &ectangular "raph

5 F

Characteristics
6 Every #ace+ eAcept the eAterior+ is a triangle 6 All internal vertices have degree S K 6 all cycles that are not #aces and the eAterior #ace have length S K 6#RO#$R%& 'RIA()*%A'$+ #%A(AR )RA#, -#'#.

Si>ing

9 selecting a particular *length+ (idth0 pair #or each 2loc: 9 o2Iective is to minimi>e space (astage 9 compleA #or non-slici2le #loorplans

( Classic Wor1
/Optimal Orientation of 0ells in 1licing floorplan +esigns2 %. 1tockme3er, Information and 0ontrol 45-1678., 6191:1

! This is an earlier paper than [Wong-Liu86 ! dealing "ith simpler problem ! iven s"icin( str%ct%re an' a set of mo'%"e s7apes 8or s7ape "ist9 ! :o; to orient t7ese mo'%"es s%c7 t7at t7e tota" area is sma""est<
/ K F N K 5 / F N MA,F / M

A D

8 5 C
F

A
F

D
.

5 E /

NA,,

Dead space
9 Dead space is the space that is (asted:

Dea' space

9 Minimi>ing area is the same as minimi>ing deadspace3 9 Dead space percentage is computed as *A - iAi0 6 A ,==T

5ifficulty
,. v K v 5 5 5 v K 5

m,9m5 choices m, m5

Eey I9ea
9 Dynamic programming
! Compute a set of irre9un9ant solutions at each sub/tree roote9 from the list of irre9un9ant solutions for its two chil9 subtrees ! Pic1 the best solution from the list of irre9un9ant solutions at the root

EAample o# Merging: only :eep irredundant solutions

Stoc:meyer Algorithm

Comple7ity of the (lgorithm

nC 1 o# leaves C 5 G 1 o# modules dCdepth o# the tree &unning timeC 7*nd0 Storage C 7*n0 2ecause+ at depth :+ < sum o# the lengths o# the lists C7*n0 < time to construct these lists C7*n0 < con#igurations stored at this node can 2e release as soon as the node is processed EAtension Each module has : possi2le shapes &unning time and storage 7*n:d0
depth :

Is this algorithm applica2le to non-slici2le #loorplansH

Summary #or ASIC #loorplanning

9 %loorplan pro2lem is de#initely '$ hard 9 Slicing topology is easier to deal (ith 9 %or a given set o# modules and the slicing tree+ Stoc:meyer)s algorithm can give the optimal solution ! 8ut a very ideal situation that doesn)t happen o#ten ! 'ice algorithm using dynamic programming 9 %or general topology+ iterative heuristics such as
simulated annealing JRong ; iu+ DAC)N.L

9 Compact #loorplan representation schemes needed 9 4opology generation and si>ing interdependent - need integrated approach
! A'D-7& graph search 2ased method JDasgupta et al3 4CAD U-NL

%$"A Design $rocess

%loorplanning #or %$"As

%$"A $lacement and %loorplanning

9 %$"A mandates

! Very #ast mapping o# digital design onto %$"A chip ! 7ptimal per#ormance in terms o# circuit speed
9 Minimi>e delay or (ire-length laid out on the chip I'= 9 Depends on i i i ho( i #ar the components are placed
, 5 F K

i,

iF

CL=
i5

C 86module
K

, / #,

5 . ,= #5

F M N ,= .

, K F M 5 / N

iK

$lacement

'etlist

%$"A

$lacement: 4op-do(n partition-2ased approach

4heory Meets $ractice

Method: 4op-do(n partition-2ased ! $ractical implementation o# linear arrangement 2y recursive min-cut 2i-partitioning ! $lace linear arrangement o# C 8s 2y space-#illing curves *@il2ert+ V0 &esults: ! Derivation o# theoretical 2ounds on ?uality o# placement : (irelength ,, ,5 ,F ,. ! Speedup : 5A compared to V$&+ a popular earlier method
,= M N / ,K F 5 ,/

, 5 F

K / . M N - ,= ,,,5 ,F,K,/ ,.

@il2ert
,

$ritha 8anerIee et al3+ ;#)A #lacement using 1pace ;illing 0ur"es: 'heor3 <eets #ractice + Special issue on Con#iguring Algorithms+ $rocesses and Architecture *CA$A0 in ACM 4ransactions on Em2edded Computing System *4ECS0+ vol3 -+ no3 5+ pp3 ,-5F+ 7cto2er 5==-3

%loorplanning #or Modern %$"As:

Single instance
n5
5 K / . M N

*c+r+m0
, F

3 % 4

. ) 6 $

nF

n,

9 9

$ro2lem: place modules having di##erent resource types on %$"As Method: 4hree phase deterministic algorithm - 7*nF0 time compleAity ! &ecursive min-cut partition 2ased linear arrangement o# modules ! Uni#ied topology generation and si>ing #or module shape ; position ! placement o# minority resources 2y graph theoretic approach &esults: ! Speedup: 5A to FMFA over eAisting (or: ! Wuality: FKT improvement in (ire-length over eAisting (or:

$ritha 8anerIee et al3+ ;ast *nified ;loorplan 'opolog3 )eneration and 1izing on ,eterogeneous ;#)As + IEEE 4rans3 on CAD o# Integrated Circuits and Systems+ vol3 5N+ no3 /+ pp3 ./,-..,+ May 5==-3

%loorplanning #or $artial &e-con#igura2ility:

Multiple instances
, 5 K / M N . F

3
inst,

* %

. ) 6 $

, F K / N

4
inst5

9 $ro2lem: some modules on %$"A re-con#igured+ some static *partial0 9 Method: 4hree phase deterministic algorithm
! %iA position o# static modules such that ! $lace remaining modules satis#ying di##erent resource re?uirements ! Minimi>e (ire-length

9 &esults:
! 'o recon#iguration overhead (ithout sacri#icing ?uality o# solution
$ritha 8anerIee et al3+ ;loorplanning for #artiall3 Reconfigura le ;#)As, I$$$ 'rans. on 0A+ of Integrated 0ircuits and 13stems+ vol3 F=+ no3 ,+ pp3 N-,M+ Xan 5=,,

Agenda
V SI design cycle ! a glimpse A "limpse o# EDA Algorithms Architectural Synthesis: Scheduling Allocation $hysical Synthesis: %loorplanning &outing 'e( technologies pose #resh challenges

4he &outing $ro2lem

9 Apply it a#ter #loorplanning6placement 9 Input:
! 'etlist ! 4iming 2udget #or+ typically+ critical nets ! ocations o# 2loc:s and locations o# pins

9 7utput:
! "eometric layouts o# all nets

9 72Iective:
! Minimi>e the total (ire length+ the num2er o# vias+ or Iust completing all connections (ithout increasing the chip area3 ! Each net meets its timing 2udget3

4he &outing Constraints

9 EAamples:
! $lacement constraint ! 'um2er o# routing layers ! Delay constraint ! Meet all geometrical constraints *design rules0 ! $hysical6Electrical6Manu#acturing constraints:
9 Crosstal: 9 $rocess variations+ yield+ or lithography issuesH

Classi#ication o# &outing

Approaches #or &outing

9 Se?uential Approach:
! &oute nets one at a time3 ! 7rder depends on #actors li:e criticality+ estimated (ire length+ and num2er o# terminals3 ! Rhen #urther routing o# nets is not possi2le 2ecause some nets are 2loc:ed 2y nets routed earlier+ apply U&ip-up and &eroute) techni?ue *or UShove-aside) techni?ue03

9 Concurrent Approach:
! Consider all nets simultaneously+ i3e3+ no ordering3

Steiner 4ree
9 %or a multi-terminal net+ (e can construct a spanning tree to connect all the terminals together3 9 8ut the (ire length (ill 2e large3 9 8etter use Steiner 4ree:
A tree connecting all terminals and some additional nodes *Steiner nodes03

Steiner 'ode

9 &ectilinear Steiner 4ree:

Steiner tree in (hich all the edges

&outing $ro2lem is Very @ard

9 Minimum Steiner 4ree $ro2lem:
! "iven a net+ #ind the Steiner tree (ith the minimum length3 ! 4his pro2lem is '$-CompleteQ

9 May need to route tens o# thousands o# nets simultaneously (ithout overlapping3 9 72stacles may eAist in the routing region3

"eneral &outing $aradigm

4(o phases:

"lo2al &outing

"lo2al routing is divided into F phases:

,3 &egion de#inition 53 &egion assignment F3 $in assignment to routing regions

&outing &egion De#inition

Divide the routing area into routing regions o# simple shape *rectangular0: 9 @ard pro2lem i# certain criterion such as sum o# length o# edges added is minimi>ed
S(itch2oA Channel

9 Channel: $ins on 5 opposite sides3 9 5-D S(itch2oA: $ins on K sides3 9 F-D S(itch2oA: $ins on all . sides3

$ro2lem %ormulation #or "lo2al &outing

Input:
regions0

A netlist ( C =(1, (>,??(n@ and the routing graph " C *V+ E0

*verteA ! routing region+ edge ! adIacency o# t(o routing

O !ecti"e: %ind a Steiner tree 'i #or each net (i, 1A i A n such that ,3

%en -'i. is minimi>ed

53 maB -%en -'i.. is minimi>ed 1u !ect to conditions *-e!. A 0-e!. #or all e! $ (here %en -'i. C the length o# the Steiner tree 4i C *eI0 C capacity o# edge *eI0 U *eI0 C 1 (ires through the channel corresponding to edge eI

Integer $rogramming Approach

Standard techni?ues to solve I$3 'o net ordering3 "ive glo2al optimum3 Can 2e eAtremely slo(+ especially #or large pro2lems3 4o ma:e it #aster+ a #e(er choices o# routing trees #or each net can 2e used3 May ma:e the pro2lem in#easi2le or give a 2ad solution3 Determining a good set o# choices o# routing trees is a hard pro2lem 2y itsel#3

Ma>e &outing $ro2lem

9 "iven:
! A planar rectangular grid graph3 ! 4(o points S and 4 on the graph3 ! 72stacles modeled as 2loc:ed vertices3

9 72Iective:
! %ind the shortest path connecting S and 43

9 4his techni?ue can 2e used in glo2al or detailed routing *s(itch2oA0 pro2lems3

Ma>e &outing
S

8asic Idea
9 A 8readth-%irst Search *8%S0 o# the grid graph3 9 Al(ays #ind the shortest path possi2le3 9 Consists o# t(o phases:
! Rave $ropagation ! &etrace

An Illustration
S

= , /

, 5 F K

5 F K /
4

F / .

Rave $ropagation
9 At step :+ all vertices at Manhattandistance : #rom S are la2eled (ith :3 9 A $ropagation ist *%I%70 is used to :eep trac: o# the vertices to 2e considered neAt3
S

5 F

5 F K /
4

F / .

,
4 A#ter Step =

5 F

,
4

5 F K

A#ter Step F

A#ter Step .

&etrace
9 4race 2ac: the actual route3 9 Starting #rom '3 9 At "erteB Cith k, go to an3 "erteB Cith la el k-,3
S

5 F

F /

, /

5 F K

K /
4

%inal la2eling

4ime and Space CompleAity

9 %or a grid structure o# si>e C h:
9 4ime per net C 7*Ch0 9 Space C 7*Ch log Ch0 *7*log Ch0 2its are needed to store each la2el30

9 %or a K=== K=== grid structure:

9 5K 2its per la2el 9 4otal KN M2ytes o# memoryQ

Detailed &outing in Special &egions

4ype o# &outing region *channel+ s(itch2oA0 &outing model *manhattan+ Y-routing0 'um2er o# terminals *i3e3 t(o terminal vs3 multi-terminal nets0 'um2er o# availa2le layers 'et type *i3e3 critical vs3 not-critical nets0 'et (idth *in case o# gridless routing0

4erminology o# Channel &outing $ro2lems

, K 5 = 5 , K = F K = Upper 2oundary

Channel

o(er 2oundary F = , 5 = F , = = 5 F 4erminals

4erminology o# grid-2ased Channel &outing $ro2lems*cont30

,
4rac:s

"rid

Columns

EAample o# Channel &outing $ro2lems

ayer ,

EAample o# Channel &outing $ro2lems *cont30

=
ayer 5

EAample o# Channel &outing $ro2lems *cont30

, K 5 = 5 , K = F K =
Via

Channel &outing $ro2lem %ormulation

Assign o# hori>ontal segments o# nets to trac:s Assign o# vertical segments to connect ! hori>ontal segments o# the same net in di##erent trac:s ! the terminal o# the net to hori>ontal segment o# the net "oals ! Channel height+ i3e3 1 trac:s is minimi>ed ! 1 Vias is minimi>ed ! 4otal (ire-length is minimi>ed

Agenda
V SI design cycle ! a glimpse A "limpse o# EDA Algorithms Architectural Synthesis: Scheduling Allocation $hysical Synthesis: %loorplanning &outing 'e( technologies pose #resh challenges

'e( Challenges
9 Design #or Manu#actura2ility 9 4hree-dimensional ICs 9 Intellectual $roperty $rotection and @ard(are Security

4ypical 7ptical Setup

*i(= 1= &3pica" I""%mination set%p

Di##raction o# ight on mas: ; e##ects

*i(= 2= &3pica" Diffraction effect

*i(= 0= *eat%re 'istortion '%e to 'iffraction effect

2ac:

7ptical $roAimity Correction *7$C0

7$C-A(are &outing JRang et al3

AS$DAC =/L

9'eed to predict 7$C overhead and More .2C frien'"3 incorporate into cost model o# routing algorithm 9 &ule-2ased vs Model-2ased methods

4hree-dimensional ICs
9 Stac:ed dies
! Additional vias called through silicon via*4SV0

9 Monolithic 9 4hermal issues

9 non-electrical thermal vias #or cooling

! 'eed to #ormulate the design automation pro2lems ta:ing these additional constraints into account

$aradigm Shi#t

Easier to integrate miAed-signal circuits (ith di##erent #unctionality per level

Ra#er level stac:ing *vertical cross-section0

Intellectual $roperty *I$0 o# V SI Industry

Already designed *and #a2ricated0 circuit components+ those are reused on a larger electronic system or system-on-chip *SoC0+ constitute an I$3 Design I$: Circuit component in electronic #orm
@ard(are I$: %a2ricated circuit component

Rhy sharing neededH

,,6=,6,F

I$ reuse and sharing are adopted to manage compleA design challenges to meet time-to-mar:et to meet lo( cost re?uirement
Sur-Kolay

NF

Design %lo( and I$

Design Spec3
Design Spec

ogic design

% C *A8 D C0 G*DDE*YD<00

So#t I$ *&4 Description0 %irm I$ *"ate netlist0 @ard I$ *Design layout0

Circuit design

IC Design
$hysical design ; D%M

%a2rication

@ard(are I$ *Chip0

%a2

,,6=,6,F

Sur-Kolay

N/

4roIans
A Combinational Trojan A Sequential Trojan

Insertion o# 4roIan ! 4he circuit is modi#ied 2y introducing or resi>ing gates or redesigning the inter#ace Activation o# 4roIan ! 4he change is activated under a speci#ic condition to eAtract valua2le in#ormation #rom the circuit or to hamper its normal 2ehavior
,,6=,6,F Sur-Kolay N.

Categories o# misappropriations
during sharing and reuse
I$ Vendor *Design @ouse0 arger I$ 6 SoC company *,0 Additional Copies o# I$

IC
*50

Design I$
*50 Mas: *F0

Selling *50 egal I$

troIan *F0

%a2rication %acility *,0 Additional Copies o# IC

Misappropriation6 Unauthori>ed &euse 9 "eneration o# illegal copies *,0 9 Unauthori>ed access *50 *hac:ing or interception0 Unauthori>ed in#ormation retrieval Inclusion o# 4roIan *eAtra un(anted circuitry0 *F0
NM

troIan IC *F0

,,6=,6,F

Sur-Kolay

Security Mechanisms

,,6=,6,F

Sur-Kolay

NN

$arting &emar:s
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