TMS320VC5501 Fixed-Point Digital Signal Processor

Data Manual

Literature Number: SPRS206K December 2002 Revised November 2008

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Revision History

REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS206J device-specific data sheet to make it an SPRS206K revision. Scope: See table below.
PAGE(S) NO. 21

ADDITIONS/CHANGES/DELETIONS Table 24, Signal Descriptions: HD[7:0]: removed M from Other column HC0: removed M from Other column HC1: removed M from Other column HCNTL0: removed M from Other column HCNTL1: removed M from Other column HCS: removed M from Other column HR/W: removed M from Other column Table 329, Peripheral IDLE Control Register Bit Field Description: Updated footnote Figure 522, Reset Timings: Added footnote about the state of the DSP pins during power up

88

161

December 2002 Revised November 2008

SPRS206K

Revision History

SPRS206K

December 2002 Revised November 2008

Contents

Contents
Section 1 2 TMS320VC5501 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Ball Grid Array (GZZ and ZZZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Low-Profile Quad Flatpack (PGF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.5 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Configurable External Ports and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Parallel Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Host Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 External Bus Selection Register (XBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Timer Signal Selection Register (TSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Inter-Integrated Circuit (I2C) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Host-Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 DMA Channel 0 Control Register (DMA_CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Input Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 EMIF Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 Changing the Clock Group Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Idle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 IDLE Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 Module Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.4 Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 16 16 17 17 19 21 38 39 39 40 40 41 42 42 43 43 45 46 48 50 51 52 53 54 56 57 58 58 60 61 63 64 64 66 76 77 77 77 80 81 84

December 2002 Revised November 2008

SPRS206K

Contents

Section 3.10.6 Clock State of Multiplexed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.7 IDLE Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 General-Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.2 Parallel Port General-Purpose I/O (PGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 External Bus Control Register (XBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Ports and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 XPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 DPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 IPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Time-Out Control Register (TOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.3 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notice Concerning TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 84 84 92 92 94 104 105 106 106 109 111 112 113 114 116 129 130 131 131 132 135 135 135 135 135 136 137 137 137 137 138 139 140 140 141 142 143 145 147 147 150 154 159 160 162

3.11

3.12 3.13

3.14 3.15 3.16

3.17 4

Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability . . . . . . . . . . . . . . . . . 4.1.1 Initialization Requirements for Boundary Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Boundary Scan Description Language (BSDL) Model . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Electrical Characteristics Over Recommended Operating Case Temperature Range . . . . . . . 5.5 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Clock Generation in Bypass Mode (APLL Synthesis Disabled) . . . . . . . . . . . . . . . . . 5.6.4 Clock Generation in Lock Mode (APLL Synthesis Enabled) . . . . . . . . . . . . . . . . . . . 5.6.5 EMIF Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Asynchronous Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Programmable Synchronous Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Synchronous DRAM Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 HOLD/HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 External Interrupt and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPRS206K

December 2002 Revised November 2008

Contents

Section 5.11 5.12 5.13 5.14 XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output (GPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel General-Purpose Input/Output (PGPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.1 TIM0/TIM1/WDTOUT Timer Pin Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.3 TIM0/TIM1/WDTOUT Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.2 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.3 McBSP as SPI Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host-Port Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.1 HPI Read and Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.2 HPI General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.3 HPI.HAS Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-Integrated Circuit (I2C) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver/Transmitter (UART) Timings . . . . . . . . . . . . . . . . . . . . . . . . .

Page 163 164 165 166 166 167 168 169 169 172 173 179 179 185 186 187 189 190 190 192

5.15

5.16

5.17 5.18 6

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2002 Revised November 2008

SPRS206K

Figures

List of Figures
Figure 21 22 201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17 19

31 32 33 34 35 36 37 38 39 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336

TMS320VC5501 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Layout (0x6C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Example A (GPIO6 = 1 at Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Example B (GPIO6 = 0 at Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Layout (0x8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Channel 0 Control Register Layout (0x0C01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Layout (0x1C80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Layout (0x1C88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Layout (0x1C8A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Layout (0x1C8C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Layout (0x1C8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 3 Register Layout (0x1C90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Layout (0x1C92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Layout (0x1C98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Layout (0x1C82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Layout (0x8400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Layout (0x8C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Layout (0x0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Layout (0x0002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Layout (0x9400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Layout (0x9401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Layout (0x9402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Layout (0x9403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Layout (0x3400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Layout (0x3401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Layout (0x4400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Layout (0x4401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Layout (0x4402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38 41 46 48 49 51 52 53 55 56 58 60 61 64 66 68 69 70 70 71 72 73 74 74 75 85 87 88 90 91 92 93 93 95 96 97

SPRS206K

December 2002 Revised November 2008

Figures

Figure 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 51 52 53 54 55 56 57 58 59 510 511 512 513 514 515 516 517 518 519 520 521 522 Parallel GPIO Enable Register 1 Layout (0x4403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Layout (0x4404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Layout (0x4405) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 2 Layout (0x4406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Layout (0x4407) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Layout (0x4408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Layout (0x8800) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Layout (0x0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Layout (0x0102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Layout (0x0200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Layout (0x0202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Layout (0x0302) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Layout (0x07FD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Layout (0x9000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR0, IER0, DBIFR0, and DBIER0 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR1, IER1, DBIFR1, and DBIER1 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bad TCK Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Good TCK Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Noise Filtering Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass Mode Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Multiply-by-N Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKIN Timings for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT1 Timings for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT2 Timings for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Read Timings (With Read Latency = 2) . . . . . . . . . . . . . . . . Programmable Synchronous Interface Write Timings (With Write Latency = 0) . . . . . . . . . . . . . . . . Programmable Synchronous Interface Write Timings (With Write Latency = 1) . . . . . . . . . . . . . . . . SDRAM Read Command (CAS Latency 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DEAC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Self-Refresh Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF.HOLD/HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 98 99 100 101 102 103 105 107 108 109 110 111 112 113 130 131 133 133 134 139 140 142 144 145 145 146 148 149 151 152 153 154 155 155 156 156 157 157 158 159 161

December 2002 Revised November 2008

SPRS206K

Figures

Figure 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Acknowledge Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output (GPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel General-Purpose Input/Output (PGPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings Using HPI.HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings With HPI.HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings Using HPI.HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings With HPI.HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HINT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI.HAS Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 162 162 163 164 165 166 166 167 168 171 171 172 174 175 177 178 181 182 183 184 184 185 186 187 188 189

10

SPRS206K

December 2002 Revised November 2008

Tables

List of Tables
Table 21 22 23 24 31 32 33 34 35 36 37 38 39 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations . . . . . . . . . . . . . . . . . . . . . . . . . 201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Configuration Selection Via the BOOTM[2:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 Routing of Parallel Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 Routing of Host Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clocks Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 3 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Reference Clock Cycles Needed Until Program Flow Begins . . . . . . . . . . . . . . . . . . . . . Peripheral Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Domain Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 PGPIO Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17 18 20 21 39 40 42 44 45 47 53 59 62 63 66 67 68 69 70 71 71 72 73 74 75 75 76 80 83 84 85 87 88 90 91 92 93 93 94 95 96 97 98 99 100

December 2002 Revised November 2008

SPRS206K

11

Tables

Table 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 51 52 53 54 55 56 57 58 59 510 511 512 Parallel GPIO Enable Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins With Pullups, Pulldowns, and Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Addresses Under Scope of XPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Bypass Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Bypass Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Lock Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Lock Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Cycle Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 101 102 103 104 105 106 107 108 109 110 111 112 113 114 116 117 118 121 121 121 121 123 124 125 125 126 126 127 127 127 127 128 128 129 140 142 142 143 143 145 145 146 147 147 150 150

12

SPRS206K

December 2002 Revised November 2008

Tables

Table 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 61 62 Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF.HOLD/HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF.HOLD/HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Switching Characteristics . . . . . . . . . . . . . . . . . . . . . XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics . . . . . . . . TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . HPI Read and Write Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Read and Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI.HAS Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 154 154 159 159 160 160 162 162 163 164 164 165 165 166 166 167 167 168 169 170 172 172 173 173 175 175 176 176 178 178 179 180 185 185 186 187 188 189 189 190 191

December 2002 Revised November 2008

SPRS206K

13

Tables

14

SPRS206K

December 2002 Revised November 2008

Features

TMS320VC5501 Features
D High-Performance, Low-Power, Fixed-Point
TMS320C55x Digital Signal Processor (DSP) 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate 16K-Byte Instruction Cache (I-Cache) One/Two Instructions Executed per Cycle Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)] Two Arithmetic/Logic Units (ALUs) One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses Instruction Cache (16K Bytes) 16K x 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K 16-Bit Dual-Access RAM (DARAM) (32K Bytes) 16K 16-Bit One-Wait-State On-Chip ROM (32K Bytes) 8M 16-Bit Maximum Addressable External Memory Space 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to: Asynchronous Static RAM (SRAM) Asynchronous EPROM Synchronous DRAM (SDRAM) Synchronous Burst RAM (SBRAM) Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values

D Programmable Low-Power Control of Six D

Device Functional Domains On-Chip Peripherals Six-Channel Direct Memory Access (DMA) Controller Two Multichannel Buffered Serial Ports (McBSPs) Programmable Analog Phase-Locked Loop (APLL) Clock Generator General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF) 8-Bit Parallel Host-Port Interface (HPI) Four Timers Two 64-Bit General-Purpose Timers 64-Bit Programmable Watchdog Timer 64-Bit DSP/BIOS Counter Inter-Integrated Circuit (I2C) Interface Universal Asynchronous Receiver/ Transmitter (UART) On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Packages: 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix) 201-Terminal MicroStar BGA (Ball Grid Array) (GZZ and ZZZ Suffixes) 3.3-V I/O Supply Voltage 1.26-V Core Supply Voltage

D D D D D

D D D

D D

TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. 15

December 2002 Revised November 2008

SPRS206K

Introduction

Introduction
This section describes the main features of the TMS320VC5501 and gives a brief description of the device.
NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

2.1

Description
The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5501 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Two full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is an 8-bit parallel interface used to provide host processor access to 16K words of internal memory on the 5501. The HPI operates in multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included. The 5501 is supported by the industrys award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments algorithm standard, and the industrys largest third-party network. The Code Composer Studio IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX, XDS510 emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments. 16

SPRS206K

December 2002 Revised November 2008

Introduction

2.2

Pin Assignments

2.2.1 Ball Grid Array (GZZ and ZZZ)

The TMS320VC5501 is offered in two 201-terminal ball grid array (BGA) packages, both of which include 25 thermal balls to improve thermal dissipation. Except for their Eco-Status (refer to Section 6.2, Packaging Information), both packages are essentially the same. Figure 21 illustrates the ball locations for both BGA packages. Table 21 lists the locations of the thermal balls and Table 22 lists the signal names and terminal numbers. NOTE: Some TMX samples were shipped in the GGW package. For more information on the GGW package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number SPRZ020D or later).

U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17

10

12

14

16

Figure 21. 201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View)

Table 21. 201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations
BALL NO. G7 H7 J7 K7 BALL NO. G8 H8 J8 K8 BALL NO. G9 H9 J9 K9 BALL NO. G10 H10 J10 K10 BALL NO. G11 H11 J11 K11

L7 L8 L9 L10 L11 For best device thermal performance: An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted. The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability Temperature Cycle performance. The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be connected to the ground plane for heat dissipation. A solid internal plane is preferred for spreading the heat. Refer to the MicroStar BGAE Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount, and reliability considerations.

December 2002 Revised November 2008

SPRS206K

17

Introduction

Table 22. 201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments
BALL NO. B1 C2 C1 D3 D2 D1 E3 E2 E1 F3 F2 F1 G4 G3 G2 G1 H1 H4 H3 H2 J1 J4 J3 J2 K1 K2 K4 K3 L1 L2 L3 L4 M1 M2 M3 N1 N2 N3 P1 P2 P3 R1 R2 T1 SIGNAL NAME GPIO6 GPIO4 GPIO2 GPIO1 GPIO0 TIM1 TIM0 INT0 CVDD INT1 INT2 DVDD INT3 NMI/WDTOUT IACK VSS CLKR0 DR0 FSR0 CLKX0 CVDD DX0 FSX0 CLKR1 DR1 FSR1 DX1 CLKX1 VSS FSX1 TEST NC CVDD RX GPIO5 DVDD TX GPIO3 VSS SCL SDA HC1 HC0 HCS BALL NO. U2 T3 U3 R4 T4 U4 R5 T5 U5 R6 T6 U6 P7 R7 T7 U7 U8 P8 R8 T8 U9 P9 R9 T9 U10 T10 P10 R10 U11 T11 R11 P11 U12 T12 R12 U13 T13 R13 U14 T14 R14 U15 T15 U16 SIGNAL NAME HCNTL1 HCNTL0 VSS HR/W HDS2 CVDD HDS1 HRDY DVDD CLKOUT XF VSS C15 C14 HINT PVDD NC X1 X2/CLKIN EMIFCLKS VSS C13 C12 C11 C10 C9 C8 C7 VSS ECLKIN ECLKOUT2 ECLKOUT1 CVDD C6 C5 DVDD C4 C3 VSS C2 C1 C0 A21 A20 BALL NO. T17 R16 R17 P15 P16 P17 N15 N16 N17 M15 M16 M17 L14 L15 L16 L17 K17 K14 K15 K16 J17 J14 J15 J16 H17 H16 H14 H15 G17 G16 G15 G14 F17 F16 F15 E17 E16 E15 D17 D16 D15 C17 C16 B17 SIGNAL NAME A19 A18 VSS A17 A16 DVDD A15 A14 VSS A13 A12 CVDD A11 A10 A9 A8 DVDD A7 A6 A5 VSS A4 A3 A2 CVDD D31 D30 D29 VSS D28 D27 D26 CVDD D25 D24 DVDD D23 D22 D21 D20 D19 VSS D18 D17 BALL NO. A16 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 A12 D11 C11 B11 A11 A10 D10 C10 B10 A9 D9 C9 B9 A8 B8 D8 C8 A7 B7 C7 D7 A6 B6 C6 A5 B5 C5 A4 B4 C4 A3 B3 A2 SIGNAL NAME D16 D15 D14 D13 D12 D11 D10 D9 DVDD D8 D7 VSS D6 D5 D4 CVDD D3 D2 D1 D0 VSS EMU1/OFF EMU0 TDO VSS TDI TRST TCK TMS RESET HPIENA HD7 CVDD HD6 HD5 DVDD HD4 HD3 CVDD HD2 HD1 VSS HD0 GPIO7

CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . NC indicates no connect. The TEST pin is reserved for internal testing. It should be left unconnected. The GPIO7 pin must be low at the rising edge of the reset signal for the device to operate properly.

18

SPRS206K

December 2002 Revised November 2008

Introduction

2.2.2 Low-Profile Quad Flatpack (PGF)

The TMS320VC5501 is offered in a 176-pin low-profile quad flatpack (LQFP). Figure 22 illustrates the pin locations for the 176-pin LQFP. Table 23 lists the signal names and pin numbers. NOTE: TMS320VC5501PGF has completed Temp Cycle reliability qualification testing with no failures through 1500 cycles of 55C to 125C following an EIA/JEDEC Moisture Sensitivity Level 4 pre-condition at 220+5/0C peak reflow. Exceeding this peak reflow temperature condition or storage and handling requirements may result in either immediate device failure post-reflow, due to package/die material delamination (popcorning), or degraded Temp cycle life performance. Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life information on a bar-code label affixed to dry-pack shipping bags. Shelf life, temperature and humidity storage conditions and re-bake instructions are prominently displayed on a nearby screen-printed label.

132

89

133

88

176

45

44

Figure 22. 176-Pin PGF Low-Profile Quad Flatpack (Top View)

December 2002 Revised November 2008

SPRS206K

19

Introduction

Table 23. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments

PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SIGNAL NAME GPIO6 GPIO4 GPIO2 GPIO1 GPIO0 TIM1 TIM0 INT0 CVDD INT1 INT2 DVDD INT3 NMI/WDTOUT IACK VSS CLKR0 DR0 FSR0 CLKX0 CVDD DX0 FSX0 CLKR1 DR1 FSR1 DX1 CLKX1 VSS FSX1 TEST NC CVDD RX GPIO5 DVDD TX GPIO3 VSS SCL SDA HC1 HC0 HCS PIN NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SIGNAL NAME HCNTL1 HCNTL0 VSS HR/W HDS2 CVDD HDS1 HRDY DVDD CLKOUT XF VSS C15 C14 HINT PVDD NC X1 X2/CLKIN EMIFCLKS VSS C13 C12 C11 C10 C9 C8 C7 VSS ECLKIN ECLKOUT2 ECLKOUT1 CVDD C6 C5 DVDD C4 C3 VSS C2 C1 C0 A21 A20 PIN NO. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 SIGNAL NAME A19 A18 VSS A17 A16 DVDD A15 A14 VSS A13 A12 CVDD A11 A10 A9 A8 DVDD A7 A6 A5 VSS A4 A3 A2 CVDD D31 D30 D29 VSS D28 D27 D26 CVDD D25 D24 DVDD D23 D22 D21 D20 D19 VSS D18 D17 PIN NO. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 SIGNAL NAME D16 D15 D14 D13 D12 D11 D10 D9 DVDD D8 D7 VSS D6 D5 D4 CVDD D3 D2 D1 D0 VSS EMU1/OFF EMU0 TDO VSS TDI TRST TCK TMS RESET HPIENA HD7 CVDD HD6 HD5 DVDD HD4 HD3 CVDD HD2 HD1 VSS HD0 GPIO7

CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . NC indicates no connect. The TEST pin is reserved for internal testing. It should be left unconnected. The GPIO7 pin must be low at the rising edge of the reset signal for the device to operate properly.

20

SPRS206K

December 2002 Revised November 2008

Introduction

2.3

Signal Descriptions

Table 24 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin Assignments, for exact pin locations based on package type.

Table 24. Signal Descriptions

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Address Bus The A[21:18] pins of the Parallel Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[3:0] or external memory interface (EMIF) address bus signals EMIF.A[21:18]. The function of the A[21:18] pins is determined by the state of the GPIO6 pin during reset. The A[21:18] pins are set to PGPIO[3:0] if GPIO6 is low during reset. The A[21:18] pins are set to EMIF.A[21:18] if GPIO6 is high during reset. The function of the A[21:18] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The A[21:18] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Parallel general-purpose I/O. PGPIO[3:0] is selected if GPIO6 is low during reset. The PGPIO[3:0] signals are configured as inputs after reset. EMIF address bus. EMIF.A[21:18] is selected if GPIO6 is high during reset. The EMIF.A[21:18] signals are in a high-impedance state during reset and are configured as outputs after reset with an output value of 0. The A[17:2] pins of the Parallel Port serve one of two functions: external memory interface (EMIF) address bus signals EMIF.A[17:2] or reserved pins. The function of the A[17:2] pins is determined by the state of the GPIO6 pin during reset. The A[17:2] pins are reserved if GPIO6 is low during reset. The A[17:2] pins are set to EMIF.A[17:2] if GPIO6 is high during reset. The function of the A[17:2] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The A[17:2] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Reserved pins. These pins are reserved when GPIO6 is low during reset. EMIF address bus. EMIF.A[17:2] is selected when GPIO6 is high during reset. The EMIF.A[17:2] signals are in a high-impedance state during reset and are configured as outputs after reset with an output value of 0. Function

A[21:18]

I/O/Z C, D, E, F, G, H, M

PGPIO[3:0]

I/O/Z

EMIF.A[21:18]

O/Z

A[17:2]

I/O/Z C, D, E, F, M

Reserved EMIF.A[17:2]

I O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

21

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Data Bus The D[31:16] pins of the Parallel Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[19:4] or external memory interface (EMIF) data bus signals EMIF.D[31:16]. The function of the D[31:16] pins is determined by the state of the GPIO6 pin during reset. The D[31:16] pins are set to PGPIO[19:4] if GPIO6 is low during reset. The D[31:16] pins are set to EMIF.D[31:16] if GPIO6 is high during reset. The function of the D[31:16] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The D[31:16] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the data bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during reset. The PGPIO[19:4] signals are configured as inputs after reset. EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The EMIF.D[31:16] signals are set as inputs after reset. The D[15:0] pins of the Parallel Port serve one of two functions: external memory interface (EMIF) data bus signals EMIF.D[15:0] or reserved pins. The function of the D[15:0] pins is determined by the state of the GPIO6 pin during reset. The D[15:0] pins are reserved if GPIO6 is low during reset. The D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during reset. The function of the D[15:0] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The D[15:0] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the data bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Reserved pins. These pins are reserved when GPIO6 is low during reset. EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The EMIF.D[15:0] signals are configured as inputs after reset. Function

D[31:16]

I/O/Z C, D, E, F, G, H, M

PGPIO[19:4] EMIF.D[31:16]

I/O/Z I/O/Z

D[15:0]

I/O/Z C, D, E, F, M

Reserved EMIF.D[15:0]

I/O/Z I/O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

22

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Control Pins The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO20 or external memory interface control signal EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 if GPIO6 is low during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high during reset. The function of the C0 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, D, E, F, G, H, M Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during reset. The PGPIO20 signal is configured as an input after reset. EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary Control Register 1). The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO21 or external memory interface control signal EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of the GPIO6 pin during reset. The C1 pin is set to PGPIO21 if GPIO6 is low during reset. The C1 pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset. The function of the C1 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO21 is selected when GPIO6 is low during reset. The PGPIO21 signal is configured as an input after reset. EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during reset. The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by the EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS). Function

C0

I/O/Z

PGPIO20

I/O/Z

EMIF.ARE/SADS/ SDCAS/SRE

O/Z

C1

I/O/Z

PGPIO21

I/O/Z

C, D, E, F, G, H, M

EMIF.AOE/SOE/ SDRAS

O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

23

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Control Pins (Continued) The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO22 or external memory interface control signal EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the GPIO6 pin during reset. The C2 pin is set to PGPIO22 if GPIO6 is low during reset. The C2 pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The function of the C2 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO22 is selected when GPIO6 is low during reset. The PGPIO22 signal is configured as an input after reset. EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during reset. The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.AWE/SWE/SDWE signal serves three different functions when used by the EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE). The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO23 or external memory interface control signal EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin during reset. The C3 pin is set to PGPIO23 if GPIO6 is low during reset. The C3 pin is set to EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, J Parallel general-purpose I/O. PGPIO23 is selected when GPIO6 is low during reset. The PGPIO23 signal is configured as an input after reset. EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset. The EMIF.ARDY signal indicates that an external device is ready for a bus transaction to be completed. If the device is not ready (EMIF.ARDY is low), the processor extends the memory access by one cycle and checks EMIF.ARDY again. An internal pullup is included to disable this feature if not used. The internal pullup can be disabled through the External Bus Control Register (XBCR). Function

C2

I/O/Z

PGPIO22

I/O/Z

C, D, E, F, G, H, M

EMIF.AWE/ SWE/SDWE

O/Z

C3

I/O/Z

PGPIO23

I/O/Z

EMIF.ARDY

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

24

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Control Pins (Continued) The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO24 or external memory interface control signal EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin during reset. The C4 pin is set to PGPIO24 if GPIO6 is low during reset. The C4 pin is set to EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO24 is selected when GPIO6 is low during reset. The PGPIO24 signal is configured as an input after reset. EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is high during reset. The EMIF.CE0 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO25 or external memory interface control signal EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin during reset. The C5 pin is set to PGPIO25 if GPIO6 is low during reset. The C5 pin is set to EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO25 is selected when GPIO6 is low during reset. The PGPIO25 signal is configured as an input after reset. EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is high during reset. The EMIF.CE1 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO26 or external memory interface control signal EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin during reset. The C6 pin is set to PGPIO26 if GPIO6 is low during reset. The C6 pin is set to EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO26 is selected when GPIO6 is low during reset. The PGPIO26 signal is configured as an input after reset. EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is high during reset. The EMIF.CE2 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. Function

C4

I/O/Z C, D, E, F, G, H, M

PGPIO24

I/O/Z

EMIF.CE0

O/Z

C5

I/O/Z C, D, E, F, G, H, M

PGPIO25

I/O/Z

EMIF.CE1

O/Z

C6

I/O/Z C, D, E, F, G, H, M

PGPIO26

I/O/Z

EMIF.CE2

O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

25

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Control Pins (Continued) The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO27 or external memory interface control signal EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin during reset. The C7 pin is set to PGPIO27 if GPIO6 is low during reset. The C7 pin is set to EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO27 is selected when GPIO6 is low during reset. The PGPIO27 signal is configured as an input after reset. EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is high during reset. The EMIF.CE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO28 or external memory interface control signal EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin during reset. The C8 pin is set to PGPIO28 if GPIO6 is low during reset. The C8 pin is set to EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO28 is selected when GPIO6 is low during reset. The PGPIO28 signal is configured as an input after reset. EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high during reset. The EMIF.BE0 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO29 or external memory interface control signal EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin during reset. The C9 pin is set to PGPIO29 if GPIO6 is low during reset. The C9 pin is set to EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO29 is selected when GPIO6 is low during reset. The PGPIO29 signal is configured as an input after reset. EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high during reset. The EMIF.BE1 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. Function

C7

I/O/Z C, D, E, F, G, H, M

PGPIO27

I/O/Z

EMIF.CE3

O/Z

C8

I/O/Z C, D, E, F, G, H, M

PGPIO28

I/O/Z

EMIF.BE0

O/Z

C9

I/O/Z C, D, E, F, G, H, M

PGPIO29

I/O/Z

EMIF.BE1

O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

26

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Control Pins (Continued) The C10 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO30 or external memory interface control signal EMIF.BE2. The function of the C10 pin is determined by the state of the GPIO6 pin during reset. The C10 pin is set to PGPIO30 if GPIO6 is low during reset. The C10 pin is set to EMIF.BE2 if GPIO6 is high during reset. The function of the C10 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO30 is selected when GPIO6 is low during reset. The PGPIO30 signal is configured as an input after reset. EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high during reset. The EMIF.BE2 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C11 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO31 or external memory interface control signal EMIF.BE3. The function of the C11 pin is determined by the state of the GPIO6 pin during reset. The C11 pin is set to PGPIO31 if GPIO6 is low during reset. The C11 pin is set to EMIF.BE3 if GPIO6 is high during reset. The function of the C11 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO31 is selected when GPIO6 is low during reset. The PGPIO31 signal is configured as an input after reset. EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high during reset. The EMIF.BE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C12 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO32 or external memory interface control signal EMIF.SDCKE. The function of the C12 pin is determined by the state of the GPIO6 pin during reset. The C12 pin is set to PGPIO32 if GPIO6 is low during reset. The C12 pin is set to EMIF.SDCKE if GPIO6 is high during reset. The function of the C12 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO32 is selected when GPIO6 is low during reset. The PGPIO32 signal is configured as an input after reset. EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during reset. The EMIF.SDCKE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. Function

C10

I/O/Z C, D, E, F, G, H, M

PGPIO30

I/O/Z

EMIF.BE2

O/Z

C11

I/O/Z C, D, E, F, G, H, M

PGPIO31

I/O/Z

EMIF.BE3

O/Z

C12

I/O/Z C, D, E, F, G, H, M

PGPIO32

I/O/Z

EMIF.SDCKE

O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

27

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Parallel Port Control Pins (Continued) The C13 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO33 or external memory interface control signal EMIF.SOE3. The function of the C13 pin is determined by the state of the GPIO6 pin during reset. The C13 pin is set to PGPIO33 if GPIO6 is low during reset. The C13 pin is set to EMIF.SOE3 if GPIO6 is high during reset. The function of the C13 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO33 is selected when GPIO6 is low during reset. The PGPIO33 signal is configured as an input after reset. EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.SOE3 signal is intended for glueless FIFO interface. The C14 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO34 or external memory interface control signal EMIF.HOLD. The function of the C14 pin is determined by the state of the GPIO6 pin during reset. The C14 pin is set to PGPIO34 if GPIO6 is low during reset. The C14 pin is set to EMIF.HOLD if GPIO6 is high during reset. The function of the C14 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO34 is selected when GPIO6 is low during reset. The PGPIO34 signal is configured as an input after reset. EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset. EMIF.HOLD is asserted by an external host to request control of the address, data, and control signals. The C15 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO35 or external memory interface control signal EMIF.HOLDA. The function of the C15 pin is determined by the state of the GPIO6 pin during reset. The C15 pin is set to PGPIO35 if GPIO6 is low during reset. The C15 pin is set to EMIF.HOLDA if GPIO6 is high during reset. The function of the C15 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, D, F, G, H, M Parallel general-purpose I/O. PGPIO35 is selected when GPIO6 is low during reset. The PGPIO35 signal is configured as an input after reset. EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during reset. The EMIF.HOLDA signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state and that the EMIF address, data, and control signals are in a high-impedance state, allowing the external memory interface to be accessed by other devices. Function

C13

I/O/Z C, D, E, F, G, H, M

PGPIO33

I/O/Z

EMIF.SOE3

O/Z

C14

I/O/Z F, G, H, J, M

PGPIO34

I/O/Z

EMIF.HOLD

C15

I/O/Z

PGPIO35

I/O/Z

EMIF.HOLDA

O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

28

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other EMIF Clock Pins ECLKIN I C, L External EMIF input clock. ECLKIN is selected as the input clock to the EMIF when EMIFCLKS is high. EMIF output clock. ECLKOUT1 outputs the EMIF input clock by default but can be held low or set to a high-impedance state through the EMIF Global Control Register 1 (EGCR1). The ECLKOUT1 pin is always in a high-impedance state during reset. The behavior of ECLKOUT1 immediately after reset depends on the state of GPIO6 during reset and EMIFCLKS: GPIO6 0 0 1 1 EMIFCLKS 0 1 0 1 ECLKOUT1 Behavior Pin is in a high-impedance state. Pin toggles at ECLKIN frequency. Pin toggles at SYSCLK3 frequency. Pin toggles at ECLKIN frequency. Function

ECLKOUT1

O/Z

E, F, M

EMIF output clock. ECLKOUT2 can be enabled to output the EMIF input clock divided by a factor 1, 2, or 4 through the EMIF Global Control Register 2 (EGCR2). ECLKOUT2 can also be held low or set to a high-impedance state through the EGCR2 register. The ECLKOUT2 pin toggles with a clock frequency equal to the EMIF input clock divided by 4 during reset. The behavior of ECLKOUT2 immediately after reset depends on the state of GPIO6 during reset and EMIFCLKS: GPIO6 0 0 1 1 EMIFCLKS I C, L EMIFCLKS 0 1 0 1 ECLKOUT2 Behavior Pin is held low. Pin toggles at one-fourth of the ECLKIN frequency. Pin toggles at one-fourth of the SYSCLK3 frequency. Pin toggles at one-fourth of the ECLKIN frequency.

ECLKOUT2

O/Z

E, F

EMIF input clock source select. The clock source for the EMIF is determined by the state of the EMIFCLKS pin. The EMIF uses an internal clock (SYSCLK3) if EMIFCLKS is low. ECLKIN is used as the clock source if EMIFCLKS is high.

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

29

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Host Port Data Bus The HD[7:0] pins of the Host Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[43:36] or host-port interface (HPI) data bus signals HPI.HD[7:0]. The function of the HD[7:0] pins is determined by the state of the GPIO6 pin during reset. The HD[7:0] pins are set to PGPIO[43:36] if GPIO6 is low during reset. The HD[7:0] pins are set to HPI.HD[7:0] if GPIO6 is high during reset. The function of the HD[7:0] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The HD[7:0] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Parallel general-purpose I/O. PGPIO[43:36] is selected when GPIO6 is low during reset. The PGPIO[43:36] signals are configured as inputs after reset. Host data bus. HPI.HD[7:0] is selected when GPIO6 is high during reset. The HPI.HD[7:0] signals are configured as inputs after reset. The HPI will operate in multiplexed mode when GPIO6 is high during reset. In multiplexed mode, an 8-bit data bus (HPI.HD[7:0]) carries both address and data. Each host cycle on the bus consists of two consecutive 8-bit transfers. Host Port Control Pins The HC0 pin of the Host Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO44 or host-port interface (HPI) signal HPI.HAS. The function of the HC0 pin is determined by the state of the GPIO6 pin during reset. The HC0 pin is set to PGPIO44 if GPIO6 is low during reset. The HC0 pin is set to HPI.HAS if GPIO6 is high during reset. The function of the HC0 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, F, G, H, J Parallel general-purpose I/O. PGPIO44 is selected when GPIO6 is low during reset. The PGPIO44 signal is configured as an input after reset. Host address strobe. HPI.HAS is selected when GPIO6 is high during reset. The HPI.HAS signal is configured as an input after reset. Hosts with multiplexed address and data pins may require HPI.HAS to latch the address in the HPIA register. HPI.HAS is only available when the HPI is operating in multiplexed mode. Function

HD[7:0]

I/O/Z

C, D, F, G, H PGPIO[43:36] I/O/Z

HPI.HD[7:0]

I/O/Z

HC0

I/O/Z

PGPIO44

I/O/Z

HPI.HAS

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

30

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Host Port Control Pins (Continued) The HC1 pin of the Host Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO45 or host-port interface (HPI) signal HPI.HBIL. The function of the HC1 pin is determined by the state of the GPIO6 pin during reset. The HC1 pin is set to PGPIO45 if GPIO6 is low during reset. The HC1 pin is set to HPI.HBIL if GPIO6 is high during reset. The function of the HC1 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO45 is selected when GPIO6 is low during reset. The PGPIO45 signal is configured as an input after reset. Host byte identification. HPI.HBIL is selected when GPIO6 is high during reset. The HPI.HBIL signal is configured as an input after reset. In multiplexed mode, the host must use HPI.HBIL to identify the first and second bytes of the host cycle. HPI Pins HCNTL0 I/O/Z HCNTL1 F, G, H, J HPI access control pins. The four binary states of the HCNTL0 and HCNTL1 pins determine which HPI register is being accessed by the host (HPIC, HPID with autoincrementing, HPIA, or HPID). The HCNTL0 and HCNTL1 pins are configured as inputs after reset. HPI chip-select. HCS must be low for the HPI to be selected by the host. The HCS pin is configured as an input after reset. A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.7, Host-Port Interface (HPI), for more details. Host read- or write-select. HR/W indicates whether the current access is to be a read or write operation. The HR/W pin is configured as an input after reset. Host data strobe pins. The HDS1 and HDS2 pins are used for strobing data in and out of the HPI. The HDS1 and HDS2 pins are configured as inputs after reset. A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.7, Host-Port Interface (HPI), for more details. Host ready (from DSP to host). The HRDY pin informs the host when the HPI is ready for the next transfer. The HRDY pin is in a high-impedance state during reset and is set to output after reset with an output value of 1. Function

HC1

I/O/Z

PGPIO45

I/O/Z

F, G, H, K

HPI.HBIL

HCS

I/O/Z

C, F, G, H, J F, G, H, J C, G, H, J

HR/W HDS1

I/O/Z

I HDS2

HRDY

O/Z

F, J, M

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

31

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other HPI Pins (Continued) HINT O/Z F, G, H, J, M Host interrupt (from DSP to host). The HINT pin is used by the DSP to interrupt the host. The HINT signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. HPI enable. The HPIENA pin must be dreiven high to enable the HPI for operation. If the HPIENA pin is low, the HPI will be completely disabled and all HPI output pins will be in a high-impedance state. If the HPI is not needed, the HPIENA pin can be pulled low. Interrupt and Reset Pins Maskable external interrupts. INT0INT3 are maskable interrupts.They are enabled through the Interrupt Enable Registers (IER0 and IER1). All maskable interrupts are globally enabled/disabled through the Interrupt Mode bit (INTM in ST1_55). INT0INT3 can be polled and reset via the Interrupt Flag Registers (IFR0 and IFR1). All interrupts are prioritized as shown in Table 375, Interrupt Table. Non-maskable external interrupt or Watchdog Timer output. The function of this pin is controlled by the Timer Signal Selection Register (TSSR). By default, the NMI/WDTOUT pin has the function of the NMI signal. NMI is an external interrupt that cannot be masked by the Interrupt Enable Registers (IER0 and IER1). When NMI is activated, the interrupt is always performed. WDTOUT serves as an input and output pin for the Watchdog Timer. IACK O/Z F, M Interrupt acknowledge. IACK indicates the receipt of an interrupt and that the program counter is fetching the interrupt vector location designated on the address bus. The IACK pin is set to a value of 1 during reset. Device reset. RESET causes the digital signal processor (DSP) to terminate current program execution. When RESET is brought to a high level, program execution begins by fetching the reset interrupt service vector at the reset vector address FFFF00h (IVPD:FFFFh). RESET affects various registers and status bits. Function

HPIENA

C, L

INT[3:0]

C, L

NMI/WDTOUT

I/O/Z

C, F, J, M

RESET

C, L

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

32

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other General-Purpose I/O Pins General-purpose configurable inputs/outputs. GPIO[7:0] can be individually configured as inputs or outputs via the GPIO Direction Register (IODIR). Data can be read from inputs or written to outputs via the GPIO Data Register (IODATA). The GPIO pins are configured as inputs after reset. NOTE: the GPIO7 pin must be low during the rising edge of the reset signal for the device to operate properly. Boot mode selection signals. GPIO[2:0]/BOOTM[2:0] are sampled following reset to configure the boot mode for the DSP. After the boot is completed, these pins can be used as general-purpose inputs/outputs. The GPIO4 pin is also used as an output for handshaking purposes on some of the boot modes. Although this pin is not involved in boot mode selection, users should be aware that this pin will become active as an output during the boot-load process and should design accordingly. After the boot-load process is complete, the loaded application may change the function of the GPIO4 pin. Input clock source selection. The CLKMD0 bit of the Clock Mode Control Register (CLKMD) determines which clock, either OSCOUT or X2/CLKIN, is used as an input clock source to the DSP. If GPIO4 is low at reset, the CLKMD0 bit of the Clock Mode Control Register (CLKMD) will be set to 0 and the internal oscillator and the external crystal will generate an input clock (OSCOUT) for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and the input clock will be taken directly from the X2/CLKIN pin. An external crystal must be attached to the X1 and X2/CLKIN pins when the internal oscillator is used to generate a clock to the DSP. Otherwise, when the oscillator is not used to generate the input clock for the DSP, an externally generated 3.3-V clock must be applied to the X2/CLKIN pin and the X1 pin must be left unconnected. Function selection for multiplexed pins. The GPIO6 pin is used to select the function of the multiplexed signals in the Parallel Port and the Host Port. The 5501 will be configured in PGPIO mode (EMIF and HPI are disabled) when the GPIO6 pin is low during reset. The 5501 will be configured in EMIF/HPI mode when the GPIO6 pin is high during reset. The function of the multiplexed signals will be set once the device is taken out of reset (RESET pin transitions from a low to high state). External output (latched software-programmable signal). XF is set high by the BSET XF instruction, set low by BCLR XF instruction, or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. The XF pin is set to a value of 1 during reset. Function

GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2/BOOTM2 GPIO1/BOOTM1 GPIO0/BOOTM0

I/O/Z

F, G, H, M

XF

O/Z

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

33

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Oscillator/Clock Pins Clock output. CLKOUT can be set to reflect the clock of the Fast Peripherals Clock Group, Slow Peripherals Clock Group, and the External Memory Interface Clock Group. The CLKOUT pin is set to the internal clock SYSCLK1 during and after reset. SYSCLK1 is set equal to a divided-by-four CLKIN or OSCOUT (depending on the state of the GPIO4 pin) during and after reset. SYSCLK1 is used to clock the Fast Peripheral Clock Group. Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. Multichannel Buffered Serial Port Pins CLKR0 DR0 FSR0 CLKX0 DX0 FSX0 CLKR1 DR1 FSR1 DX1 CLKX1 FSX1 I/O/Z I I/O/Z I/O/Z O/Z I/O/Z I/O/Z I I/O/Z O/Z I/O/Z I/O/Z C, F, G, H, M L, G F, G, H, M C, F, G, H, M F, H, M F, G, H, M C, G, H, M L, G F, G, H, M F, H, M C, F, G, H, M F, G, H, M Receive clock input of McBSP0. The CLKR0 pin is configured as input after reset. Serial data receive input of McBSP0 Frame synchronization pulse for receive input of McBSP0. The FSR0 pin is configured as input after reset. Transmit clock of McBSP0. The CLKX0 pin is configured as input after reset. Serial data transmit output of McBSP0. The DX0 pin is in a high-impedance state during and after reset. Frame synchronization pulse for transmit output of McBSP0. The FSX0 pin is configured as input after reset. Receive clock input of McBSP1. The CLKR1 pin is configured as input after reset. Serial data receive input of McBSP1 Frame synchronization pulse for receive input of McBSP1. The FSR1 pin is configured as input after reset. Serial data transmit output of McBSP1. The DX1 pin is in a high-impedance state during and after reset. Transmit clock of McBSP1. The CLKX1 pin is configured as input after reset. Frame synchronization pulse for transmit output of McBSP1. The FSX1 pin is configured as input after reset. Function

CLKOUT

O/Z

X2/CLKIN X1

I O

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

34

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other UART Pins TX RX SCL SDA O I I/O/Z I/O/Z C, F, M C, F, M UART transmit data output. The UART.TX signal outputs a value of 1 during and after reset. UART receive data input I2C Pins I2C clock bidirectional port. (Open collector I/O) I2C data bidirectional port. (Open collector I/O) Timer Pins Input/Output pin for Timer 0. The TIM0 pin can be configured as an output or an input via the Timer Signal Selection Register (TSSR).When configured as an output, the TIM0 pin can signal a pulse or a change of state when the Timer 0 count matches its period. When configured as an input, the TIM0 pin can be used to provide the clock source for Timer 0 (external clock source mode) or it can be used to start/stop the timer from counting (clock gating mode). This pin can also be used as general-purpose I/O. The TIM0 pin is configured as an input after reset. Input/Output pin for Timer 1. The TIM1 pin can be configured as an output or an input via the Timer Signal Selection Register (TSSR).When configured as an output, the TIM1 pin can signal a pulse or a change of state when the Timer 1 count matches its period. When configured as an input, the TIM1 pin can be used to provide the clock source for Timer 1 (external clock source mode) or it can be used to start/stop the timer from counting (clock gating mode). This pin can also be used as general-purpose I/O. The TIM1 pin is configured as an input after reset. Supply Pins VSS CVDD PVDD NC S S S Digital Ground. Dedicated ground for the device. Digital Power, + VDD. Dedicated power supply for the core CPU. Digital Power, + VDD. Dedicated power supply for the PLL module. No Connect Function

TIM0

I/O/Z

F, G, H, M

TIM1

I/O/Z

F, G, H, M

DVDD S Digital Power, + VDD. Dedicated power supply for the I/O pins. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

December 2002 Revised November 2008

SPRS206K

35

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Test Pins IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. Refer to Section 3.17, Notice Concerning TCK, for important information regarding this pin. IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. J IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin has an internal pulldown device. Function

TCK

C, J

TDI

TDO

O/Z

TMS

TRST

C, L, K

I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low)

36

SPRS206K

December 2002 Revised November 2008

Introduction

Table 24. Signal Descriptions (Continued)

Pin Name Multiplexed Signal Name Pin Type Other Test Pins (Continued) Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O by way of the IEEE standard 1149.1 scan system. EMU0 I/O/Z J The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not connected. Internal pullups have been included for this purpose. If the user chooses to disable these pins through the XBCR, external pullup resistors must be added to these two pins. Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as I/O by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = low, EMU0 = high, EMU1/OFF = low The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not connected. Internal pullups have been included for this purpose. If the user chooses to disable these pins through the XBCR, external pullup resistors must be added to these two pins. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A Internal pullup [always enabled] B Internal pulldown [always enabled] C Hysteresis input D Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G Pin can be configured as a general-purpose input. H PIn can be configured as a general-purpose output. J Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L Fail-safe pin M Pin is in high-impedance during reset (RESET pin is low) Function

EMU1/OFF

I/O/Z

December 2002 Revised November 2008

SPRS206K

37

38
C55x CPU Instruction Buffer Unit (IU) Program Flow Unit (PU) Address Data Flow Unit (AU) Data Computation Unit (DU) ECLKIN ECLKOUT1 ECLKOUT2 EMIFCLKS [PAB] (24) External Memory Interface (EMIF) A[21:2] D[31:0] C[15:0] Parallel Port MUX A[21:2] D[31:0] C[15:0] PGPIO[35:0] PGPIO[45:36] HD[7:0] Host Port MUX Parallel GeneralPurpose I/O HC0 HC1 Timer XPORT DARAM ROM Instruction Cache DPORT HD[7:0] HAS HBIL IPORT Host-Port Interface (HPI) Internal Memory Interface EMIF DARAM0 WDTimer DARAM1 PERI General-Purpose I/O I2C McBSP TX DR FSR CLKX DX CLKR FSX UART RX DMA Controller Timer 3 (DSP/BIOS Timer) MPORT Peripheral Controller Power Management HCNTL0 HCNTL1 HCS HR/W HDS1 HDS2 HRDY HINT HPIENA GPIO[7:0] SCL SDA

Functional Overview

The following functional overview is based on the block diagram in Figure 31.

TCK

Functional Overview

SPRS206K

TMS

TDI

TDO TRST

Emulation Control

EMU0

EMU1/OFF

Program Address Bus

Program Data Bus [PB] (32)

Data Read Address Bus B [BAB] (24)

Data Read Bus B [BB] (16)

Data Read Address Bus C [CAB] (24)

Data Read Bus C [CB] (16)

Data Read Address Bus D [DAB] (24)

Data Read Bus D [DB] (16)

Data Write Address Bus E [EAB] (24)

Data Write Bus E [EB] (16)

Data Write Address Bus F [FAB] (24)

Data Write Bus F [FB] (16)

TIM

X1 X2/CLKIN CLKOUT

Clock Generator

NMI/WDTOUT

Muxing Logic

NMI

INT3

RESET

INT3 Interrupt RESET Control

December 2002 Revised November 2008

INT[2:0]

INT[2:0]

Figure 31. TMS320VC5501 Functional Block Diagram

Functional Overview

3.1

Memory
The 5501 supports a unified memory map (program and data accesses are made to the same physical space). The total on-chip memory is 32K words (16K 16-bit words of RAM and 16K 16-bit words of ROM).

3.1.1 On-Chip ROM

TMS320VC5501 incorporates 16K x16-bit of on-chip, one-wait-state maskable ROM that can be mapped into program memory space. The on-chip ROM is located at the byte address range FF8000hFFFFFFh when MPNMC = 0 at reset. When MPNMC = 1 at reset, the on-chip ROM is disabled and not present in the memory map, and byte address range FF8000hFFFFFFh is directed to external memory space. MPNMC is a bit located in the ST3 status register, and its status is determined by the logic level on the BOOTM[2:0] pins when sampled at reset. If BOOTM[2:0] are set to 00h at reset, the MPNMC bit is set to 1 and the on-chip ROM is disabled; otherwise, the MPNMC bit is cleared to 0 and the on-chip ROM is enabled. These pins are not sampled again until the next hardware reset. The software reset instruction does not affect the MPNMC bit. Software can be used to set or clear the MPNMC bit. The ROM can be accessed by the program bus (P) and the two read data buses (C and D). The on-chip ROM is a two-cycle-per-word memory access, except for the first word access, which requires four cycles. The standard on-chip ROM contains a bootloader which provides a variety of methods to load application code automatically after power up or a hardware reset. For more information, see Section 3.1.5, Boot Configuration. A vector table associated with the bootloader is also contained in the ROM. A boot mode branch table is included in the ROM which contains hard-coded jumps to the beginning of each boot mode code section in the bootloader. A sine look-up table is provided containing 256 values (crossing 360 degrees) expressed in Q15 format. The standard on-chip ROM layout is shown in Table 31. Table 31. On-Chip ROM Layout
STARTING BYTE ADDRESS FF_8000h FF_ECAEh FF_ECB0h FF_ED00h FF_EF00h FF_FF00h CONTENTS Bootloader Program Bootloader Revision Number Boot Mode Branch Table Sine Table Reserved Interrupt Vector Table

December 2002 Revised November 2008

SPRS206K

39

Functional Overview

3.1.2 On-Chip Dual-Access RAM (DARAM)

TMS320VC5501 features 16K x 16-bit (32K bytes) of on-chip dual-access RAM. This memory enhances system performance, since the C55x CPU can access a DARAM block twice per machine cycle. The DARAM is composed of 4 blocks of 4K x 16-bit each (see Table 32). Each block in the DARAM can support two reads in one cycle, a read and a write in one cycle, or two writes in one cycle. The dual-access RAM is located in the (byte) address range 000000h007FFFh, it can be accessed by the program, data and DMA buses. The HPI has NO access to the DARAM block when device is in reset. Table 32. DARAM Blocks
BYTE ADDRESS RANGE 000000h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh MEMORY BLOCK DARAM 0 DARAM 1 DARAM 2 DARAM 3

First 192 bytes are reserved for Memory-Mapped Registers (MMRs).

3.1.3 Instruction Cache

On the TMS320VC5501, instructions may reside in internal memory or external memory. When instructions reside in external memory, the I-Cache can improve the overall system performance by buffering the most recent instructions accessed by the CPU. The 5501 includes a 16K-byte instruction cache, which consists of a single 2-way cache block. The 2-way cache uses 2-way associative mapping and holds up to 16K bytes: 512 sets, two lines per set, four 32-bit words per line. In the 2-way cache, each line is identified by a unique tag. The 2-way cache is updated based on a least-recently-used algorithm. Control bits in the CPU status register ST3_55 provide the ability to enable, freeze, and flush the cache. For more information on the instruction cache, see the TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630).

40

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.1.4 Memory Map

Byte Address 000000h DARAM0 (8K Bytes) 002000h DARAM1 (8K Bytes) 004000h DARAM2 (8K Bytes) 006000h DARAM3 (8K Bytes) 008000h 008000h 002000h DARAM1 (8K Bytes) 004000h DARAM2 (8K Bytes) 006000h DARAM3 (8K Bytes) Byte Address 000000h DARAM0 (8K Bytes)

Reserved

Reserved

010000h External CE0 Space (4M minus 64K Bytes) 400000h External CE1 Space (4M Bytes) 800000h External CE2 Space (4M Bytes) C00000h External CE3 Space (4M Bytes Minus 32K Bytes) FF8000h ROM (32K Bytes)

010000h External CE0 Space (4M minus 64K Bytes) 400000h External CE1 Space (4M Bytes) 800000h External CE2 Space (4M Bytes) C00000h

External CE3 Space (4M Bytes)

MPNMC = 0

MPNMC = 1

The lower 64K bytes in CE0 Space include 32K bytes of DARAM space and 32K bytes of reserved space. The 32K bytes are for on-chip ROM block. The CE space size shown in the figure represents the maximum addressable memory space for a 32-bit EMIF configuration. The maximum addressable memory space per CE is reduced when 16- or 8-bit EMIF configurations are used for asynchronous and SBSRAM memory types. For more detailed information, refer to TMS320VC5501/5502 DSP External Memory Inteface (EMIF) Reference Guide (literature number SPRU621).

Figure 32. TMS320VC5501 Memory Map

December 2002 Revised November 2008

SPRS206K

41

Functional Overview

3.1.5 Boot Configuration

The on-chip bootloader provides a way to transfer application code and tables from an external source to the on-chip RAM at power up. The 5501 provides several options to download the code to accommodate varying system requirements. These options include: Host-port interface (HPI) boot in multiplexed mode External memory boot (via EMIF) from 16-bit asynchronous memory Serial port boot (from McBSP0) with 16-bit element length SPI EPROM boot (from McBSP0) supporting EPROMs with 24-bit addresses I2C EPROM boot (from I2C) supporting EPROMs larger than 512K bits UART boot Direct execution (no boot) from 16-bit or 32-bit external asynchronous memory

The external pins BOOTM2, BOOTM1, and BOOTM0 select the boot configuration. The values of BOOTM[2:0] are latched with the rising edge of the RESET input. BOOTM2 is shared with GPIO2, BOOTM1 is shared with GPIO1, and BOOTM0 is shared with GPIO0. The boot configurations available are summarized in Table 33. Table 33. Boot Configuration Selection Via the BOOTM[2:0] Pins
BOOTM[2:0] 000 001 010 011 100 101 110 111 SPI EPROM boot Serial port boot (from McBSP0) External memory boot (via EMIF) from 16-bit asynchronous memory Direct execution from 32-bit external asynchronous memory HPI boot I2C EPROM boot UART boot BOOT PROCESS Direct execution from 16-bit external asynchronous memory

3.2

Peripherals
The 5501 includes the following on-chip peripherals: An external memory interface (EMIF) supporting a 32-bit interface to asynchronous memory, SDRAM, and SBSRAM An 8-bit host-port interface (HPI) A six-channel direct memory access (DMA) controller Two multichannel buffered serial ports (McBSPs) A programmable analog phase-locked loop (APLL) clock generator General-purpose I/O (GPIO) pins and a dedicated output pin (XF)

The 5501 can be configured as follows: EMIF/HPI mode: 32-bit external memory interface with 8-bit host-port interface PGPIO mode: PGPIO support with no external memory interface and no host-port interface 42 SPRS206K December 2002 Revised November 2008

Functional Overview

Four timers Two 64-bit general-purpose timers A programmable watchdog timer A DSP/BIOS timer

An Inter-integrated Circuit (I2C) multi-master and slave interface A Universal Asynchronous Receiver/Transmitter (UART)

For detailed information on the C55x DSP peripherals, see the following documents: TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630) TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146) TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613) TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592) TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU621) TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide (literature number SPRU597)

3.3

Configurable External Ports and Signals

A number of pins on the 5501 have two functions, a feature that allows system designers to choose an appropriate media interface for his/her application without the need for a large pin-count package. Two muxes are included in the 5501 to control the configuration of these dual-function pins: the Parallel Port Mux and the Host Port Mux. The state of these muxes is set at reset based on the state of the GPIO6 pin. The External Bus Selection Register (XBSR) reflects the configuration of these muxes after the 5501 comes out of reset.

3.3.1 Parallel Port Mux

The Parallel Port Mux of the 5501 controls the function of 20 address signals (pins A[21:2]), 32 data signals (pins D[31:0]), and 16 control signals (pins C0 through C15). The Parallel Port Mux supports two different modes: Full EMIF mode: The EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to their corresponding pins on the Parallel Port Mux. Parallel general-purpose I/O mode: The EMIF and HPI are disabled and 16 control, 4 address, and 16 data pins of the Parallel Port Mux are set to parallel general-purpose I/O (PGPIO).

The mode of the Parallel Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the EMIF and the HPI will be disabled: pins A[17:2] and pins D[15:0] will become reserved pins. All other pins in the Parallel Port Mux are set to parallel general-purpose I/O. The Parallel/Host Port Mux Mode bit field in the External Bus Selection Register (XBSR) will also be set to 0 to reflect the PGPIO mode of the Parallel Port Mux. If GPIO6 is high at reset, the HPI will be enabled in multiplexed mode and the EMIF will be fully enabled: pins A[21:2] are set to EMIF.A[21:2], pins D[31:0] are set to EMIF.D[31:0], and pins C[15:0] are set to their corresponding EMIF operation. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect the full EMIF mode of the Parallel Port Mux. Note that in multiplexed mode, the HPI will use the HD[7:0] pins to strobe in address and data information (see Section 3.7, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed mode).

December 2002 Revised November 2008

SPRS206K

43

Functional Overview

Table 34 lists the individual routing of the EMIF and PGPIO signals to the external parallel address, data, and control buses. Table 34. TMS320VC5501 Routing of Parallel Port Mux Signals
PIN PARALLEL/HOST PORT MUX MODE = 0 (PGPIO) Address Bus A[17:2] A[21:18] D[31:16] D[15:0] C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Reserved PGPIO[3:0] Data Bus PGPIO[19:4] Reserved Control Bus PGPIO20 PGPIO21 PGPIO22 PGPIO23 PGPIO24 PGPIO25 PGPIO26 PGPIO27 PGPIO28 PGPIO29 PGPIO30 PGPIO31 PGPIO32 PGPIO33 PGPIO34 PGPIO35 EMIF.ARE/SADS/SDCAS/SRE EMIF.AOE/SOE/SDRAS EMIF.AWE/SWE/SDWE EMIF.ARDY EMIF.CE0 EMIF.CE1 EMIF.CE2 EMIF.CE3 EMIF.BE0 EMIF.BE1 EMIF.BE2 EMIF.BE3 EMIF.SDCKE EMIF.SOE3 EMIF.HOLD EMIF.HOLDA EMIF.D[31:16] EMIF.D[15:0] EMIF.A[17:2] EMIF.A[21:18] PARALLEL/HOST PORT MUX MODE = 1 (FULL EMIF)

44

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.3.2 Host Port Mux

The 5501 Host Port Mux controls the function of 8 data signals (pins HD[7:0]) and 2 control signals (pins HC0 and HC1). The Host Port Mux supports two different modes: 8-bit multiplexed mode: The HPIs 8 data and 2 control signals are routed to their corresponding pins on the Host Port Mux. Parallel general-purpose I/O mode: All pins on the Host Port Mux are routed to PGPIO. The HPI and EMIF are disabled.

The mode of the Host Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the pins of the Host Port Mux will be set to PGPIO. In this mode, the EMIF and the HPI will be disabled. The Parallel/Host Port Mux Mode bit of the External Bus Control Register will be set to 0 to reflect the PGPIO mode of the Host Port Mux. If GPIO6 is high, the HPI will be enabled in 8-bit (multiplexed) mode: pins HD[7:0] are set to HPI.HD[7:0], and HC0 and HC1 are set to HPI.HAS and HPI.HBIL, respectively. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect the HPI multiplexed mode of the Host Port Mux. See Section 3.7, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed mode. Table 35 lists the individual routing of the HPI and PGPIO signals to the Host Port Mux pins. Table 35. TMS320VC5501 Routing of Host Port Mux Signals
PIN PARALLEL/HOST PORT MUX MODE = 0 (PGPIO) Data Bus HD[7:0] HC0 HC1 PGPIO[43:36] Control Bus PGPIO44 PGPIO45 HPI.HAS HPI.HBIL HPI.HD[7:0] PARALLEL/HOST PORT MUX MODE = 1 (8-BIT HPI MULTIPLEXED)

December 2002 Revised November 2008

SPRS206K

45

Functional Overview

3.3.3 External Bus Selection Register (XBSR)

The External Bus Selection Register controls the mode of the Parallel Port Mux and Host Port Mux. The Parallel Port Mux can be configured to support the 32-bit EMIF or to support parallel general-purpose I/O. The Host Port Mux can be configured to support the HPI in 8-bit (multiplexed) mode or parallel general-purpose I/O (PGPIO). The XBSR configures the Parallel Port Mux and the Host Port Mux at reset based on the state of the GPIO6 pin at reset. When GPIO6 is high at reset, the Parallel Port Mux will be configured to support the 32-bit EMIF and the Host Port Mux will be configured to support the HPI in 8-bit (multiplexed) mode. When GPIO6 is low at reset, both the Parallel Port Mux and the Host Port Mux will be configured to support parallel general-purpose I/O; the EMIF and HPI will be disabled in this mode. The Paralle/Host Port Mux Mode bit of the XBSR will reflect the mode selected for the Parallel and Host Port Muxes. The clock to the EMIF module is disabled automatically when this module is not selected through the External Bus Selection Register. Note that any accesses to disabled modules will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1.

15 Reserved R, 00000000

3 Reserved (see NOTE) R/W, 0

2 Reserved (see NOTE) R/W, 0

0 Parallel /Host Port Mux Mode R/W, GPIO6

Reserved R, 0000 LEGEND: R = Read, W = Write, n = value at reset

Reserved R, 0

NOTE: This reserved bit must be kept as zero during any writes to XBSR.

Figure 33. External Bus Selection Register Layout (0x6C00)

Modifying the XBSR to change the mode of the Parallel Port Mux and Host Port Mux after the 5501 has been brought out of reset is not supported.

46

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 36. External Bus Selection Register Bit Field Description

BIT NAME Reserved Reserved Reserved Reserved Parallel/Host Port Mux Mode BIT NO. 154 3 2 1 0 ACCESS R R/W R/W R R/W RESET VALUE 000000000000 0 0 0 GPIO6 Reserved Reserved. This reserved bit must be kept as zero during any writes to XBSR. Reserved. This reserved bit must be kept as zero during any writes to XBSR. Reserved Parllel/Host Port Mux Mode bit. Determines the mode of the Parallel Port Mux and the Host Port Mux. Parallel/Host Port Mux Mode = 0: The Parallel Port Mux is configured to support PGPIO. In this mode, the HPI and EMIF cannot be used. The Host Port Mux is configured to support PGPIO. In this mode, the Host Port Mux pins will be routed to PGPIO. Parallel/Host Port Mux Mode = 1: The Parallel Port Mux is configured to support the 32-bit EMIF. In this mode, the EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to their corresponding pins on the Parallel Port Mux. The Host Port Mux is configured to support the HPI in 8-bit (multiplexed) mode. In this mode, the HPI is enabled and its eight data/address and two control signals are routed to their corresponding pins on the Host Port Mux. DESCRIPTION

December 2002 Revised November 2008

SPRS206K

47

Functional Overview

3.3.4 Configuration Examples

Figure 34 and Figure 35 illustrate example configurations for the 5501 based on the state of GPIO6 at reset.

32 X2/CLKIN CLKOUT, X1 D[31:0] Clock Generator EMIF ARDY, HOLD, ECLKIN, EMIFCLKS A[21:2], ECLKOUT1, ECLKOUT2, ARE/SADS/SDCAS/SRE, AOE/SOE/SDRAS, AWE/SWE/SDWE, CE[3:0], BE[3:0], SDCKE, SOE3, HOLDA

TIM0

TIMER0

PGPIO

HD[7:0], HCNTL0, HCNTL1, HCS, HR/W TIM1 TIMER1 HPI HAS, HBIL, HDS1, HDS2, HPIENA HINT, HRDY CLKR0, FSR0, CLKX0, FSX0 WD Timer McBSP0 DR0 DX0 CLKR1, FSR1, CLKX1, FSX1 McBSP1 DR1 DX1

TIMER3 (DSP/BIOS Timer) 8 GPIO[7:0] GPIO XF

RX UART TX

NMI/WDTOUT SCL, SDA I2C Interrupt Control INT[3:0], RESET IACK

Shading denotes a peripheral module not available for this configuration. The NMI/WDTOUT pin has NMI function by default, but can be set to WDTOUT through the TSSR.

Figure 34. Configuration Example A (GPIO6 = 1 at Reset)

48

SPRS206K

December 2002 Revised November 2008

Functional Overview

X2/CLKIN CLKOUT, X1

Clock Generator

EMIF

46 TIM0 TIMER0 PGPIO PGPIO[45:0]

TIM1

TIMER1

HPI

CLKR0, FSR0, CLKX0, FSX0 WD Timer McBSP0 DR0 DX0 CLKR1, FSR1, CLKX1, FSX1 McBSP1 DR1 DX1

TIMER3 (DSP/BIOS Timer) 8 GPIO[7:0] GPIO XF

RX UART TX

NMI/WDTOUT SCL, SDA I2C Interrupt Control INT[3:0], RESET IACK

Shading denotes a peripheral module not available for this configuration. The NMI/WDTOUT pin has NMI function by default, but can be set to WDTOUT through the TSSR.

Figure 35. Configuration Example B (GPIO6 = 0 at Reset)

December 2002 Revised November 2008

SPRS206K

49

Functional Overview

3.4

Timers
The 5501 has four 64-bit timers: Timer 0, Timer 1, Watchdog Timer (WDT), and Timer 3. The first two timers, Timer 0 and Timer 1, are mainly used as general-purpose timers. The third timer, the Watchdog Timer, can be used as either a general-purpose timer or a watchdog timer. The fourth timer is reserved as a DSP/BIOS counter; users have no access to this timer. Each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively. Timer 0, Timer 1, and the Watchdog Timer are each assigned a pin: TIM0 pin is assigned to Timer 0, TIM1 is assigned to Timer 1, and NMI/WDTOUT is used by the Watchdog Timer. The input (TIN) or output (TOUT) signal of Timer 0, Timer 1, and the Watchdog Timer can be connected to their respective pins via the Timer Signal Selection Register (TSSR). The DSP/BIOS timer input, output, and interrupt signals are not internally connected. No interrupts are needed from this timer; therefore, the timer interrupt signal is not internally connected to the CPU interrupt logic. The interrupt signal (TINT) of the Watchdog Timer can be internally connected to the NMI, RESET, and INT3 signals via the TSSR. Note that the NMI/WDTOUT pin has a dual function: Watchdog Timer pin and NMI input pin. The function of the NMI/WDTOUT pin can be selected through the TSSR. For more information on the 5501 timers, see the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618).

50

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.4.1 Timer Interrupts

As stated earlier, each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively. The interrupt signals of Timer 0 and Timer 1 are directly connected to the interrupt logic of the DSP (see Figure 36). The interrupts for Timer 0 and Timer 1 are maskable and can be enabled or disabled through the TINT0 and TINT1 bits of the interrupt enable registers (IER0 and IER1); setting TINT0 of IER0 to 1 enables the interrupt for Timer 0 and setting TINT1 of IER1 enables the interrupt for Timer 1.

TMS320VC5501 DSP Interrupt Logic RESET INT3 NMI TINT1 TINT0

Timer0 10 Others TINT Timer1 TINT Watchdog Timer TINT

01

11

10

IWCON

RESET

INT3

NMI/WDTOUT

Figure 36. Timer Interrupts The interrupt signal for the Watchdog Timer can be internally connected to the RESET, INT3, or NMI signals by setting the IWCON bit of the Timer Signal Selection Register (TSSR) appropriately (see Figure 36). The DSP will be reset once the Watchdog Timer generates an interrupt if the timer interrupt is connected to RESET (IWCON = 01). A non-maskable interrupt will be generated if the timer interrupt is connected to NMI (IWCON = 10). An external interrupt will be generated when the timer interrupt signal is connected to INT3 (IWCON = 11), but only if the INT3 bit of IER0 is set to 1. Refer to Section 3.16, Interrupts, for more information on using interrupts.

December 2002 Revised November 2008

SPRS206K

51

Functional Overview

3.4.2 Timer Pins

The 5501 has one pin for each timer: TIM0 for Timer 0, TIM1 for Timer 1, and NMI/WDTOUT for the Watchdog Timer. Either the output (TOUT) or input (TIN) signal can be connected to the timer pin (see Figure 37). When the timer pin is configured as an output, the TOUT signal is connected to the pin. The TIN signal is connected to the pin when the pin is configured as an input. Each pin can be configured as input or output through the Timer Signal Selection Register (TSSR) (bits TIM0_MODE, TIM1_MODE, and WDT_MODE).
TMS320VC5501 DSP TSSR TIN Timer0 TOUT Peripheral Bus TIM0_MODE TIM0

TIN Timer1 TOUT

TIM1_MODE TIM1

TIN Watchdog Timer TOUT

WDT_MODE NMI/WDTOUT

Figure 37. Timer Pins

When configured as input, the timer pin can be used to source an external clock to the timer. Also, when the timer pin is configured as input and the timer is running off an internal clock, the timer pin can be used to start or stop count of the timer (clock gating). When the timer pin is configured as an output, the timer pin can signal a pulse (pulse mode) or a change of state (clock mode) when the timer count matches its period. The NMI/WDTOUT pin has two functions: Watchdog Timer pin or NMI pin. The NMI/WDTOUT_CFG bit of the TSSR controls the function of this pin. It is possible to configure the NMI/WDTOUT pin as NMI (NMI/WDTOUT_CFG = 1) and also connect the Watchdog Timer TINT signal to the NMI signal (IWCON = 10). In this case, the external NMI signal will be overridden by the TINT signal of the Watchdog Timer, i.e., applying a signal to the NMI/WDTOUT pin will not generate the non-maskable interrupt NMI. For all three timers (Timer 0, Timer 1, and the Watchdog Timer), both the TIN and TOUT signals can be used for general-purpose input/output. The timer pin must be configured for input to use the TIN signal as general-purpose input/output. The timer pin can be configured as an input by setting the pin mode bit of the Timer Signal Selection Register (TSSR) to 0. The TOUT signal can be used as general-purpose input/output if the timer pin is configured for output. The timer pin can be configured as an output by setting the pin mode bit of the TSSR to 1. The GPIO Enable Register (GPEN), GPIO Direction Register (GPIODIR), and the GPIO Data Register (GPDAT) of each timer can be used to control the state of the timer pins when used as general-purpose input/output.

52

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.4.3 Timer Signal Selection Register (TSSR)

The Timer Signal Selection Register (TSSR) controls several pin characteristics for Timer 0, Timer 1, and the Watchdog Timer. The TSSR can be used to specify whether the pins of Timer 0, Timer 1, and the Watchdog Timer are inputs or outputs. The TSSR also determines how the interrupt signal of the Watchdog Timer is connected internally and sets the function for the NMI/WDTOUT pin of the 5501. By default, all timer pins (TIM0, TIM1, and NMI/WDTOUT) are set as inputs, the interrupt signal of the Watchdog Timer is not internally connected to anything, and the NMI/WDTOUT pin has the function of the NMI signal.

15 Reserved R, 00000000

0 NMI/WDTOUT _CFG R/W, 1

Reserved R, 00

WDT_MODE R/W, 0

TIM1_MODE R/W, 0

TIM0_MODE R/W, 0

IWCON R/W, 00

LEGEND: R = Read, W = Write, n = value at reset

Figure 38. Timer Signal Selection Register Layout (0x8000) Table 37. Timer Signal Selection Register Bit Field Description
BIT NAME Reserved WDT_MODE BIT NO. 156 5 ACCESS R R/W RESET VALUE 0000000000 0 Reserved WDT pin mode WDT_MODE = 0: WDT_MODE = 1: TIM1_MODE 4 R/W 0 TIM1 pin mode TIM1_MODE = 0: TIM1_MODE = 1: TIM0_MODE 3 R/W 0 TIM0 pin mode TIM0_MODE = 0: TIM0_MODE = 1: TIM0 pin is used as the timer input pin. TIM0 pin is used as the timer output pin. TIM1 pin is used as the timer input pin. TIM1 pin is used as the timer output pin. WDTOUT pin is used as the timer input pin. WDTOUT pin is used as the timer output pin. DESCRIPTION

If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the NMI/WDTOUT pin will be ignored.

December 2002 Revised November 2008

SPRS206K

53

Functional Overview

Table 37. Timer Signal Selection Register Bit Field Description (Continued)
BIT NAME IWCON BIT NO. 2:1 ACCESS R/W RESET VALUE 00 DESCRIPTION Internal WDT output signal connection IWCON = 00: IWCON = 01: Internal watchdog timer interrupt (TINT) signal has no internal connection. Internal watchdog timer interrupt (TINT) signal has an internal connection to RESET pin. Internal watchdog timer interrupt (TINT) signal has an internal connection to NMI pin. Internal watchdog timer interrupt (TINT) signal has an internal connection to INT3 pin.

IWCON = 10:

IWCON = 11:

NMI/WDTOUT_CFG

R/W

NMI/WDTOUT configuration NMI/WDTOUT_CFG = 0: NMI/WDTOUT pin is used as the WDTOUT pin. NMI/WDTOUT_CFG = 1: NMI/WDTOUT pin is used as the NMI input pin.

If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the NMI/WDTOUT pin will be ignored.

3.5

Universal Asynchronous Receiver/Transmitter (UART)

The UART peripheral is based on the industry-standard TL16C550B asynchronous communications element, which in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes, including three additional bits of error status per byte for the receiver FIFO. The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be configured to minimize software management of the communications link. The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors from 1 to 65535 and producing a 16 reference clock for the internal transmitter and receiver logic.

54

SPRS206K

December 2002 Revised November 2008

Functional Overview
S e l e c t Data Bus Buffer 16 Line Control Register Receiver Timing and Control

8 8

Receiver FIFO

Peripheral Bus

Receiver Buffer Register

Receiver Shift Register

RX pin

Divisor Latch (LS) Divisor Latch (MS)

16

Baud Generator

Line Status Register 8 Transmitter FIFO 8 8 S e l e c t

Transmitter Timing and Control

Transmitter Holding Register Modem Control Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register

Transmitter Shift Register

TX pin

Control Logic

Interrupt/ Event Control Logic

Interrupt to CPU Event to DMA controller

8 Power and Emulation Control Register

Figure 39. UART Functional Block Diagram

December 2002 Revised November 2008

SPRS206K

55

Functional Overview

3.6

Inter-Integrated Circuit (I2C) Module

The TMS320VC5501 also includes an I2C serial port for control purposes. Features of the I2C port include: Compatibility with Philips I2C-Bus Specification, Version 2.1 (January 2000) Fast mode up to 400 Kbps (no fail-safe I/O buffers) Noise filters (on the SDA and SCL pins) to suppress noise of 50 ns or less (I2C module clock must be in the range of 7 MHz to 12 MHz) 7-bit and 10-bit device addressing modes Master (transmit/receive) and slave (transmit/receive) functionality Events: DMA, interrupt, or polling Slew-rate limited open-drain output buffers

The I2C module clock must be in the range of 7 MHz to 12 MHz. This is necessary for the proper operation of the I2C module. NOTE: For additional information, see the TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146). Figure 310 is a block diagram of the I2C module.

I2C Module Clock Prescale I2CPSC SYSCLK2 From PLL Clock Generator

SCL I2C Clock Noise Filter

Bit Clock Generator I2CCLKH I2CCLKL

Control I2COAR I2CSAR I2CMDR Own Address Slave Address Mode Data Count

Transmit I2CXSR Transmit Shift Transmit Buffer Interrupt/DMA Noise Filter Receive I2CDRR Receive Buffer Receive Shift I2CIER I2CSTR I2CISRC Interrupt Enable Status Interrupt Source I2CCNT

I2CDXR SDA I2C Data

I2CRSR

NOTE A: Shading denotes control/status registers.

Figure 310. I2C Module Block Diagram

56

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.7

Host-Port Interface (HPI)

The 5501 HPI provides an 8-bit parallel interface (multiplexed mode) to a host with the following features: Host access to on-chip DARAM (excluding CPU memory-mapped registers) 16-bit address register with autoincrement capability for faster transfers Multiple address/data strobes provide a glueless interface to a variety of hosts HRDY signal for handshaking with host

The 5501 HPI can access the entire DARAM space of the 5501 (excluding memory-mapped CPU registers); however, it does not have access to external memory of the peripheral I/O space. Furthermore, the HPI cannot access internal DARAM space when the device is in reset. Note that all accesses made through the HPI are word-addressed. NOTE: No host access should occur when the HPI is placed in IDLE. The host cannot wake up the DSP through the DSP_INT bit of the HPIC register when the DSP is in IDLE mode. The 5501 HPI only supports data transfers in multiplexed 8-bit mode. In multiplexed mode, the host can only send 8 bits of data at a time through the HD[7:0] bus; therefore, some extra steps have to be taken to read/write from the 5501s internal memory [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for more information on the 5501 HPI]. The 5501 HPI has its own register set, therefore the HINT bit of CPU register ST3_55 is not used for DSP-to-host interrrupts. The HINT bit in the Host Port Control Register (HPIC) should be used for DSP-to-host interrupts. A host must not initiate any transfer requests from the HPI while the HPI is being brought out of reset. As described in Section 3.9.6, Reset Sequence, the C55x CPU and the peripherals are not brought out of reset immediately after the RESET pin transitions from low to high. Instead, an internal counter stretches the reset signal to allow enough time for the internal oscillator to stabilize and also to allow the reset signal to propagate through different parts of the device. The IACK pin will go low for two CPU clock cycles to indicate that this internal reset signal has been deasserted. A host must follow one of these two requirements before initiating transfer requests from the HPI: 1. Keep the HPIENA pin low until the internal reset signal has been deasserted. 2. Keep the HCS, HDS1, and HDS2 pins inactive until the internal reset signal has been deasserted. Note that when the HPI bootmode is used, the GPIO4 pin can also be used to determine when the internal reset signal has been deasserted as this pin is used by the HPI to signal to the host that it is ready to receive access requests.

December 2002 Revised November 2008

SPRS206K

57

Functional Overview

3.8

Direct Memory Access (DMA) Controller

The 5501 DMA provides the following features: Four standard ports for the following data resources: two for DARAM, one for Peripherals, and one for External Memory Six channels, which allow the DMA controller to track the context of six independent DMA channels Programmable low/high priority for each DMA channel One interrupt for each DMA channel Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected events. Programmable address modification for source and destination addresses Idle mode that allows the DMA controller to be placed in a low-power (idle) state under software control

The 5501 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in power-down mode for the Auto-wakeup/Idle function to work.] The 5501 DMA controller allows transfers to be synchronized to selected events. The 5501 supports 14 separate synchronization events and each channel can be tied to separate synchronization event independent of the other channels. Synchronization events are selected by programming the SYNC field in the channel-specific DMA Channel Control Register (DMA_CCR). The 5501 DMA can access all the internal DARAM space as well as all external memory space. The 5501 DMA also has access to the registers for the following peripheral modules: McBSP, UART, GPIO, PGPIO, and I2C.

3.8.1 DMA Channel 0 Control Register (DMA_CCR0)

The DMA Channel 0 Control Register (DMA_CCR0) bit layouts are shown in Figure 311. DMA_CCR1 to DMA_CCR5 have similar bit layouts. See the TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613) for more information on the DMA Channel n Control Register (n = 0, 1, 2, 3, 4, or 5).

15 DSTAMODE R/W, 00

14

13 SRCAMODE R/W, 00

12

11 ENDPROG R/W, 0

10 WP R/W, 0

9 REPEAT R/W, 0

8 AUTOINIT R/W, 0

7 EN R/W, 0

6 PRIO R/W, 0

5 FS R/W, 0

4 SYNC R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 311. DMA Channel 0 Control Register Layout (0x0C01)

58

SPRS206K

December 2002 Revised November 2008

Functional Overview

The SYNC field (bits[4:0]) of the DMA_CCR register specifies the event that can initiate the DMA transfer for the corresponding DMA channel. The five bits allow several configurations as listed in Table 38. The bits are set to zero upon reset. Table 38. Synchronization Control Function
SYNC FIELD IN DMA_CCR 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b 10000b 10001b 10010b 10011b 10100b Other values No event synchronized McBSP 0 Receive Event (REVT0) McBSP 0 Transmit Event (XEVT0) Reserved (Do not use this value) Reserved (Do not use this value) McBSP1 Receive Event (REVT1) McBSP1 Transmit Event (XEVT1) Reserved (Do not use this value) Reserved (Do not use this value) Reserved (Do not use this value) Reserved (Do not use this value) UART Receive Event (UARTREVT) UART Transmit Event (UARTXEVT) Timer 0 Event Timer 1 Event External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 I2C Receive Event I2C Transmit Event Reserved (Do not use these values) SYNCHRONIZATION MODE

December 2002 Revised November 2008

SPRS206K

59

60 GPIO4 at Reset = 0 > CLKMD[0] = 0 GPIO4 at Reset = 1 > CLKMD[0] = 1 CLKOSEL (CLKOUTSR[2:1]) CLKMD (CLKMD[0]) PLLEN (PLLCSR[0]) CLKOUTDIS (CLKOUTSR[0]) CLKOUT Divider D1 0 /1,/2,/4 ENA D1EN (PLLDIV1[15]) Divider D2 /1,/2,/4 D0EN (PLLDIV0[15]) ENA D2EN (PLLDIV2[15]) Divider D3 /1,/2,/4 ENA D3EN (PLLDIV3[15]) 55x Core CLKOUT3 (DSP Core Clock) CK3SEL (CK3SEL[3:0]) SYSCLK3 (EMIF Internal Clock) Divider OD1 /1,/2,...,/32 ENA OD1EN (OSCDIV1[15]) SYSCLK2 (Slow Peripherals) SYSCLK1 (Fast Peripherals) 1 OSCOUT 0 Divider D0 PLL PLLOUT 1 /1,/2,...,/32 PLLREF x2, x3, ...,x15 ENA 1 EMIF /1,/2,/4 0 ECLKOUT1 ECLKOUT2

3.9

System Clock Generator

Functional Overview

The TMS320VC5501 includes a flexible clock generator module consisting of a PLL and oscillator, with several dividers so that different clocks may be generated for different parts of the system (i.e., 55x core, Fast Peripherals, Slow Peripherals, External Memory Interface). Figure 312 provides an overview of the system clock generator included in the 5501.

SPRS206K

GPIO4 at Reset

X2/CLKIN

OSC

X1

PWRDN

OSCPWRDN (PLLCSR[2])

Clock Generator

ECLKIN

December 2002 Revised November 2008

EMIFCLKS

Figure 312. System Clock Generator

Functional Overview

3.9.1 Input Clock Source

The clock input to the 5501 can be sourced from either an externally generated 3.3-V clock input on the X2/CLKIN pin, or from the on-chip oscillator if an external crystal circuit is attached to the device as shown in Figure 313. The CLKMD0 bit of the Clock Mode Control Register (CLKMD) determines which clock, either OSCOUT or X2/CLKIN, is used as an input clock source to the DSP. If GPIO4 is low at reset, the CLKMD0 bit of the Clock Mode Control Register (CLKMD) will be set to 0 and the internal oscillator and the external crystal will generate the input clock to the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and the input clock will be taken directly from the X2/CLKIN pin. The input clock source to the DSP can be directly used to generate the clocks to other parts of the system (Bypass Mode) or it can be multiplied by a value from 2 to 15 and divided by a value from 1 to 32 to achieve a desired frequency (PLL Mode). The PLLEN bit of the PLL Control/Status Register (PLLCSR) is used to select between the PLL and bypass modes of the clock generator. The clock generated through either the PLL Mode or the Bypass Mode can be further divided down to generate a clock source for other parts of the system, or Clock Groups. Clock groups allow for lower power and performance optimization since the frequency of groups with no high-speed requirements can be set to one-fourth or one-half the frequency of other groups. A description of the different clock groups included in the 5501 and the procedure for changing the operating frequency for those clock groups are described later in this section.

3.9.1.1

Internal System Oscillator With External Crystal

The 5501 includes an internal oscillator which can be used in conjunction with an external crystal to generate the input clock to the DSP. The oscillator requires an external crystal connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock source must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator can be used as a clock source to the PLL, the crystal oscillation frequency can be multiplied to generate the input clock to the different clock groups of the DSP. The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance (ESR) as specified in Table 39. The connection of the required circuit is shown in Figure 313. Under some conditions, all the components shown are not required. The capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL in the equation is the load specified for the crystal that is also specified in Table 39. CL + C 1C 2 ( C 1 ) C 2)

X2/CLKIN

X1 RS Crystal

C1

C2

Figure 313. Internal System Oscillator With External Crystal

December 2002 Revised November 2008

SPRS206K

61

Functional Overview

Table 39. Recommended Crystal Parameters

FREQUENCY RANGE (MHz) 2015 1512 1210 108 86 65 MAXIMUM ESR SPECIFICATIONS () 40 40 40 60 60 80 CLOAD (pF) 10 16 16 18 18 18 MAXIMUM CSHUNT (pF) 7 7 7 7 7 7 RS (k) 0 0 2.8 2.2 8.8 14

The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum ESR might seem to meet these specifications. However, it is recommended that crystals with actual maximum ESR specifications as shown in Table 39 be used since this will result in maximum crystal performance reliability. The internal oscillator can be set to power-down mode through the use of the OSCPWRDN bit in the PLL Control/Status Register (PLLCSR). If the internal oscillator and the external crystal are generating the input clock for the DSP (CLKMD0 = 0), the internal oscillator will be set to power-down mode when the OSCPWRDN bit is set to 1 and the clock generator is set to its idle mode (CLKIS bit of the IDLE Status Register (ISTR) becomes 1). If the X2/CLKIN pin is supplying the input clock to the DSP (CLKMD0 = 1), the internal oscillator will be set to power-down immediately after the OSCPWRDN bit is set to 1. The 5501 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference clock cycles) to allow the oscillator input to become stable after waking up from power-down state or after reset. If a reset is asserted, program flow will start after all stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator stabilization period has completed. See Section 3.9.6, Reset Sequence, for more details on program flow after reset or after oscillator power-down. See Section 3.10, Idle Control, for more information on the oscillator power-down mode.

3.9.1.2

Clock Generation With PLL Disabled (Bypass Mode, Default)

After reset, the PLL multiplier (M1) and its divider (D0) will be bypassed by default and the input clock to point C in Figure 314 will be taken from, depending on the state of the GPIO4 pin after reset, either the internal oscillator or the X2/CLKIN pin. The PLL can be taken out of bypass mode as described in Section 3.9.4.1, C55x Subsystem Clock Group.

3.9.1.3

Clock Generation With PLL Enabled (PLL Mode)

When not in bypass mode, the frequency of the input clock can be divided down by a programmable divider (D0) by any factor from 1 to 32. The output clock of the divider can be multiplied by any factor from 2 to 15 through a programmable multiplier (M1). The divider factor can be set through the PLLDIV0 bit of the PLL Divider 0 Register. The multiplier factor can be set through the PLLM bits of the PLL Multiplier Control Register. There is a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 312, as well as for the C55x Core clock (CLKOUT3), the Fast Peripherals clock (SYSCLK1), the Slow Peripherals clock (SYSCLK2), and the EMIF internal clock (SYSCLK3). The clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 310 for the PLL clock input and output frequency ranges.

62

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.9.1.4

Frequency Ranges for Internal Clocks

There are specific minimum and maximum reference clocks for all of the internal clocks. Table 310 lists the minimum and maximum frequencies for the internal clocks of the TMS320VC5501. Table 310. Internal Clocks Frequency Ranges
CLOCK SIGNAL OSCOUT (CLKMD = 0) PLLREF (PLLEN = 1) PLLOUT (PLLEN = 1) CLKOUT3 SYSCLK1 SYSCLK2 MIN 5 12 70 MAX 20 100 300 300 150 SYSCLK1 SYSCLK1 UNIT MHz MHz MHz MHz MHz MHz

SYSCLK3 MHz Also see the electrical specification (timing requirements and switching characteristics parameters) in Section 5.6, Clock Options, of this data manual. When an internal clock is used for the EMIF module, the frequency for SYSCLK3 must also be less than or equal to 100 MHz. When an external clock is used, the maximum frequency of SYSCLK3 can be equal to or less than the frequency of SYSCLK1; however, the frequency of the clock signal applied to the ECLKIN pin must be less than or equal to 100 MHz.

3.9.2 Clock Groups

The TMS320VC5501 has four clock groups: the C55x Subsystem Clock Group, the Fast Peripherals Clock Group, the Slow Peripherals Clock Group, and the External Memory Interface Clock Group. Clock groups allow for lower power and performance optimization since the frequency of groups with no high-speed requirements can be set to 1/4 or 1/2 the frequency of other groups.

3.9.2.1

C55x Subsystem Clock Group

The C55x Subsystem Clock Group includes the C55x CPU core, internal memory (DARAM and ROM), the ICACHE, and all CPU-related modules. The input clock to this clock group is taken from the CLKOUT3 signal (as shown in Figure 312), the source of which can be controlled through the CLKOUT3 Select Register (CK3SEL). The different options for the CLKOUT3 signal are intended for test purposes; it is recommended that the CK3SEL bits of the CK3SEL register be kept at their default value of 1011b during normal operation. When operating the clock generator in PLL Mode, the frequency of CLKOUT3 can be set by adjusting the divider and multiplier values of D0 and M1 through the PLLDIV0 and PLLM registers, respectively.

3.9.2.2

Fast Peripherals Clock Group

The Fast Peripherals Clock Group includes the DMA, HPI, and the timers. The input clock to this clock group is taken from the output of divider 1 (D1) (as shown in Figure 312). By default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV1 bits of the PLL Divider1 Register (PLLDIV1) through software.

3.9.2.3

Slow Peripherals Clock Group

The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken from the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock Group must be equal to or less than that of the Fast Peripherals Clock Group.

3.9.2.4

External Memory Interface Clock Group

The External Memory Interface Clock Group includes the External Memory Interface (EMIF) module and the external data bridge modules. The input clock to this clock group is taken from the output of divider 3 (D3). By default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV3 bits of the PLL Divider3 Register (PLLDIV3) through software. The clock frequency of the External Memory Interface Clock Group must be equal to or less than that of the Fast Peripherals Clock Group.

December 2002 Revised November 2008

SPRS206K

63

Functional Overview

3.9.3 EMIF Input Clock Selection

The EMIF may be clocked from an external asynchronous clock source through the ECLKIN pin if a specific EMIF frequency is needed. The source for the EMIF clock can be specified through the EMIFCLKS pin. If EMIFCLKS is low, then the EMIF will be clocked via the same internal clock that feeds the data bridge module and performance will be optimal. If EMIFCLKS is high, then an external asynchronous clock, which can be taken up to 100 MHz, will clock the EMIF. The data throughput performance may be degraded due to synchronization issues when an external clock source is used for the EMIF.

3.9.4 Changing the Clock Group Frequencies

DSP software can be used to change the clock frequency of each clock group by setting adequate values in the PLL control registers. Figure 314 shows which PLL control registers affect the different portions of the clock generator. The following sections describe the procedures for changing the frequencies of each clock group.

OSCOUT X2/CLKIN CLKMD0

0 Point A 1

Divider D0

Point B

PLL Core Multiplier M1

1 Point C 0 Divider D1 Divider D2 Divider D3 SYSCLK1 SYSCLK2 SYSCLK3

PLLEN

CLKOUT3 Divider OD1

PLLCSR PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 CK3SEL WKEN Oscillator Power-Down Control

Figure 314. Clock Generator Registers

64

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.9.4.1

C55x Subsystem Clock Group

Changes to the PLL Control Register (PLLCSR), the PLL Divider0 Register (PLLDIV0), and the PLL Multiplier Register (PLLM) affect the clock of this clock group. The following procedure must be followed to change or to set the PLL to a specific value: 1. Switch to bypass mode by setting the PLLEN bit to 0. 2. Set the PLL to its reset state by setting the PLLRST bit to 1. 3. Change the PLL setting through the PLLM and PLLDIV0 bits. 4. Wait for 1 s. 5. Release the PLL from its reset state by setting PLLRST to 0. 6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt. 7. Switch back to PLL mode by setting the PLLEN bit to 1. The frequency of the C55x Subsystem Clock Group can be up to 300 MHz.

3.9.4.2

Fast Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Fast Peripherals Clock Group. The PLLDIV1 value of the PLL Divider1 Register (PLLDIV1) should not be set in a manner that makes the frequency for this clock group greater than 150 MHz. There must be no activity in the modules included in the Fast Peripherals Clock Group when the value of PLLDIV1 is being changed. It is recommended that the fast peripheral modules be put in IDLE mode before changing the PLLDIV1 value.

3.9.4.3

Slow Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Slow Peripherals Clock Group. The PLLDIV2 value of the PLL Divider2 Register (PLLDIV2) should not be set in a manner that makes the frequency for this clock group greater than 150 MHz or greater than the frequency of the Fast Peripherals Clock Group. There must be no activity in the modules included in the Slow Peripherals Clock Group when the value of PLLDIV2 is being changed. It is recommended that the slow peripheral modules be put in IDLE mode before changing the PLLDIV2 value.

3.9.4.4

External Memory Interface Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the External Memory Interface Clock Group. The PLLDIV3 value of the PLL Divider3 Register (PLLDIV3) should not be set in a manner that makes the frequency for this clock group greater than 100 MHz or greater than the frequency of the Fast Peripherals Clock Group, whichever is smaller. If an external clock is used, the clock on the ECLKIN pin can be up to 100 MHz and the output of divider 3 can be set equal to or lower than the frequency of the Fast Peripherals Clock Group. There must be no external memory accesses when the value of PLLDIV3 is being changed, this means that the value of PLLDIV3 cannot be changed by a program that is being executed from external memory. It is recommended that the EMIF be put in IDLE mode before changing the PLLDIV3 value.

December 2002 Revised November 2008

SPRS206K

65

Functional Overview

3.9.5 PLL Control Registers

The 5501 PLL control registers are accessible via the I/O memory map. Table 311. PLL Control Registers
ADDRESS 1C80h 1C82h 1C88h 1C8Ah 1C8Ch 1C8Eh 1C90h 1C92h 1C98h 8400h 8C00h REGISTER PLLCSR CK3SEL PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 WKEN CLKOUTSR CLKMD

3.9.5.1
15

PLL Control / Status Register (PLLCSR)

8 Reserved R, 00000000

7 Reserved R, 0

6 STABLE R, 1

5 LOCK R, 0

4 Reserved R, 0

3 PLLRST R/W, 1

2 OSCPWRDN R/W, 0

1 PLLPWRDN R/W, 0

0 PLLEN R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 315. PLL Control/Status Register Layout (0x1C80)

66

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 312. PLL Control/Status Register Bit Field Description

BIT NAME Reserved STABLE BIT NO. 15:7 6 ACCESS R R RESET VALUE 000000000 1 DESCRIPTION Reserved. Reads return 0. Writes have no effect. Oscillator output stable. This bit indicates if the OSCOUT output has stabilized. STABLE = 0: Oscillator output is not yet stable. Oscillator counter is not done counting 41,032 reference clock cycles. Oscillator output is stable. This is true if any one of the three cases is true: a) Oscillator counter has finished counting. b) Oscillator counter is disabled. c) Test mode.

STABLE = 1:

LOCK

Lock mode indicator. This bit indicates whether the clock generator is in its lock mode. LOCK = 0: LOCK = 1: The PLL is in the process of getting a phase lock. The clock generator is in the lock mode. The PLL has a phase lock and the output clock of the PLL has the frequency determined by the PLLM register and PLLDIV0 register.

Reserved PLLRST

4 3

R R/W

0 1

Reserved. Reads return 0. Writes have no effect. Asserts RESET to PLL PLLRST = 0: PLLRST = 1: PLL reset released PLL reset asserted

OSCPWRDN

R/W

Sets internal oscillator to power-down mode OSCPWRDN = 0: OSCPWRDN = 1: Oscillator operational Oscillator set to power-down mode based on state of CLKMD0 bit of Clock Mode Control Register (CLKMD). When CLKMD0 = 0, the internal oscillator is set to power-down mode when the clock generator is set to its idle mode [CLKIS bit of the IDLE Status Register (ISTR) becomes 1]. When CLKMD0 = 1, the internal oscillator is set to power-down mode immediately after the OSCPWRDN bit is set to 1.

PLLPWRDN

R/W

Selects PLL power down PLLPWRDN = 0: PLLPWRDN = 1: PLL operational PLL placed in power-down state

PLLEN

R/W

PLL mode enable. This bit controls the multiplexer before dividers D1, D2, and D3. PLLEN = 0: Bypass mode. Divider D1 and PLL are bypassed. SYSCLK1 to 3 divided down directly from input reference clock. PLL mode. Divider D1 and PLL are not bypassed. SYSCLK1 to 3 divided down from PLL output.

PLLEN = 1:

December 2002 Revised November 2008

SPRS206K

67

Functional Overview

3.9.5.2
15

PLL Multiplier Control Register (PLLM)

8 Reserved R, 00000000

7 Reserved R, 000

4 PLLM R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 316. PLL Multiplier Control Register Layout (0x1C88) Table 313. PLL Multiplier Control Register Bit Field Description
BIT NAME Reserved PLLM BIT NO. 15:5 4:0 ACCESS R R/W RESET VALUE 00000000000 00000 PLL multiplier-select PLLM = 0000000001: PLLM = 00010: PLLM = 00011: PLLM = 00100: PLLM = 00101: PLLM = 00110: PLLM = 00111: PLLM = 01000: PLLM = 01001: PLLM = 01010: PLLM = 01011: PLLM = 01100: PLLM = 01101: PLLM = 01110: PLLM = 01111: PLLM = 1000011111: Reserved Times 2 Times 3 Times 4 Times 5 Times 6 Times 7 Times 8 Times 9 Times 10 Times 11 Times 12 Times 13 Times 14 Times 15 Reserved DESCRIPTION Reserved. Reads return 0. Writes have no effect.

68

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.9.5.3

PLL Divider 0 Register (PLLDIV0) (Prescaler)

This register controls the value of the PLL prescaler (Divider D0).
15 D0EN R/W, 1 7 Reserved R, 000 LEGEND: R = Read, W = Write, n = value at reset 5 4 PLLDIV0 R/W, 00000 14 Reserved R, 0000000 0 8

Figure 317. PLL Divider 0 Register Layout (0x1C8A) Table 314. PLL Divider 0 Register Bit Field Description
BIT NAME D0EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D0 enable D0EN = 0: D0EN = 1: Reserved PLLDIV0 14:5 4:0 R R/W 0000000000 00000 Divider D0 ratio PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 00000: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101: 10110: 10111: 11000: 11001: 11010: 11011: 11100: 11101: 11110: 11111: Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 Divide by 16 Divide by 17 Divide by 18 Divide by 19 Divide by 20 Divide by 21 Divide by 22 Divide by 23 Divide by 24 Divide by 25 Divide by 26 Divide by 27 Divide by 28 Divide by 29 Divide by 30 Divide by 31 Divide by 32 Divider 0 disabled Divider 0 enabled DESCRIPTION

Reserved. Reads return 0. Writes have no effect.

December 2002 Revised November 2008

SPRS206K

69

Functional Overview

3.9.5.4

PLL Divider1 Register (PLLDIV1) for SYSCLK1

This register controls the value of the divider D1 for SYSCLK1. It is in both the BYPASS and PLL paths.

15 D1EN R/W, 1

14 Reserved R, 0000000

7 Reserved R, 000

4 PLLDIV1 R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 318. PLL Divider 1 Register Layout (0x1C8C) Table 315. PLL Divider 1 Register Bit Field Description
BIT NAME D1EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D1 enable D1EN = 0: D1EN = 1: Reserved PLLDIV1 14:5 4:0 R R/W 0000000000 00011 Divider 1 disabled Divider 1 enabled DESCRIPTION

Reserved. Reads return 0. Writes have no effect. Divider D1 ratio (SYSCLK1 divider) PLLDIV1 = 00000: PLLDIV1 = 00001: PLLDIV1 = 00010: PLLDIV1 = 00011: PLLDIV1 = 0010011111: Divide by 1 Divide by 2 Reserved Divide by 4 Reserved

3.9.5.5

PLL Divider2 Register (PLLDIV2) for SYSCLK2

This register controls the value of the divider D2 for SYSCLK2. It is in both the BYPASS and PLL paths.

15 D2EN R/W, 1

14 Reserved R, 0000000

7 Reserved R, 000

4 PLLDIV2 R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 319. PLL Divider 2 Register Layout (0x1C8E)

70

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 316. PLL Divider 2 Register Bit Field Description

BIT NAME D2EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D2 enable D2EN = 0: D2EN = 1: Reserved PLLDIV2 14:5 4:0 R R/W 0000000000 00011 Divider 2 disabled Divider 2 enabled DESCRIPTION

Reserved. Reads return 0. Writes have no effect. Divider D2 ratio (SYSCLK2 divider) PLLDIV2 = 00000: PLLDIV2 = 00001: PLLDIV2 = 00010: PLLDIV2 = 00011: PLLDIV2 = 0010011111: Divide by 1 Divide by 2 Reserved Divide by 4 Reserved

3.9.5.6

PLL Divider3 Register (PLLDIV3) for SYSCLK3

This register controls the value of the divider D3 for SYSCLK3. It is in both the BYPASS and PLL paths.

15 D3EN R/W, 1

14 Reserved R, 0000000

7 Reserved R, 000

4 PLLDIV3 R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 320. PLL Divider 3 Register Layout (0x1C90)

Table 317. PLL Divider 3 Register Bit Field Description

BIT NAME D3EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D3 enable D3EN = 0: D3EN = 1: Reserved PLLDIV3 14:5 4:0 R R/W 0000000000 00011 Divider 3 disabled Divider 3 enabled DESCRIPTION

Reserved. Reads return 0. Writes have no effect. Divider D3 ratio (SYSCLK3 divider) PLLDIV3 = 00000: PLLDIV3 = 00001: PLLDIV3 = 00010: PLLDIV3 = 00011: PLLDIV3 = 0010011111: Divide by 1 Divide by 2 Reserved Divide by 4 Reserved

December 2002 Revised November 2008

SPRS206K

71

Functional Overview

3.9.5.7

Oscillator Divider1 Register (OSCDIV1) for CLKOUT3

This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path.
15 OD1EN R/W, 0 7 Reserved R, 000 LEGEND: R = Read, W = Write, n = value at reset 5 4 OSCDIV1 R/W, 00000 14 Reserved R, 0000000 0 8

Figure 321. Oscillator Divider1 Register Layout (0x1C92) Table 318. Oscillator Divider1 Register Bit Field Description
BIT NAME OD1EN BIT NO. 15 ACCESS R/W RESET VALUE 0 DESCRIPTION Oscillator divider OD1 enable OD1EN = 0: OD1EN = 1: Reserved OSCDIV1 14:5 4:0 R R/W 0000000000 00000 Oscillator divider 1 disabled Oscillator divider 1 enabled

Reserved. Reads return 0. Writes have no effect. Divider OD1 ratio (CLKOUT3 divider) OSCDIV1 = 00000: OSCDIV1 = 00001: OSCDIV1 = 00010: OSCDIV1 = 00011: OSCDIV1 = 00100: OSCDIV1 = 00101: OSCDIV1 = 00110: OSCDIV1 = 00111: OSCDIV1 = 01000: OSCDIV1 = 01001: OSCDIV1 = 01010: OSCDIV1 = 01011: OSCDIV1 = 01100: OSCDIV1 = 01101: OSCDIV1 = 01110: OSCDIV1 = 01111: OSCDIV1 = 10000: OSCDIV1 = 10001: OSCDIV1 = 10010: OSCDIV1 = 10011: OSCDIV1 = 10100: OSCDIV1 = 10101: OSCDIV1 = 10110: OSCDIV1 = 10111: OSCDIV1 = 11000: OSCDIV1 = 11001: OSCDIV1 = 11010: OSCDIV1 = 11011: OSCDIV1 = 11100: OSCDIV1 = 11101: OSCDIV1 = 11110: OSCDIV1 = 11111: Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 Divide by 16 Divide by 17 Divide by 18 Divide by 19 Divide by 20 Divide by 21 Divide by 22 Divide by 23 Divide by 24 Divide by 25 Divide by 26 Divide by 27 Divide by 28 Divide by 29 Divide by 30 Divide by 31 Divide by 32

72

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.9.5.8

Oscillator Wakeup Control Register (WKEN)

This register controls whether different events in the system are enabled to wake up the device after entering OSCPWRDN.
15 Reserved R, 00000000 7 Reserved R, 000 LEGEND: R = Read, W = Write, n = value at reset 5 4 WKEN4 R/W, 1 3 WKEN3 R/W, 1 2 WKEN2 R/W, 1 1 WKEN1 R/W, 1 0 WKEN0 R/W, 1 8

Figure 322. Oscillator Wakeup Control Register Layout (0x1C98) Table 319. Oscillator Wakeup Control Register Bit Field Description
BIT NAME Reserved WKEN4 BIT NO. 15:5 4 ACCESS R R/W RESET VALUE 00000000000 1 DESCRIPTION Reserved. Reads return 0. Writes have no effect. Input INT3 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN4 = 0: Wake-up enabled. A low-to-high transition on INT3 wakes up the oscillator and clears the OSCPWRDN bit. WKEN4 = 1: Wake-up disabled. A low-to-high transition on INT3 does not wake up the oscillator. WKEN3 3 R/W 1 Input INT2 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN3 = 0: Wake-up enabled. A low-to-high transition on INT2 wakes up the oscillator and clears the OSCPWRDN bit. WKEN3 = 1: Wake-up disabled. A low-to-high transition on INT2 does not wake up the oscillator. WKEN2 2 R/W 1 Input INT1 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN2 = 0: Wake-up enabled. A low-to-high transition on INT1 wakes up the oscillator and clears the OSCPWRDN bit. WKEN2 = 1: Wake-up disabled. A low-to-high transition on INT1 does not wake up the oscillator. WKEN1 1 R/W 1 Input INT0 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN1 = 0: Wake-up enabled. A low-to-high transition on INT0 wakes up the oscillator and clears the OSCPWRDN bit. WKEN1 = 1: Wake-up disabled. A low-to-high transition on INT0 does not wake up the oscillator. WKEN0 0 R/W 1 Input NMI can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN0 = 0: Wake-up enabled. A low-to-high transition on NMI wakes up the oscillator and clears the OSCPWRDN bit. WKEN0 = 1: Wake-up disabled. A low-to-high transition on NMI does not wake up the oscillator.

December 2002 Revised November 2008

SPRS206K

73

Functional Overview

3.9.5.9

CLKOUT3 Select Register (CK3SEL)

This register controls which clock is output onto the CLKOUT3 so that it may be used to test and debug the PLL (in addition to its normal function of being a direct input clock divider). Modes other than CK3SEL = 1011 are intended for debug use only and should not be used during normal operation.
15 Reserved R, 00000000 7 Reserved R, 0000 LEGEND: R = Read, W = Write, n = value at reset 4 3 CK3SEL R/W, 1011 0 8

Figure 323. CLKOUT3 Select Register Layout (0x1C82) Table 320. CLKOUT3 Select Register Bit Field Description
BIT NAME Reserved CK3SEL BIT NO. 15:4 3:0 ACCESS R R/W RESET VALUE 000000000000 1011 DESCRIPTION Reserved. Reads return 0. Writes have no effect. Output on CLK3SEL pin CK3SEL = 1001 CK3SEL = 1010 CK3SEL = 00000111

CLKOUT3 becomes point A in Figure 314 CLKOUT3 becomes point B in Figure 314 CLKOUT3 becomes oscillator divider output in Figure 314 CK3SEL = 1011 CLKOUT3 becomes point C in Figure 314 CK3SEL = Other Not supported The different options for the CLKOUT3 signal are intended for test purposes; it is recommended that the CK3SEL bits of the CK3SEL register be kept at their default value of 1011b during normal operation.

3.9.5.10 CLKOUT Selection Register (CLKOUTSR)

As described in Section 3.9.2, Clock Groups, the 5501 has different clock groups, each of which can be driven by a clock that is different from the CPU clock. The CLKOUT Selection Register determines which clock signal is reflected on the CLKOUT pin.
15 Reserved R, 00000000 7 Reserved R, 00000 LEGEND: R = Read, W = Write, n = value at reset 3 2 CLKOSEL R/W, 01 1 0 CLKOUTDIS R/W, 0 8

Figure 324. CLKOUT Selection Register Layout (0x8400)

74

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 321. CLKOUT Selection Register Bit Field Description

BIT NAME Reserved CLKOSEL BIT NO. 153 2:1 ACCESS R R/W RESET VALUE 0000000000000 01 Reserved CLKOUT source-select CLKOSEL = 00: CLKOSEL = 01: CLKOSEL = 10: CLKOSEL = 11: CLKOUTDIS 0 R/W 0 Disable CLKOUT CLKOUTDIS = 0: CLKOUTDIS = 1: CLKOUT enabled CLKOUT disabled (driving 0) Reserved CLKOUT source is SYSCLK1 CLKOUT source is SYSCLK2 CLKOUT source is SYSCLK3 DESCRIPTION

3.9.5.11 Clock Mode Control Register (CLKMD)

15 Reserved R, 00000000 8

7 Reserved R, 0000000 LEGEND: R = Read, W = Write, n = value at reset

0 CLKMD0 R/W, GPIO4 state at reset

Figure 325. Clock Mode Control Register Layout (0x8C00) Table 322. Clock Mode Control Register Bit Field Description
BIT NAME Reserved CLKMD0 BIT NO. 151 0 ACCESS R R/W RESET VALUE 000000000000000 GPIO4 state at reset Reserved Clock output source-select CLKMD0 = 0: CLKMD0 = 1: OSCOUT is selected as clock input source X2/CLKIN is selected as clock input source DESCRIPTION

December 2002 Revised November 2008

SPRS206K

75

Functional Overview

3.9.6 Reset Sequence

When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or X2/CLKIN, dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the following events will occur in the order listed below. GPIO6 is sampled on the rising edge of the reset signal. The state of GPIO6 determines the function of the multiplexed pins of the 5501. (See Section 3.3, Configurable External Ports and Signals, for more information on pin multiplexing.) The state of GPIO6 during the rising edge of reset determines the value of the Parallel/Host Port Mux Mode bit of the External Bus Control Register (XBSR). GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0 bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and the input clock will be taken directly from the X2/CLKIN pin. After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately. Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal to propagate through different parts of the device. After all internal delay cycles have expired, the IACK pin will go low for two CPU clock cycles to indicate this internal reset signal has been deasserted. The BOOTM[2:0] pins will be sampled and their values will be stored in the Boot Mode Register (BOOTM_MODE). The value in the BOOTM_MODE register will be used by the bootloader to determine the boot mode of the DSP. Program flow will commence after all internal delay cycles have expired.

The 5501 has internal circuitry that will count down 70 reference clock cycles to allow reset signals to propagate correctly to all parts of the device after reset (RESET pin goes high). Furthermore, the 5501 also has internal circuitry that will count down 41,032 reference clock cycles to allow the oscillator input to become stable after waking up from power-down state or reset. If a reset is asserted, program flow will start after all stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator stabilization period has completed. Table 323 summarizes the number of reference clock cycles needed before program flow begins. Table 323. Number of Reference Clock Cycles Needed Until Program Flow Begins
CONDITION Oscillator Not Used (GPIO4 = 1) After Reset After Oscillator Power-Down Oscillator Used (GPIO4 = 0) REFERENCE CLOCK CYCLES 70 41,102 41,032

All output (O/Z) and input/output (I/O/Z) pins (except for CLKOUT, ECLKOUT2, and XF) will go into high-impedance mode during reset and will come out of high-impedance mode when the stabilization periods have expired. All output (O/Z) and input/output (I/O/Z) pins will retain their value when the device enters a power-down mode such as IDLE3 mode.

76

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.10 Idle Control

The Idle function is implemented for low power consumption. The Idle function achieves low power consumption by gating the clock to unused parts of the chip, and/or setting the clock generator (PLL) and the internal oscillator to a power-down mode.

3.10.1

Clock Domains

The 5501 provides six clock domains to power-off the main clock to the portions of the device that are not being used. The six domains are: CPU Domain Master Port Domain (includes DMA and HPI modules) ICACHE Peripherals Domain Clock Generator Domain EMIF Domain

3.10.2

IDLE Procedures

Before entering idle mode (executing the IDLE instruction), the user has first to determine which part of the system needs to be disabled and then program the Idle Control Register (ICR) accordingly. When the IDLE instruction is executed, the ICR will be copied into the Idle Status Register (ISTR). The different bits of the ISTR register will be propagated to disable the chosen domains. Special care has to be taken in programming the ICR as some IDLE domain combinations are not valid (for example: CPU on and clock generator off).

3.10.2.1 CPU Domain Idle Procedure

The 5501 CPU can be idled by executing the following procedure. 1. Write 1 to the CPUI bit (bit 0 of ICR). 2. Execute the IDLE instruction. 3. CPU will go to idle state

3.10.2.2 Master Port Domain (DMA/HPI) Idle Procedure

The clock to the DMA module and/or the HPI module will be stopped when the DMA and/or the HPI bit in the MICR is set to 1 and the MPIS bit in the ISTR becomes 1. The DMA will go into idle immediately if there is no data transfer taking place. If there is a data transfer taking place, then it will finish the current transfer and then go into idle. The HPI will go into idle regardless of whether or not there is a data transfer taking place. Software must confirm that the HPI has no activity before setting it to idle. The 5501 DMA module and the HPI module can be disabled by executing the following procedure. 1. Write 1 to the DMA bit and/or the HPI bit in MICR. 2. Write 1 to the MPI bit in ICR. 3. Execute the IDLE instruction. 4. DMA and/or HPI go/goes to idle.

December 2002 Revised November 2008

SPRS206K

77

Functional Overview

3.10.2.3 Peripheral Modules Idle Procedure

The clock to the modules included in the Peripherals Domain will be stopped when their corresponding bit in the PICR is set to 1 and the PERIS bit in the ISTR becomes 1. Each module in this domain will go into idle immediately if it has no activity. If the module being set to idle has activity, it will wait until the activity completes before going into idle. Each peripheral module can be idled by executing the following procedure. 1. Write 1 to the corresponding bit in PICR for each peripheral to be idled. 2. Write 1 to the PERI bit in ICR. 3. Execute the IDLE instruction. 4. Every peripheral with its corresponding PICR bit set will go to idle.

3.10.2.4 EMIF Module Idle Procedure

The 5501 EMIF can be idled in one of two ways: through the ICR and through the PICR. The EMIF will go into idle immediately if there is no data transfer taking place within the DMA. If there is a data transfer taking place, then the EMIF will wait until the DMA finishes the current transfer and goes into idle before going into idle itself. Please note that while the EMIF is in idle, the SDRAM refresh function of the EMIF will not be available. The 5501 EMIF can be idled through the ICR only when the following modules are set to idle: CPU, I-Port, ICACHE, DMA, and HPI. To place the EMIF in idle using the ICR, execute the following procedure: 1. Write 1 to the DMA and HPI bits in MICR. 2. Write 1 to the CPUI, MPI, ICACHEI, EMIFI, and IPORTI bits in ICR. 3. Execute the IDLE instruction. 4. EMIF and all modules listed in Step 2 will go to idle. The 5501 EMIF can also be idled through the PICR. To place the EMIF in idle using the PICR, execute the following procedure: 1. Write a 1 to the EMIF bit in PICR. 2. Write a 1 to the PERI bit in ICR. 3. Execute IDLE instruction. 4. EMIF will go to IDLE.

3.10.2.5 IDLE2 Mode

In IDLE2 mode, all modules except the CLOCK module are set to idle state. To place the 5501 in IDLE2 mode, perform the following steps. 1. Write a 1 to all peripheral module bits in the PICR. 2. Write a 1 to the HPI and DMA bits in MICR. 3. Write a 1 to all domain bits in the ICR except the CLOCK domain bit (CLKI). 4. Execute the IDLE instruction. 5. All internal clocks will be disabled, the CLOCK module will remain active.

78

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.10.2.6 IDLE3 Mode

In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5501 in IDLE3 mode, perform the following steps: 1. Clear (i.e., set to 0) the PLLEN bit in PLLCSR to place the PLL in bypass mode. 2. Set the PLLPWRDN and PLLRST bits in PLLCSR to 1. 3. Write a 1 to all peripheral module bits in PICR (write 0x3FFF to PICR). 4. Write a 1 to the HPI and DMA bits in MICR (write 0x0003 to MICR). 5. Write a 1 to all domain bits and bit 9 in the ICR (write 0x03FF to ICR). 6. Execute the IDLE instruction. 7. PLL core is set to power-down mode and all internal clocks are disabled.

3.10.2.7 IDLE3 Mode With Internal Oscillator Disabled

In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator is set to the power-down mode. This is the lowest power-consuming state that 5501 can be placed under. 1. Clear (i.e., set to 0) the PLLEN bit in PLLCSR to place the PLL in bypass mode. 2. Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to 1. 3. Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have interrupt 0 (INT0) wake up the oscillator]. 4. Write a 1 to all peripheral module bits in PICR (write 0x3FFF to PICR). 5. Write a 1 to the HPI and DMA bits in MICR (write 0x0003 to MICR). 6. Write a 1 to all domain bits and bit 9 in the ICR (write 0x03FF to ICR). 7. Execute the IDLE instruction. 8. Internal oscillator is set to power-down mode, PLL core is set to power-down mode, and all internal clocks are disabled. Note that the internal oscillator can be awakened through an NMI or external interrupt as long as that event is specified in the Oscillator Wakeup Control Register and, in the case of an external interrupt, the interrupt is enabled in the CPUs Interrupt Enable Register.

Maskable external interrupts must be enabled through IER prior to setting the 5501 to IDLE.

December 2002 Revised November 2008

SPRS206K

79

Functional Overview

3.10.3

Module Behavior at Entering IDLE State

All transactions must be completed before entering the IDLE state. Table 324 lists the behavior of each module before entering the IDLE state. Table 324. Peripheral Behavior at Entering IDLE State
CLOCK DOMAIN MODULES CPU Interrupt Controller CPU IDLE Controller PLL Controller MODULE BEHAVIOR AT ENTERING IDLE STATE (ASSUMING THE IDLE CONTROL IS SET) Enter IDLE after CPU stops pipeline. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE state after current DMA transfer to internal memory, EMIF, or peripheral, or enter IDLE state immediately if no transfer exists. Master Port DMA DMA has function of Auto-wakeup/Idle with McBSP data transfer during IDLE. HPI ICACHE ICACHE External Bus Selection Register Timer Signal Selection Register CLKOUT Selection Register External Bus Control Register Clock Mode Control Register Timer0/1 and WDT DSP/BIOS Timer Enter IDLE state immediately. Software has to take care of HPI activity. Enter IDLE state after current data transfer from EMIF or program fetch from CPU finishes, or enter IDLE state immediately if no transfer and no access exist. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE state immediately Enter IDLE state immediately External Clock and Frame: Enter IDLE state after current McBSP activity is finished or enter IDLE state immediately if no activity exists. McBSP has function of Auto-wakeup/Idle with DMA transfer during IDLE. Internal Clock and Frame: Enter IDLE state immediately if both transmitter and receiver are in reset (XRST = 0 and RRST = 0). IDLE state not entered otherwise. Enter IDLE state immediately. Enter IDLE state after current I2C activity is finished or enter IDLE state immediately if no activity exists. Enter IDLE state after current UART activity is finished or enter IDLE state immediately if no activity exists. Enter IDLE state immediately. Enter IDLE state immediately. Power-down state if set by software before IDLE Power-down state if set by software before IDLE Enter IDLE mode after current DMA transfer or enter IDLE mode immediately if no activity exists.

Peripheral McBSP0/1

GPIO I2C UART Parallel GPIO PLL divider Clock Generator PLL core Oscillator EMIF EMIF

80

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.10.4

Wake-Up Procedures

It is the users responsibility to ensure that there exists a valid wake-up procedure before entering idle mode. Keep in mind that a hardware reset will restore all modules to their active state. All wake-up procedures are described in the next sections.

3.10.4.1 CPU Domain Wake-up Procedure

The CPU domain can be taken out of idle though an enabled external interrupt or an NMI signal. External interrupts can be enabled through the use of the IER0 and IER1 registers. Other modules, such as the EMIF module, will be taken out of idle automatically when the CPU wakes up. Please see the wake-up procedures for other modules for more information.

3.10.4.2 Master Port Domain (DMA/HPI) Wake-up Procedure

The 5501 DMA module and the HPI module can be taken out of idle simultaneously by executing the following procedure. 1. Write 0 to the MPI bit in ICR. 2. Execute the IDLE instruction. 3. DMA and HPI wake up. It is also possible to wake up the DMA and HPI modules individually through the use of the Master Idle Control Register. To wake up only the DMA or the HPI module, perform the following steps: 1. Write 0 to the DMA bit or the HPI bit in MICR. 2. Selected module wakes up.

3.10.4.3 Peripheral Modules Wake-up Procedure

All 5501 peripherals can be taken out of idle simultaneously by executing the following procedure. 1. Write 0 to the PERI bit in ICR. 2. Execute the IDLE instruction. 3. All idled peripherals wake up. It is also possible to wake up individual peripherals through the use of the Peripheral Idle Control Register by executing the following procedure. 1. Write 0 to the idle control bit of peripheral(s) in PICR. 2. Idled peripherals with 0 in PICR wake up.

December 2002 Revised November 2008

SPRS206K

81

Functional Overview

3.10.4.4 EMIF Module Wake-up Procedure

If both the CPU and the EMIF are in idle, then the EMIF will come out of idle when the CPU is taken out of idle. The CPU can be taken out of idle through the use of an NMI or an enabled external interrupt. External interrupts can be enabled through the IER0 and IER1 registers. If the CPU is not in idle, then the EMIF can be taken out of idle through either of the following two procedures: 1. Write 0 to the PERI bit in ICR. 2. Execute the IDLE instruction. 3. All idled peripherals, including the EMIF, wake up. Or: 1. Write 0 to the EMIF bit in PICR. 2. The EMIF module will wake up.

3.10.4.5 IDLE2 Mode Wake-up Procedure

The 5501 can be taken completely out of IDLE2 mode by executing the following procedure. 1. CPU wakes up from idle through NMI or enabled external interrupt. 2. Write 0 to all bits in the ICR. 3. Execute the IDLE instruction. 4. All internal clocks are enabled and all modules come out of idle.

3.10.4.6 IDLE3 Mode Wake-up Procedure

The 5501 can be taken completely out of IDLE3 mode by executing the following procedure. 1. CPU wakes up from idle through NMI or enabled external interrupt. 2. Write 0 to all bits in the ICR. 3. Execute the IDLE instruction. 4. All internal clocks are enabled and all modules come out of idle. 5. Write 0 to the PLLPWRDN and PLLRST bits in PLLCSR. 6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt. 7. Set the PLLEN bit in PLLCSR to 1. 8. All internal clocks will now come from the PLL core. NOTE: Step 3 can be modified to only wake up certain modules, see previous sections for more information on the wake-up procedures for the 5501 modules.

82

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.10.4.7 IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure

The internal oscillator of the 5501 will be woken up along with the CLOCK module through an NMI or an enabled external interrupt. The source (INT0, INT1, INT2, INT3, or NMI) for the wake-up signal can be selected through the use of the WKEN register. The maskable external interrupts must be enabled through IER0 and IER1 prior to setting the 5501 to Idle 3 mode. The 5501 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference clock cycles) to allow the oscillator input to become stable after waking up from power-down state or reset. When waking up from idle mode, program flow will start after the stabilization period of the oscillator has expired (41 032 reference clock cycles). To take the 5501 (including the internal oscillator) out of the idle 3 state, execute the following procedure: 1. External interrupt or NMI occurs (as specified in the WKEN register) and program flow begins after 41,032 reference clock cycles. 2. CPU wakes up. 3. Write 0 to all bits in the ICR. 4. Execute the IDLE instruction. 5. All internal clocks are enabled and all modules come out of idle. 6. Write 0 to the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR. 7. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt. 8. Set the PLLEN bit in PLLCSR to 1. 9. All internal clocks will now come from the PLL core. NOTE: Step 2 can be modified to only wake up certain modules, see previous sections for more information on the wake-up procedures for the 5501 modules.

3.10.4.8 Summary of Wake-up Procedures

Table 325 summarizes the wake-up procedures. Table 325. Wake-Up Procedures
ISTR VALUE xxx0xxx0 CLOCK DOMAIN STATUS CPU ON Clock Generator ON Other ON/OFF CPU OFF Clock Generator ON Other ON/OFF CPU OFF Clock Generator OFF Other OFF EXIT FROM IDLE 1. DSP software modifies ICR and executes IDLE instruction 2. Reset 1. Unmasked interrupt from external or on-chip module 2. Reset xxx11111 1. Unmasked interrupt from external 2. Reset ICR AFTER WAKE-UP 1. Modified value ISTR AFTER WAKE-UP 1. Updated to ICR modified value after IDLE instruction 2. All 0 1. CPUIS, CLKIS, and EMIFIS/XPORTIS/IPORTIS are set to 0 2. All 0 1. CPUIS, CLKIS, and EMIFIS/XPORTIS/IPORTIS are set to 0 2. All 0

2. All 0 1. Not modified

xxx0xxx1

2. All 0 1. Not modified

2. All 0

December 2002 Revised November 2008

SPRS206K

83

Functional Overview

3.10.5

Auto-Wakeup/Idle Function for McBSP and DMA

The 5501 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in power-down mode for the Auto-wakeup/Idle function to work.]

3.10.6

Clock State of Multiplexed Modules

The clock to the EMIF module is disabled automatically when this module is not selected through the External Bus Selection Register (XBSR). Note that any accesses to disabled modules will result in a bus error.

3.10.7

IDLE Control and Status Registers

The clock domains are controlled by the IDLE Configuration Register (ICR) that allows the user to place different parts of the device in Idle mode. The IDLE Status Register (ISTR) reflects the portion of the device that remains active. The peripheral domain is controlled by the Peripheral IDLE Control Register (PICR). The Peripheral IDLE Status Register (PISTR) reflects the portion of the peripherals that are in the IDLE state. The Master IDLE Control Register (MICR) is used to place the HPI and DMA in Idle mode. The IDLE state of the HPI and DMA is reflected by the Master IDLE Status Register (MISR). The PLL Control/Status Register (PLLCSR) is used to power down the PLL core when the IDLE instruction is executed. The settings in the ICR, PICR, and MICR take effect after the IDLE instruction is executed. For example, writing xxx000001b into the ICR does not indicate that the CPU domain is in IDLE mode; rather, it indicates that after the IDLE instruction, the CPU domain will be in IDLE mode. Procedures for placing portions of the device in Idle mode and taking them out of Idle mode are described in Section 3.10.2 (IDLE Procedures) and Section 3.10.4 (Wake-Up Procedures), respectively. Table 326. Clock Domain Memory-Mapped Registers
ADDRESS 0x0001 0x0002 0x9400 0x9401 0x9402 0x9403 REGISTER NAME IDLE Configuration Register (ICR) IDLE Status Register (ISTR) Peripheral IDLE Control Register (PICR) Peripheral IDLE Status Register (PISTR) Master IDLE Control Register (MICR) Master IDLE Status Register (MISR)

84

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.10.7.1 IDLE Configuration Register (ICR)

15 Reserved R, 000000 10 9 CLKEI R/W, 0 8 IPORTI R/W, 0

7 MPORTI R/W, 0

6 XPORTI R/W, 0

5 EMIFI R/W, 0

4 CLKI R/W, 0

3 PERI R/W, 0

2 ICACHEI R/W, 0

1 MPI R/W, 0

0 CPUI R/W, 0

LEGEND: R = Read, W = Write, n = value at reset This bit must be set to 1 when placing the clock generator in idle; otherwise, a bus error interrupt will be generated.

Figure 326. IDLE Configuration Register Layout (0x0001) Table 327. IDLE Configuration Register Bit Field Description
BIT NAME Reserved CLKEI BIT NO. 1510 9 ACCESS R R/W RESET VALUE 000000 0 Reserved Extended device clock generator idle control bit. The CLKEI bit must be set to 1 along with the CLKI bit in order to properly place the device clock generator in idle. CLKI 0 1 CLKEI 0 1 Device clock generator module remains active after execution of an IDLE instruction. Device clock generator is disabled after execution of an IDLE instruction. DESCRIPTION

Any other combination of CLKI and CLKEI is not valid. Setting CLKI to 1 and executing the IDLE instruction will generate a bus error interrupt if CLKEI is not set to 1. Disabling the clock generator provides the lowest level of power reduction by stopping the system clock. Whenever the clock generator is idled, the CLKEI, CPUI, MPI, ICACHEI, EMIFI, XPORTI, MPORTI, and IPORTI bits must be set to 1 in order to ensure a proper power-down mode. A bus error interrupt will be generated if the idle instruction is executed when CLKI = 1 and any of these bits are not set to 1. IPORTI 8 R/W 0 IPORT idle control bit. The IPORT is used for all ICACHE transactions. IPORTI = 0: IPORTI = 1: MPORTI 7 R/W 0 IPORT remains active after execution of an IDLE instruction IPORT is disabled after execution of an IDLE instruction

MPORT idle control bit. The MPORT is used for all DMA and HPI transactions. MPORTI = 0: MPORTI = 1: MPORT remains active after execution of an IDLE instruction MPORT is disabled after execution of an IDLE instruction

XPORTI

R/W

XPORT idle control bit. The XPORT is used for all I/O memory transactions. XPORTI = 0: XPORTI = 1: XPORT remains active after execution of an IDLE instruction XPORT is disabled after execution of an IDLE instruction

EMIFI

R/W

External Memory Interface (EMIF) idle control bit EMIFI = 0: EMIFI = 1: EMIF module remains active after execution of an IDLE instruction EMIF module is disabled after execution of an IDLE instruction

December 2002 Revised November 2008

SPRS206K

85

Functional Overview

Table 327. IDLE Configuration Register Bit Field Description (Continued)

BIT NAME CLKI BIT NO. 4 ACCESS R/W RESET VALUE 0 DESCRIPTION Device clock generator idle control bit. The CLKEI bit must be set to 1 along with the CLKI bit in order to properly place the device clock generator in idle. CLKI 0 1 CLKEI 0 1 Device clock generator module remains active after execution of an IDLE instruction. Device clock generator is disabled after execution of an IDLE instruction.

Any other combination of CLKI and CLKEI is not valid. Setting CLKI to 1 and executing the IDLE instruction will generate a bus error interrupt if CLKEI is not set to 1. Disabling the clock generator provides the lowest level of power reduction by stopping the system clock. Whenever the clock generator is idled, the CLKEI, CPUI, MPI, ICACHEI, EMIFI, XPORTI, MPORTI, and IPORTI bits must be set to 1 in order to ensure a proper power-down mode. A bus error interrupt will be generated if the idle instruction is executed when CLKI = 1 and any of these bits are not set to 1. PERI 3 R/W 0 Peripheral Idle control bit PERI = 0: PERI = 1: ICACHEI 2 R/W 0 All peripheral modules become/remain active after execution of an IDLE instruction All peripheral modules with 1 in PICR are disabled after execution of an IDLE instruction

ICACHE idle control bit ICACHEI = 0: ICACHEI = 1: ICACHE module remains active after execution of an IDLE instruction ICACHE module is disabled after execution of an IDLE instruction

MPI

R/W

Master peripheral (DMA and HPI) idle control bit MPI = 0: MPI = 1: DMA and HPI modules remain active after execution of an IDLE instruction DMA and HPI modules are disabled after execution of an IDLE instruction

CPUI

R/W

CPU idle control bit CPUI = 0: CPUI = 1: CPU module remains active after execution of an IDLE instruction CPU module is disabled after execution of an IDLE instruction

86

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.10.7.2 IDLE Status Register (ISTR)

15 Reserved R, 0000000 9 8 IPORTIS R, 0

7 MPORTIS R, 0

6 XPORTIS R, 0

5 EMIFIS R, 0

4 CLKIS R, 0

3 PERIS R, 0

2 ICACHEIS R, 0

1 MPIS R, 0

0 CPUIS R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 327. IDLE Status Register Layout (0x0002) Table 328. IDLE Status Register Bit Field Description
BIT NAME Reserved IPORTIS BIT NO. 159 8 ACCESS R R RESET VALUE 0000000 0 Reserved IPORT idle status bit. The IPORT is used for all ICACHE transactions. IPORTIS = 0: IPORTIS = 1: MPORTIS 7 R 0 IPORT is active IPORT is disabled DESCRIPTION

MPORT idle status bit. The MPORT is used for all DMA and HPI transactions. MPORTIS = 0: MPORTIS = 1: MPORT is active MPORT is disabled

XPORTIS

XPORT idle status bit. The XPORT is used for all I/O memory transactions. XPORTIS = 0: XPORTIS = 1: XPORT is active XPORT is disabled

EMIFIS

External Memory Interface (EMIF) idle status bit EMIFIS = 0: EMIFIS = 1: EMIF module is active EMIF module is disabled

CLKIS

Device clock generator idle status bit CLKIS = 0: CLKIS = 1: Device clock generator module is active Device clock generator is disabled

PERIS

Peripheral idle status bit PERIS = 0: PERIS = 1: All peripheral modules are active All peripheral modules are disabled

ICACHEIS

ICACHE idle status bit ICACHEIS = 0: ICACHE module is active ICACHEIS = 1: ICACHE module is disabled

MPIS

DMA and HPI idle status bit MPIS = 0: MPIS = 1: DMA and HPI modules are active DMA and HPI modules are disabled

CPUIS

CPU idle status bit CPUIS = 0: CPUIS = 1: CPU module is active CPU module is disabled

December 2002 Revised November 2008

SPRS206K

87

Functional Overview

3.10.7.3 Peripheral IDLE Control Register (PICR)

15 Reserved R, 00

14

13 MISC R/W, 0

12 EMIF R/W, 0

11 BIOST R/W, 0

10 WDT R/W, 0

9 PIO R/W, 0

8 URT R/W, 0

7 I2C R/W, 0

6 ID R/W, 0

5 IO R/W, 0

4 Reserved R/W, 0

3 SP1 R/W, 0

2 SP0 R/W, 0

1 TIM1 R/W, 0

0 TIM0 R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 328. Peripheral IDLE Control Register Layout (0x9400)

Table 329. Peripheral IDLE Control Register Bit Field Description

BIT NAME Reserved MISC BIT NO. 1514 13 ACCESS R R/W RESET VALUE 00 0 Reserved MISC bit MISC = 0: MISC = 1: Miscellaneous modules remain active when ISTR.PERIS = 1 and IDLE instruction is executed. MIscellaneous module is disabled when ISTR.PERIS = 1 and IDLE instruction is executed. DESCRIPTION

Miscellaneous modules include the XBSR, TIMEOUT Error Register, XBCR, Timer Signal Selection Register, CLKOUT Select Register, and Clock Mode Control Register. EMIF 12 R/W 0 EMIF bit EMIF = 0: EMIF = 1: BIOST 11 R/W 0 EMIF module remains active when ISTR.PERIS = 1 and IDLE instruction is executed. EMIF module is disabled when ISTR.PERIS = 1 and IDLE instruction is executed.

BIOS timer bit BIOST = 0: BIOST = 1: DSP/BIOS timer remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. DSP/BIOS timer is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed.

WDT

10

R/W

Watchdog timer bit WDT = 0: WDT = 1: WDT remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. WDT is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed.

PIO

R/W

Parallel GPIO bit PIO = 0: PIO = 1: Parallel GPIO remains active when ISTR.PERIS = 1 (ISTR.[3]) and the IDLE instruction is executed. Parallel GPIO is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed.

If the peripheral is already in IDLE, setting PERI (bit 3 of ICR) to 0 and executing the IDLE instruction will wake up all peripherals, and PICR bit settings will be ignored. If PERIS (bit 3 of ISTR) = 1, executing the IDLE instruction will wake up the peripheral if its PICR bit is 0.

88

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 329. Peripheral IDLE Control Register Bit Field Description (Continued)
BIT NAME URT BIT NO. 8 ACCESS R/W RESET VALUE 0 UART bit URT = 0: URT = 1: I2C 7 R/W 0 I2C bit I2C = 0: I2C = 1: ID 6 R/W 0 ID bit ID = 0: ID = 1: IO 5 R/W 0 IO bit IO = 0: IO = 1: Reserved SP1 4 3 R/W R/W 0 0 Reserved McBSP1 bit SP1 = 0: SP1 = 1: SP0 2 R/W 0 McBSP0 bit SP0 = 0: SP0 = 1: TIM1 1 R/W 0 TIMER1 bit TIM1 = 0: TIM1 = 1: TIM0 0 R/W 0 TIMER0 bit TIM0 = 0: TIM0 = 1: TIMER0 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. TIMER0 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. TIMER1 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. TIMER1 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP0 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP0 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP1 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP1 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. GPIO remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. GPIO is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. ID remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. ID is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. I2C remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. I2C is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. UART remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. UART is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. DESCRIPTION

If the peripheral is already in IDLE, setting PERI (bit 3 of ICR) to 0 and executing the IDLE instruction will wake up all peripherals, and PICR bit settings will be ignored. If PERIS (bit 3 of ISTR) = 1, executing the IDLE instruction will wake up the peripheral if its PICR bit is 0.

December 2002 Revised November 2008

SPRS206K

89

Functional Overview

3.10.7.4 Peripheral IDLE Status Register (PISTR)

15 Reserved R, 00 7 I2C R, 0 6 ID R, 0 14 13 MISC R, 0 5 IO R, 0 12 EMIF R, 0 4 Reserved R, 0 11 BIOST R, 0 3 SP1 R, 0 10 WDT R, 0 2 SP0 R, 0 9 PIO R, 0 1 TIM1 R, 0 8 URT R, 0 0 TIM0 R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 329. Peripheral IDLE Status Register Layout (0x9401) Table 330. Peripheral IDLE Status Register Bit Field Description
BIT NAME Reserved MISC BIT NO. 1514 13 ACCESS R R RESET VALUE 00 0 Reserved MISC bit MISC = 0: MISC = 1: Miscellaneous modules are active Miscellaneous modules are disabled DESCRIPTION

Miscellaneous modules include the XBSR, TIMEOUT Error Register, XBCR, Timer Signal Selection Register, CLKOUT Select Register, and Clock Mode Control Register. EMIF 12 R 0 EMIF bit EMIF = 0: EMIF = 1: BIOST 11 R 0 EMIF module is active EMIF module is disabled

BIOS timer bit BIOST = 0: BIOST = 1: DSP/BIOS timer is active DSP/BIOS timer is disabled

WDT

10

Watchdog timer bit WDT = 0: WDT = 1: WDT is active WDT is disabled

PIO

Parallel GPIO bit PIO = 0: PIO = 1: Parallel GPIO is active Parallel GPIO is disabled

URT

UART bit URT = 0: URT = 1: UART is active UART is disabled

I2C

I2C bit I2C = 0: I2C = 1: I2C is active I2C is disabled

ID

ID bit ID = 0: ID = 1: ID is active ID is disabled

IO

IO bit IO = 0: IO = 1: GPIO is active GPIO is disabled

90

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 330. Peripheral IDLE Status Register Bit Field Description (Continued)
BIT NAME Reserved SP1 BIT NO. 4 3 ACCESS R R RESET VALUE 0 0 Reserved McBSP1 bit SP1 = 0: SP1 = 1: SP0 2 R 0 McBSP0 bit SP0 = 0: SP0 = 1: TIM1 1 R 0 TIMER1 bit TIM1 = 0: TIM1 = 1: TIM0 0 R 0 TIMER0 bit TIM0 = 0: TIM0 = 1: TIMER0 is active TIMER0 is disabled TIMER1 is active TIMER1 is disabled McBSP0 is active McBSP0 is disabled McBSP1 is active McBSP1 is disabled DESCRIPTION

3.10.7.5 Master IDLE Control Register (MICR)

15 Reserved R, 00000000 8

7 Reserved R, 000000 LEGEND: R = Read, W = Write, n = value at reset

1 HPI R/W, 0

0 DMA R/W, 0

Figure 330. Master IDLE Control Register Layout (0x9402) Table 331. Master IDLE Control Register Bit Field Description
BIT NAME Reserved HPI BIT NO. 152 1 ACCESS R R/W RESET VALUE 00000000000000 0 Reserved HPI bit HPI = 0: HPI = 1: DMA 0 R/W 0 DMA bit DMA = 0: DMA = 1: DMA remains active when ISTR.MPIS becomes 1 DMA is disabled when ISTR.MPIS becomes 1 HPI remains active when ISTR.MPIS becomes 1 HPI is disabled when ISTR.MPIS becomes 1 DESCRIPTION

December 2002 Revised November 2008

SPRS206K

91

Functional Overview

3.10.7.6 Master IDLE Status Register (MISR)

15 Reserved R, 00000000 8

7 Reserved R, 000000 LEGEND: R = Read, W = Write, n = value at reset

1 HPI R, 0

0 DMA R, 0

Figure 331. Master IDLE Status Register Layout (0x9403) Table 332. Master IDLE Status Register Bit Field Description
BIT NAME Reserved HPI BIT NO. 152 1 ACCESS R R RESET VALUE 00000000000000 0 Reserved HPI bit HPI = 0: HPI = 1: DMA 0 R 0 DMA bit DMA = 0: DMA = 1: DMA is active DMA is in IDLE status HPI is active HPI is in IDLE status DESCRIPTION

3.11 General-Purpose I/O (GPIO)

The 5501 includes an 8-bit I/O port solely for general-purpose input and output. Several dual-purpose (multiplexed) pins complement the dedicated GPIO pins. The following sections describe the 8-bit GPIO port as well as the dual GPIO functions of the Parallel Port Mux and Host Port Mux pins.

3.11.1

General-Purpose I/O Port

The general-purpose I/O port consists of eight individually bit-selectable I/O pins GPIO0 (LSB) through GPIO7 (MSB). The I/O port is controlled using two registersIODIR and IODATAthat can be accessed by the CPU or by the DMA, via the peripheral bus controller. The General-Purpose I/O Direction Register (IODIR) is mapped at address 0x3400, and the General-Purpose I/O Data Register (IODATA) is mapped at address 0x3401. Figure 332 and Figure 333 show the bit layout of IODIR and IODATA, respectively. Table 333 and Table 334 describe the bit fields of these registers.

92

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.11.1.1 General-Purpose I/O Direction Register (IODIR)

15 Reserved R, 00000000 7 IO7DIR R/W, 0 6 IO6DIR R/W, 0 5 IO5DIR R/W, 0 4 IO4DIR R/W, 0 3 IO3DIR R/W, 0 2 IO2DIR R/W, 0 1 IO1DIR R/W, 0 0 IO0DIR R/W, 0 8

LEGEND: R = Read, W = Write, n = value at reset

Figure 332. GPIO Direction Register Layout (0x3400) Table 333. GPIO Direction Register Bit Field Description
BIT NAME Reserved IOxDIR BIT NO. 158 70 ACCESS R R/W RESET VALUE 00000000 00000000 Reserved Data direction bits that configure the GPIO pins as inputs or outputs. IOxDIR = 0: IOxDIR = 1: x = value from 0 to 7 Configure corresponding GPIO pin as an input Configure corresponding GPIO pin as an output DESCRIPTION

3.11.1.2 General-Purpose I/O Data Register (IODATA)

15 Reserved R, 00000000 7 IO7D R/W, pin 6 IO6D R/W, pin 5 IO5D R/W, pin 4 IO4D R/W, pin 3 IO3D R/W, pin 2 IO2D R/W, pin 1 IO1D R/W, pin 0 IO0D R/W, pin 8

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 333. GPIO Data Register Layout (0x3401) Table 334. GPIO Data Register Bit Field Description
BIT NAME Reserved IOxD BIT NO. 158 70 ACCESS R R/W RESET VALUE 00000000 Depends on the signal level on the corresponding I/O pin Reserved Data bits that are used to control the level of the I/O pins configured as outputs and to monitor the level of the I/O pins configured as inputs. If IOxDIR = 0, then: IOxD = 0: Corresponding GPIO pin is read as a low IOxD = 1: Corresponding GPIO pin is read as a high If IOxDIR = 1, then: IOxD = 0: Set corresponding GPIO pin to low IOxD = 1: Set corresponding GPIO pin to high x = value from 0 to 7 DESCRIPTION

December 2002 Revised November 2008

SPRS206K

93

Functional Overview

3.11.2

Parallel Port General-Purpose I/O (PGPIO)

Four address pins (A[21:18]), 16 data pins (D[31:16]), 16 control signals (C[15:0]), 8 host data pins (HD[7:0]), and 2 HPI control pins (HC0, HC1) can be individually enabled as PGPIO when the Parallel/Host Port Mux Mode bit field of the External Bus Selection Register (XBSR) is cleared for PGPIO mode (see Table 335). These pins are controlled by three sets of registers: the PGPIO enable registers, the PGPIO direction registers, and the PGPIO data registers. The PGPIO enable registers PGPIOEN0PGPIOEN2 (see Figure 334, Figure 337, and Figure 340) determine if the output function of the PGPIO pins is enabled or disabled. The PGPIO direction registers PGPIODIR0PGPIODIR2 (see Figure 335, Figure 338, and Figure 341) determine if corresponding bits in the PGPIO data registers specify an output value or an input value. The PGPIO data registers PGPIODAT0PGPIODAT2 (see Figure 336, Figure 339, and Figure 342) store the value read or written externally.

To use a PGPIO pin as an output, its corresponding bit must be set to 1 in both the enable and direction registers. The state of the pin is then controlled through its bit in the data register. Conversely, to use a PGPIO pin as an input, its corresponding bit must be cleared to 0 in both the enable and the direction registers. The state of the pin can then be read from its bit in the data register. NOTE: The enable registers PGPIOENn cannot override the External Bus Selection Register (XBSR) setting. Table 335. TMS320VC5501 PGPIO Cross-Reference
PIN PARALLEL/HOST PORT MUX MODE = 0 (PGPIO) EMIF Address Bus A[21:18] D[31:16] C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 PGPIO[3:0] EMIF Data Bus PGPIO[19:4] EMIF Control Bus PGPIO20 PGPIO21 PGPIO22 PGPIO23 PGPIO24 PGPIO25 PGPIO26 PGPIO27 PGPIO28 PGPIO29 PGPIO30 PGPIO31 PGPIO32 PGPIO33 PGPIO34 PGPIO35 EMIF.ARE/SADS/SDCAS/SRE EMIF.AOE/SOE/SDRAS EMIF.AWE/SWE/SDWE EMIF.ARDY EMIF.CE0 EMIF.CE1 EMIF.CE2 EMIF.CE3 EMIF.BE0 EMIF.BE1 EMIF.BE2 EMIF.BE3 EMIF.SDCKE EMIF.SOE3 EMIF.HOLD EMIF.HOLDA EMIF.D[31:16] EMIF.A[21:18] PARALLEL/HOST PORT MUX MODE = 1 (FULL EMIF)

94

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 335. TMS320VC5501 PGPIO Cross-Reference (Continued)

PIN PARALLEL/HOST PORT MUX MODE = 0 (PGPIO) HPI Data Bus HD[7:0] HC0 HC1 PGPIO[43:36] HPI Control Bus PGPIO44 PGPIO45 HPI.HAS HPI.HBIL HPI.HD[7:0] PARALLEL/HOST PORT MUX MODE = 1 (FULL EMIF)

3.11.2.1 Parallel GPIO Enable Register 0 (PGPIOEN0)

15 IO15EN R/W, 0 7 IO7EN R/W, 0 14 IO14EN R/W, 0 6 IO6EN R/W, 0 13 IO13EN R/W, 0 5 IO5EN R/W, 0 12 IO12EN R/W, 0 4 IO4EN R/W, 0 11 IO11EN R/W, 0 3 IO3EN R/W, 0 10 IO10EN R/W, 0 2 IO2EN R/W, 0 9 IO9EN R/W, 0 1 IO1EN R/W, 0 8 IO8EN R/W, 0 0 IO0EN R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 334. Parallel GPIO Enable Register 0 Layout (0x4400) Table 336. Parallel GPIO Enable Register 0 Bit Field Description
BIT NAME IOxEN BIT NO. 150 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Enable or disable output function of the corresponding I/O pins. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. IOxEN = 0: Output function of the PGPIOx pin is disabledi.e., the pin cannot drive an output signal; it can only be used as an input. When IOxEN = 0, IOxDIR must also be cleared to 0. Output function of the PGPIOx pin is enabledi.e., the pin is used to drive an output signal. When IOxEN = 0, IOxDIR must also be set to 1; otherwise, the output value is undefined.

IOxEN = 1:

x = value from 0 to 15

December 2002 Revised November 2008

SPRS206K

95

Functional Overview

3.11.2.2 Parallel GPIO Direction Register 0 (PGPIODIR0)

15 IO15DIR R/W, 0 7 IO7DIR R/W, 0 14 IO14DIR R/W, 0 6 IO6DIR R/W, 0 13 IO13DIR R/W, 0 5 IO5DIR R/W, 0 12 IO12DIR R/W, 0 4 IO4DIR R/W, 0 11 IO11DIR R/W, 0 3 IO3DIR R/W, 0 10 IO10DIR R/W, 0 2 IO2DIR R/W, 0 9 IO9DIR R/W, 0 1 IO1DIR R/W, 0 8 IO8DIR R/W, 0 0 IO0DIR R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 335. Parallel GPIO Direction Register 0 Layout (0x4401) Table 337. Parallel GPIO Direction Register 0 Bit Field Description
BIT NAME IOxDIR BIT NO. 150 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Data direction bits specify if corresponding bits in the data registers specify an output value or an input value. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. IOxDIR = 0: IOxDIR = 1: Corresponding bit in the data register specifies the value read on the PGPIOx pin (input). When IOxDIR = 0, IOxEN must also be cleared to 0. Corresponding bit in the data register specifies the value driven on the PGPIOx pin (output). When IOxDIR = 1, IOxEN must also be set to 1.

x = value from 0 to 15

96

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.11.2.3 Parallel GPIO Data Register 0 (PGPIODAT0)

15 IO15DAT R/W, pin 7 IO7DAT R/W, pin 14 IO14DAT R/W, pin 6 IO6DAT R/W, pin 13 IO13DAT R/W, pin 5 IO5DAT R/W, pin 12 IO12DAT R/W, pin 4 IO4DAT R/W, pin 11 IO11DAT R/W, pin 3 IO3DAT R/W, pin 10 IO10DAT R/W, pin 2 IO2DAT R/W, pin 9 IO9DAT R/W, pin 1 IO1DAT R/W, pin 8 IO8DAT R/W, pin 0 IO0DAT R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 336. Parallel GPIO Data Register 0 Layout (0x4402) Table 338. Parallel GPIO Data Register 0 Bit Field Description
BIT NAME IOxDAT BIT NO. 150 ACCESS R/W RESET VALUE Depends on the signal level on the corresponding I/O pin DESCRIPTION Data bits that are used to either control the level of the corresponding I/O pins configured as output pins or to monitor the level of the corresponding I/O pins configured as input pins. The function of the data register bits is determined by the setting of the direction register bits. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. If IOxEN = 0 and IOxDIR = 0, then IOxDAT is used to read the value of the PGPIOx pin: IOxDAT = 0: IOxDAT = 1: PGPIOx pin is read as a low PGPIOx pin is read as a high

If IOxEN = 1 and IOxDIR = 1, then IOxDAT is used to set the value of the PGPIOx pin: IOxDAT = 0: IOxDAT = 1: Set PGPIOx pin to low Set PGPIOx pin to high

Note that other combinations of IOxEN and IOxDIR are not supportedi.e., IOxEN and IOxDIR must always be set to the same value. x = value from 0 to 15

December 2002 Revised November 2008

SPRS206K

97

Functional Overview

3.11.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1)

15 IO31EN R/W, 0 7 IO23EN R/W, 0 14 IO30EN R/W, 0 6 IO22EN R/W, 0 13 IO29EN R/W, 0 5 IO21EN R/W, 0 12 IO28EN R/W, 0 4 IO20EN R/W, 0 11 IO27EN R/W, 0 3 IO19EN R/W, 0 10 IO26EN R/W, 0 2 IO18EN R/W, 0 9 IO25EN R/W, 0 1 IO17EN R/W, 0 8 IO24EN R/W, 0 0 IO16EN R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 337. Parallel GPIO Enable Register 1 Layout (0x4403) Table 339. Parallel GPIO Enable Register 1 Bit Field Description
BIT NAME IOxEN BIT NO. 150 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Enable or disable output function of the corresponding I/O pins. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. IOxEN = 0: Output function of the PGPIOx pin is disabledi.e., the pin cannot drive an output signal; it can only be used as an input. When IOxEN = 0, IOxDIR must also be cleared to 0. Output function of the PGPIOx pin is enabledi.e., the pin is used to drive an output signal. When IOxEN = 0, IOxDIR must also be set to 1; otherwise, the output value is undefined.

IOxEN = 1:

x = value from 16 to 31

98

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.11.2.5 Parallel GPIO Direction Register 1 (PGPIODIR1)

15 IO31DIR R/W, 0 7 IO23DIR R/W, 0 14 IO30DIR R/W, 0 6 IO22DIR R/W, 0 13 IO29DIR R/W, 0 5 IO21DIR R/W, 0 12 IO28DIR R/W, 0 4 IO20DIR R/W, 0 11 IO27DIR R/W, 0 3 IO19DIR R/W, 0 10 IO26DIR R/W, 0 2 IO18DIR R/W, 0 9 IO25DIR R/W, 0 1 IO17DIR R/W, 0 8 IO24DIR R/W, 0 0 IO16DIR R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 338. Parallel GPIO Direction Register 1 Layout (0x4404) Table 340. Parallel GPIO Direction Register 1 Bit Field Description
BIT NAME IOxDIR BIT NO. 150 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Data direction bits specify if corresponding bits in the data registers specify an output value or an input value. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. IOxDIR = 0: IOxDIR = 1: Corresponding bit in the data register specifies the value read on the PGPIOx pin (input). When IOxDIR = 0, IOxEN must also be cleared to 0. Corresponding bit in the data register specifies the value driven on the PGPIOx pin (output). When IOxDIR = 1, IOxEN must also be set to 1.

x = value from 16 to 31

December 2002 Revised November 2008

SPRS206K

99

Functional Overview

3.11.2.6 Parallel GPIO Data Register 1 (PGPIODAT1)

15 IO31DAT R/W, pin 7 IO23DAT R/W, pin 14 IO30DAT R/W, pin 6 IO22DAT R/W, pin 13 IO29DAT R/W, pin 5 IO21DAT R/W, pin 12 IO28DAT R/W, pin 4 IO20DAT R/W, pin 11 IO27DAT R/W, pin 3 IO19DAT R/W, pin 10 IO26DAT R/W, pin 2 IO18DAT R/W, pin 9 IO25DAT R/W, pin 1 IO17DAT R/W, pin 8 IO24DAT R/W, pin 0 IO16DAT R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 339. Parallel GPIO Data Register 1 Layout (0x4405) Table 341. Parallel GPIO Data Register 1 Bit Field Description
BIT NAME IOxDAT BIT NO. 150 ACCESS R/W RESET VALUE Depends on the signal level on the corresponding I/O pin DESCRIPTION Data bits that are used to either control the level of the corresponding I/O pins configured as output pins or to monitor the level of the corresponding I/O pins configured as input pins. The function of the data register bits is determined by the setting of the direction register bits. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. If IOxEN = 0 and IOxDIR = 0, then IOxDAT is used to read the value of the PGPIOx pin: IOxDAT = 0: IOxDAT = 1: PGPIOx pin is read as a low PGPIOx pin is read as a high

If IOxEN = 1 and IOxDIR = 1, then IOxDAT is used to set the value of the PGPIOx pin: IOxDAT = 0: IOxDAT = 1: Set PGPIOx pin to low Set PGPIOx pin to high

Note that other combinations of IOxEN and IOxDIR are not supportedi.e., IOxEN and IOxDIR must always be set to the same value. x = value from 16 to 31

100

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.11.2.7 Parallel GPIO Enable Register 2 (PGPIOEN2)

15 Reserved R/W, 00 7 IO39EN R/W, 0 6 IO38EN R/W, 0 14 13 IO45EN R/W, 0 5 IO37EN R/W, 0 12 IO44EN R/W, 0 4 IO36EN R/W, 0 11 IO43EN R/W, 0 3 IO35EN R/W, 0 10 IO42EN R/W, 0 2 IO34EN R/W, 0 9 IO41EN R/W, 0 1 IO33EN R/W, 0 8 IO40EN R/W, 0 0 IO32EN R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 340. Parallel GPIO Enable Register 2 Layout (0x4406) Table 342. Parallel GPIO Enable Register 2 Bit Field Description
BIT NAME Reserved IOxEN BIT NO. 1514 130 ACCESS R/W R/W RESET VALUE 00 00000000000000 Reserved Enable or disable output function of the corresponding I/O pins. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. IOxEN = 0: Output function of the PGPIOx pin is disabledi.e., the pin cannot drive an output signal; it can only be used as an input. When IOxEN = 0, IOxDIR must also be cleared to 0. Output function of the PGPIOx pin is enabledi.e., the pin is used to drive an output signal. When IOxEN = 0, IOxDIR must also be set to 1; otherwise, the output value is undefined. DESCRIPTION

IOxEN = 1:

x = value from 32 to 45

December 2002 Revised November 2008

SPRS206K

101

Functional Overview

3.11.2.8 Parallel GPIO Direction Register 2 (PGPIODIR2)

15 Reserved R/W, 00 7 IO39DIR R/W, 0 6 IO38DIR R/W, 0 14 13 IO45DIR R/W, 0 5 IO37DIR R/W, 0 12 IO44DIR R/W, 0 4 IO36DIR R/W, 0 11 IO43DIR R/W, 0 3 IO35DIR R/W, 0 10 IO42DIR R/W, 0 2 IO34DIR R/W, 0 9 IO41DIR R/W, 0 1 IO33DIR R/W, 0 8 IO40DIR R/W, 0 0 IO32DIR R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 341. Parallel GPIO Direction Register 2 Layout (0x4407) Table 343. Parallel GPIO Direction Register 2 Bit Field Description
BIT NAME Reserved IOxDIR BIT NO. 1514 130 ACCESS R/W R/W RESET VALUE 00 00000000000000 Reserved Data direction bits specify if corresponding bits in the data registers specify an output value or an input value. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. IOxDIR = 0: IOxDIR = 1: Corresponding bit in the data register specifies the value read on the PGPIOx pin (input). When IOxDIR = 0, IOxEN must also be cleared to 0. Corresponding bit in the data register specifies the value driven on the PGPIOx pin (output). When IOxDIR = 1, IOxEN must also be set to 1. DESCRIPTION

x = value from 32 to 45

102

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.11.2.9 Parallel GPIO Data Register 2 (PGPIODAT2)

15 Reserved R/W, 00 7 IO39DAT R/W, pin 6 IO38DAT R/W, pin 14 13 IO45DAT R/W, pin 5 IO37DAT R/W, pin 12 IO44DAT R/W, pin 4 IO36DAT R/W, pin 11 IO43DAT R/W, pin 3 IO35DAT R/W, pin 10 IO42DAT R/W, pin 2 IO34DAT R/W, pin 9 IO41DAT R/W, pin 1 IO33DAT R/W, pin 8 IO40DAT R/W, pin 0 IO32DAT R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 342. Parallel GPIO Data Register 2 Layout (0x4408) Table 344. Parallel GPIO Data Register 2 Bit Field Description
BIT NAME Reserved IOxDAT BIT NO. 1514 130 ACCESS R/W R/W RESET VALUE 00 Depends on the signal level on the corresponding I/O pin Reserved Data bits that are used to either control the level of the corresponding I/O pins configured as output pins or to monitor the level of the corresponding I/O pins configured as input pins. The function of the data register bits is determined by the setting of the direction register bits. See Table 335, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. If IOxEN = 0 and IOxDIR = 0, then IOxDAT is used to read the value of the PGPIOx pin: IOxDAT = 0: IOxDAT = 1: PGPIOx pin is read as a low PGPIOx pin is read as a high DESCRIPTION

If IOxEN = 1 and IOxDIR = 1, then IOxDAT is used to set the value of the PGPIOx pin: IOxDAT = 0: IOxDAT = 1: Set PGPIOx pin to low Set PGPIOx pin to high

Note that other combinations of IOxEN and IOxDIR are not supportedi.e., IOxEN and IOxDIR must always be set to the same value. x = value from 32 to 45

December 2002 Revised November 2008

SPRS206K

103

Functional Overview

3.12 External Bus Control Register

The External Bus Control Register is used to disable/enable the bus pullups, pulldowns, and bus holders of the 5501 pins. Table 345 lists which 5501 pins have pullups, pulldowns, and bus holders, and which bit on the XBCR enables/disables that feature. Please note that for pins with dual functionality (e.g., HC0, HC1, C0, etc.), the bus holder, pullup, and pulldown feature of each pin can be enabled or disabled regardless of the function of the pin at the time.

Table 345. Pins With Pullups, Pulldowns, and Bus Holders

XBCR CONTROL BIT PIN TCK TDI TEST TMS TRST EMU1/OFF EMU WDT EMU0 NMI/WDTOUT HC0 HC1 HCNTL0 HCNTL1 HCS HC HR/W HDS1 HDS2 HRDY HINT HD HD[7:0] C0 C1 C2 C3 C4 C5 C6 C7 PC C8 C9 C10 C11 C12 C13 C14 C15 PD PA D[31:0] A[21:2] FEATURE Pullup Pullup Pullup Pulldown Pullup Pullup Pullup Pullup Pulldown Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Bus Holder Bus Holder Bus Holder Bus Holder Pullup Bus Holder Bus Holder Bus Holder Bus Holder Bus Holder Bus Holder Bus Holder Bus Holder Bus Holder Bus Holder Pullup Bus Holder Bus Holder Bus Holder

104

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.12.1
15

External Bus Control Register (XBCR)

8 Reserved R, 00000000

7 EMU R/W, 0

6 TEST R/W, 0

5 WDT R/W, 0

4 HC R/W, 0

3 HD R/W, 0

2 PC R/W, 0

1 PD R/W, 0

0 PA R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 343. External Bus Control Register Layout (0x8800) Table 346. External Bus Control Register Bit Field Description
BIT NAME Reserved EMU BIT NO. 158 7 ACCESS R R/W RESET VALUE 00000000 0 Reserved EMU bit EMU = 0: EMU = 1: TEST 6 R/W 0 TEST bit TEST = 0: Pullups/pulldowns on test pins are enabled (does not include EMU1 and EMU0 pins) TEST = 1: Pullups/pulldowns on test pins are disabled (does not include EMU1 and EMU0 pins) WDT 5 R/W 0 WDT bit WDT = 0: Pullup on NMI/WDTOUT pin is enabled WDT = 1: Pullup on NMI/WDTOUT pin is disabled HC 4 R/W 0 HPI control signal bit HC = 0: HC = 1: HD 3 R/W 0 Pullups/pulldowns on HPI control pins (HC0 and HC1) are enabled Pullups/pulldowns on HPI control pins (HC0 and HC1) are disabled Pullups on EMU1 and EMU0 pins are enabled. Pullups on EMU1 and EMU0 pins are disabled. DESCRIPTION

HPI data bus bit HD = 0: HD = 1: Bus holders on HPI data bus (pins HD[7:0]) are enabled Bus holders on HPI data bus (pins HD[7:0]) are disabled

PC

R/W

EMIF control signals PC = 0: PC = 1: Bus holders and pullups on EMIF control pins are enabled Bus holders and pullups on EMIF control pins are disabled

PD

R/W

EMIF data bus signals PD = 0: PD = 1: Bus holders on EMIF data bus (pins D[31:0]) are enabled Bus holders on EMIF data bus (pins D[31:0]) are disabled

PA

R/W

EMIF address bus signals PA = 0: PA = 1: Bus holders on EMIF address bus (pins A[21:2]) are enabled Bus holders on EMIF address bus (pins A[21:2]) are disabled

December 2002 Revised November 2008

SPRS206K

105

Functional Overview

3.13 Internal Ports and System Registers

The 5501 includes three internal ports that interface the CPU core with the peripheral modules. Although these ports cannot be directly controlled by user code, the registers associated with each port can be used to monitor a number of error conditions that could be generated through illegal operation of the 5501. The port registers are described in the following sections. The 5501 also includes two registers that can be used to monitor and control several aspects of the interface between the CPU and the system-level peripherals, these registers are also described in the following sections.

3.13.1

XPORT Interface

The XPORT interfaces the CPU core to all peripheral modules. The XPORT will generate bus errors for invalid accesses to any registers that fall under the ranges shown in Table 347. The INTERREN bit of the XPORT Configuration Register (XCR) controls the bus error feature of the XPORT. The INTERR bit of the XPORT Bus Error Register (XERR) is set to 1 when an error occurs during an access to a register listed in Table 347. The EBUS and DBUS bits can be used to distinguish whether the error occurred during a write or read access. Table 347. I/O Addresses Under Scope of XPORT
I/O ADDRESS RANGE 0x00000x03FF 0x14000x17FF 0x20000x23FF

The PERITO bit of the XERR is used to indicate that a CPU, DMA, or HPI access to a disabled/idled peripheral module has generated a time-out error. The time-out error feature is enabled through the PERITOEN bit of the Time-Out Control Register (TOCR). A time-out error is generated when 512 clock cycles pass without a response from the peripheral register. The XPORT can be placed into idle by setting the XPORTI bit of the Idle Control Register (ICR) and executing the IDLE instruction. When the XPORT is in idle, it will stop accepting new peripheral module requests and it will also not check for internal I/O bus errors. If there is a request from the CPU core or a peripheral module, the XPORT will not respond and hang. The ICR register will generate a bus error if the XPORT is idled without the CPU or Master Port domains being in idle mode.

106

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.13.1.1 XPORT Configuration Register (XCR)

The XPORT Configuration Register bit layout is shown in Figure 344 and the bits are described in Table 348.

15 INTERREN R/W, 1

14 Reserved R, 0000000

7 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset

Figure 344. XPORT Configuration Register Layout (0x0100) Table 348. XPORT Configuration Register Bit Field Description
BIT NAME INTERREN BIT NO. 15 ACCESS R/W RESET VALUE 1 INTERREN bit INTERREN = 0: The XPORT will not generate a bus error for invalid accesses to registers listed in Table 347. Note that any invalid accesses to these registers will hang the pipeline. The XPORT will generate a bus error for invalid accesses to registers listed in Table 347. Note that when a bus error occurs, any data returned by the read instruction will not be valid. DESCRIPTION

INTERREN = 1:

Reserved 140 R 000000000000000 Reserved This feature will not work if the XPORT is placed in idle through the ICR. However, a bus error will be generated if the XPORT is placed in idle without the CPU being in idle.

December 2002 Revised November 2008

SPRS206K

107

Functional Overview

3.13.1.2 XPORT Bus Error Register (XERR)

The XPORT Bus Error Register bit layout is shown in Figure 345 and the bits are described in Table 349.

15 INTERR R, 0

14 Reserved R, 00

13

12 PERITO R, 0

11 Reserved R, 0000

7 Reserved R, 000

4 EBUS R, 0

3 DBUS R, 0

2 Reserved R, 000

LEGEND: R = Read, W = Write, n = value at reset

Figure 345. XPORT Bus Error Register Layout (0x0102) Table 349. XPORT Bus Error Register Bit Field Description
BIT NAME INTERR BIT NO. 15 ACCESS R RESET VALUE 0 INTERR bit INTERR = 0: INTERR = 1: Reserved PERITO 1413 12 R R 00 0 Reserved PERITO bit PERITO = 0: PERITO = 1: Reserved EBUS 115 4 R R 0000000 0 Reserved EBUS error bit EBUS = 0: EBUS = 1: DBUS 3 R 0 DBUS error bit DBUS = 0: DBUS = 1: No error An error occurred during a DBUS access (read) to one of the registers listed in Table 347. No error An error occurred during an EBUS access (write) to one of the registers listed in Table 347. No error A time-out error occurred during an access to a peripheral register. No error An error occurred during an access to one of the registers listed in Table 347. DESCRIPTION

Reserved 20 R 000 Reserved See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus.

108

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.13.2

DPORT Interface

The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on the EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write posting registers, which are freely associated with E and F bus writes, exist within the DPORT and are used to store the write address and data so that writes can be zero wait state for the CPU. External memory writes will not generate stalls to the CPU unless the two write posting registers are filled. Write posting is enabled by setting the WPE bit of the DCR to 1. The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external memory has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit of the Time-Out Control Register (TOCR). This function is not recommended during normal operation of the 5501. The DPORT can be placed into idle through the EMIFI bit of the Idle Control Register (ICR) and executing the IDLE instruction. When the DPORT is in idle, it will stop accepting new EMIF requests. If there is a request from the CPU or the EMIF, the DPORT will not respond and hang. The ICR register will generate a bus error if the DPORT is idled without the CPU or Master Port domains being in idle.

3.13.2.1 DPORT Configuration Register (DCR)

The DPORT Configuration Register bit layout is shown in Figure 346 and the bits are described in Table 350.

15 Reserved R, 00000000

7 WPE R/W, 0

6 Reserved R, 0000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 346. DPORT Configuration Register Layout (0x0200) Table 350. DPORT Configuration Register Bit Field Description
BIT NAME Reserved WPE BIT NO. 158 7 ACCESS R R/W RESET VALUE 00000000 0 Reserved Write Posting Enable bit WPE = 0: WPE = 1: Write posting disabled Write posting enabled DESCRIPTION

Reserved 60 R 0000000 Reserved Write posting should not be enabled or disabled while the EMIF is conducting a transaction with external memory.

December 2002 Revised November 2008

SPRS206K

109

Functional Overview

3.13.2.2 DPORT Bus Error Register (DERR)

The DPORT Bus Error Register bit layout is shown in Figure 347 and the bits are described in Table 351.

15 Reserved R, 000

13

12 EMIFTO R, 0

11 Reserved R, 0000

7 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset

Figure 347. DPORT Bus Error Register Layout (0x0202) Table 351. DPORT Bus Error Register Bit Field Description
BIT NAME Reserved EMIFTO BIT NO. 1513 12 ACCESS R R RESET VALUE 000 0 Reserved EMIFTO bit EMIFTO = 0: EMIFTO = 1: Reserved 110 R 000000000000 Reserved No error Error 1 error DESCRIPTION

110

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.13.3

IPORT Interface

The IPORT interfaces the I-Cache to the EMIF module. The ICACHETO bit of the IPORT Bus Error Register (IERR) can be used to determine if a time-out error has occurred during an ICACHE access to external memory. The time-out feature is enabled through the EMIFTOEN bit of the Time-Out Control Register (TOCR). The IPORT can be placed into idle through the IPORTI bit of the Idle Control Register (ICR) and executing the IDLE instruction. The IPORT will go into idle when there are no new requests from the ICACHE. When the IPORT is in idle, it will stop accepting new requests from the CPU, it is important that the program flow not use external memory in this case. If there are requests from the CPU, the IPORT will not respond and hang. The ICR register will generate a bus error if the IPORT is idled without the CPU domain being in idle.

3.13.3.1 IPORT Bus Error Register (IERR)

The IPORT Bus Error Register bit layout is shown in Figure 348 and the bits are described in Table 352.

15 Reserved R, 000

13

12 ICACHETO R, 0

11 Reserved R, 0000

7 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset

Figure 348. IPORT Bus Error Register Layout (0x0302) Table 352. IPORT Bus Error Register Bit Field Description
BIT NAME Reserved ICACHETO BIT NO. 1513 12 ACCESS R R RESET VALUE 000 0 Reserved ICACHETO bit ICACHETO = 0: ICACHETO = 1: Reserved 110 R 000000000000 Reserved No error A time-out error occurred during an ICACHE access to external memory. DESCRIPTION

December 2002 Revised November 2008

SPRS206K

111

Functional Overview

3.13.4

System Configuration Register (CONFIG)

The System Configuration Register can be used to determine the operational state of the ICACHE. If the ICACHE is not functioning, the CACHEPRES bit of the CONFIG register will be cleared. If the ICACHE is functioning normally, this bit will be set. The System Configuration Register bit layout is shown in Figure 349 and the bits are described in Table 353.

15 Reserved R, 10000010

7 Reserved R, 00

5 CACHEPRES R, 0

4 Reserved RW, 0

3 Reserved R, 0000

LEGEND: R = Read, W = Write, n = value at reset This Reserved bit must be kept as zero during any writes to CONFIG.

Figure 349. System Configuration Register Layout (0x07FD) Table 353. System Configuration Register Bit Field Description
BIT NAME Reserved CACHEPRES BIT NO. 156 5 ACCESS R R RESET VALUE 1000001000 0 Reserved ICACHE present CACHEPRES = 0: ICACHE is not functioning CACHEPRES = 1: ICACHE is enabled and working Reserved 4 R/W 0 Reserved Reserved 30 R 0000 Reserved This Reserved bit must be kept as zero during any writes to CONFIG. DESCRIPTION

112

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.13.5

Time-Out Control Register (TOCR)

The Time-Out Control Register can be used to select whether or not a time-out error is generated when an access to a disabled/idled peripheral module occurs. If the CPU or DMA access a disabled/idle peripheral module and 512 CPU clock cycles pass without an acknowledgement from the peripheral module, then a time-out error will be sent to the corresponding module if bit 1 in the Time-Out Control Register is set. A time-out error will generate a CPU bus error that can be serviced through software by using the bus error interrupt (BERR) (see Section 3.16, Interrupts, for more information on interrupts). If the DMA gets a time-out error, it will set the TIMEOUT bit in the DMA Status Register (DMACSR) and generate a time-out error that can be serviced through software by the CPU [see the TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613) for more information on using this feature of the DMA]. The Time-Out Control Register can also be used to select whether or not a time-out error is generated when a memory access through the EMIF module stalls for more than 512 CPU clock cycles. It is recommended that this feature not be used for it can cause unexpected results.
15 Reserved R, 00000000 7 Reserved R, 000000 LEGEND: R = Read, W = Write, n = value at reset 2 1 EMIFTOEN R/W, 0 0 PERITOEN R/W, 1 8

Figure 350. Time-Out Control Register Layout (0x9000) Table 354. Time-Out Control Register Bit Field Description
BIT NAME Reserved EMIFTOEN BIT NO. 152 1 ACCESS R R/W RESET VALUE 00000000000000 0 Reserved EMIF time-out control bit EMIFTOEN = 0: EMIFTOEN = 1: A time-out error is not generated when an EMIF access stalls for more than 512 CPU clock cycles. A time-out error is generated when an EMIF access stalls for more than 512 CPU clock cycles. DESCRIPTION

PERITOEN

R/W

Peripheral module time-out control bit PERITOEN = 0: PERITOEN = 1: A time-out error is not generated when a CPU access to a disabled/idle peripheral module stalls for more than 512 CPU clock cycles. A time-out error is generated when a CPU access to a disabled/idle peripheral module stalls for more than 512 CPU clock cycles.

December 2002 Revised November 2008

SPRS206K

113

Functional Overview

3.14 CPU Memory-Mapped Registers

The 5501 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to 4Fh. Table 355 provides a list of the CPU memory-mapped registers (MMRs) available. The corresponding TMS320C54x (C54x) CPU registers are also indicated where applicable. Table 355. CPU Memory-Mapped Registers
C54X REGISTER IER IFR ST0 ST1 AL AH AG BL BH BG TREG TRN AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK BRC RSA REA PMST XPC C55X REGISTER IER0 IFR0 ST0_55 ST1_55 ST3_55 ST0 ST1 AC0L AC0H AC0G AC1L AC1H AC1G T3 TRN0 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK03 BRC0 RSA0L REA0L PMST XPC T0 T1 T2 T3 AC2L AC2H AC2G WORD ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Temporary Register 3 Transition Register 0 Auxiliary Register 0 Auxiliary Register 1 Auxiliary Register 2 Auxiliary Register 3 Auxiliary Register 4 Auxiliary Register 5 Auxiliary Register 6 Auxiliary Register 7 Data Stack Pointer Circular Buffer Size Register for AR[03] Block Repeat Counter 0 Low Part of Block Repeat Start Address Register 0 Low Part of Block Repeat End Address Register 0 Status Register 3 (protected address for C54x code) Program Counter Extension Register for C54x code Reserved Temporary Register 0 Temporary Register 1 Temporary Register 2 Temporary Register 3 Accumulator 2 Accumulator 1 Accumulator 0 C55X REGISTER DESCRIPTION Interrupt Enable Register 0 Interrupt Flag Register 0 Status Register 0 Status Register 1 Status Register 3 Reserved Status Register 0 (protected address for C54x code) Status Register 1 (protected address for C54x code) BIT FIELD [150] [150] [150] [150] [150] [150] [150] [150] [150] [3116] [3932] [150] [3116] [3932] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [70] [150] [150] [150] [150] [150] [150] [3116] [3932]

TMS320C54x and C54x are trademarks of Texas Instruments. 114

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 355. CPU Memory-Mapped Registers (Continued)

C54X REGISTER C55X REGISTER CDP AC3L AC3H AC3G DPH DP PDP BK47 BKC BSA01 BSA23 BSA45 BSA67 BSAC BIOS TRN1 BRC1 BRS1 CSR RSA0H RSA0L REA0H REA0L RSA1H RSA1L REA1H REA1L RPTC IER1 IFR1 DBIER0 DBIER1 IVPD IVPH ST2_55 SSP SP SPH CDPH WORD ADDRESS (HEX) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Single Repeat Counter Interrupt Enable Register 1 Interrupt Flag Register 1 Debug Interrupt Enable Register 0 Debug Interrupt Enable Register 0 Interrupt Vector Pointer Interrupt Vector Pointer Status Register 2 System Stack Pointer Data Stack Pointer High Part of the Extended Stack Pointers (XSP = SPH:SP, XSSP = SPH:SSP) High Part of the Extended Coefficient Data Pointer (XCDP = CDPH:CDP) Block Repeat End Address Register 1 Block Repeat Start Address Register 1 Block Repeat End Address Register 0 High Part of the Extended Data Page Register (XDP = DPH:DP) Reserved Reserved Data Page Register Peripheral Data Page Register Circular Buffer Size Register for AR[47] Circular Buffer Size Register for CDP Circular Buffer Start Address Register for AR[01] Circular Buffer Start Address Register for AR[23] Circular Buffer Start Address Register for AR[45] Circular Buffer Start Address Register for AR[67] Circular Buffer Start Address Register for CDP Data Page Pointer Storage Location for 128-word Data Table Transition Register 1 Block Repeat Counter 1 BRC1 Save Register Computed Single Repeat Register Block Repeat Start Address Register 0 C55X REGISTER DESCRIPTION Coefficient Data Pointer Accumulator 3 BIT FIELD [150] [150] [3116] [3932] [60] [60] [60] [150] [80] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [2316] [150] [2316] [150] [2316] [150] [2316] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [150] [60] [60]

December 2002 Revised November 2008

SPRS206K

115

Functional Overview

3.15 Peripheral Registers

Each 5501 device has a set of peripheral memory-mapped registers as listed in Table 356 through Table 374. Peripheral registers are accessed using the port qualifier. For more information on the use of the port qualifier, see the TMS320C55x Assembly Language Tools Users Guide (literature number SPRU280). Some registers use less than 16 bits. When reading these registers, unused bits are always read as 0. The user guides for each peripheral contain detailed information on the operation and the functions of each of the peripheral registers (see Section 4.2, Documentation Support, for a list of documents supporting each peripheral). Table 356. Peripheral Bus Controller Configuration Registers
WORD ADDRESS 0x0000 0x0001 0x0002 0x0003 to 0x000D 0x000E 0x000F 0x0010 0x0011 0x0100 0x0102 0x0200 0x0202 0x0302 0x07FD ICR ISTR Reserved Reserved BOOT_MOD Reserved Reserved XCR XERR DCR DERR IERR CONFIG XPORT Configuration Register XPORT Bus Error Register DPORT Configuration Register DPORT Bus Error Register IPORT Bus Error Register System Configuration Register Time-Out Control Register 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0010 0000 0000 0000 0000 0000 0001 Boot Mode Register (read only) Value of GPIO[2:0] at reset REGISTER NAME Reserved Idle Configuration Register Idle Status Register 0000 0000 0000 0000 0000 0000 0000 0000 DESCRIPTION RESET VALUE

0x9000 TOCR x denotes a dont care.

116

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 357. External Memory Interface Registers

WORD ADDRESS 0x0800 0x0801 0x0802 0x0803 0x0804 0x0805 0x0806 0x0807 0x0808 0x0809 0x080A 0x080B 0x080C 0x080D 0x080E 0x080F 0x0810 0x0811 0x0812 to 0x0821 0x0822 0x0823 0x0824 0x0825 0x0826 0x0827 0x0828 0x0829 0x082A 0x082B 0x082C to 0x0839 0x0840 REGISTER NAME EGCR1 EGCR2 CE1_1 CE1_2 CE0_1 CE0_2 CE2_1 CE2_2 CE3_1 CE3_2 SDC1 SDC2 SDRC1 SDRC2 SDX1 SDX2 CE1_SC1 CE1_SC2 CE0_SC1 CE0_SC2 CE2_SC1 CE2_SC2 CE3_SC1 CE3_SC2 CESCR1 DESCRIPTION EMIF Global Control Register 1 EMIF Global Control Register 2 EMIF CE1 Space Control Register 1 EMIF CE1 Space Control Register 2 EMIF CE0 Space Control Register 1 EMIF CE0 Space Control Register 2 Reserved Reserved EMIF CE2 Space Control Register 1 EMIF CE2 Space Control Register 2 EMIF CE3 Space Control Register 1 EMIF CE3 Space Control Register 2 EMIF SDRAM Control Register 1 EMIF SDRAM Control Register 2 EMIF SDRAM Refresh Control Register 1 EMIF SDRAM Refresh Control Register 2 EMIF SDRAM Extension Register 1 EMIF SDRAM Extension Register 2 Reserved EMIF CE1 Secondary Control Register 1 EMIF CE1 Secondary Control Register 2 EMIF CE0 Secondary Control Register 1 EMIF CE0 Secondary Control Register 2 Reserved Reserved EMIF CE2 Secondary Control Register 1 EMIF CE2 Secondary Control Register 2 EMIF CE3 Secondary Control Register 1 EMIF CE3 Secondary Control Register 2 Reserved EMIF CE Size Control Register 1 EMIF CE Size Control Register 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 1111 1111 1111 0011 1111 1111 1111 1111 1111 1111 1111 0011 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 0100 1000 1100 0101 1101 1100 0000 0000 0101 1101 0101 1111 1101 1111 0000 0000 0001 0111 RESET VALUE 0010 0111 0111 1100 0000 0000 0000 1001 1111 1111 0001 1111 1111 1111 1111 1111 1111 1111 0000 0011 1111 1111 1111 1111

0x0841 CESCR2 x denotes a dont care.

December 2002 Revised November 2008

SPRS206K

117

Functional Overview

Table 358. DMA Configuration Registers

WORD ADDRESS REGISTER NAME DESCRIPTION GLOBAL REGISTER 0x0E00 0x0E01 DMA_GCR(2:0) DMA_GTCR(3:0) DMA Global Control Register DMA Global Timeout Control Register CHANNEL #0 REGISTERS 0x0C00 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 0x0C06 0x0C07 0x0C08 0x0C09 0x0C0A 0x0C0B 0x0C0C 0x0C0D 0x0C0E 0x0C0F DMA_CSDP0 DMA_CCR0(15:0) DMA_CICR0(5:0) DMA_CSR0(6:0) DMA_CSSA_L0 DMA_CSSA_U0 DMA_CDSA_L0 DMA_CDSA_U0 DMA_CEN0 DMA_CFN0 DMA_CSFI0 DMA_CSEI0 DMA_CSAC0 DMA_CDAC0 DMA_CDEI0 DMA_CDFI0 DMA Channel 0 Source Destination Parameters Register DMA Channel 0 Control Register DMA Channel 0 Interrupt Control register DMA Channel 0 Status register DMA Channel 0 Source Start Address, lower bits, register DMA Channel 0 Source Start Address, upper bits, register DMA Channel 0 Source Destination Address, lower bits, register DMA Channel 0 Source Destination Address, upper bits, register DMA Channel 0 Element Number register DMA Channel 0 Frame Number register DMA Channel 0 Source Frame Index register DMA Channel 0 Source Element Index register DMA Channel 0 Source Address Counter register DMA Channel 0 Destination Address Counter register DMA Channel 0 Destination Element Index register DMA Channel 0 Destination Frame Index register CHANNEL #1 REGISTERS 0x0C20 0x0C21 0x0C22 0x0C23 0x0C24 0x0C25 0x0C26 0x0C27 0x0C28 0x0C29 0x0C2A 0x0C2B 0x0C2C 0x0C2D 0x0C2E 0x0C2F DMA_CSDP1 DMA_CCR1(15:0) DMA_CICR1(5:0) DMA_CSR1(6:0) DMA_CSSA_L1 DMA_CSSA_U1 DMA_CDSA_L1 DMA_CDSA_U1 DMA_CEN1 DMA_CFN1 DMA_CSFI1 DMA_CSEI1 DMA_CSAC1 DMA_CDAC1 DMA_CDEI1 DMA_CDFI1 DMA Channel 1 Source Destination Parameters Register DMA Channel 1 Control Register DMA Channel 1 Interrupt Control register DMA Channel 1 Status register DMA Channel 1 Source Start Address, lower bits, register DMA Channel 1 Source Start Address, upper bits, register DMA Channel 1 Source Destination Address, lower bits, register DMA Channel 1 Source Destination Address, upper bits, register DMA Channel 1 Element Number register DMA Channel 1 Frame Number register DMA Channel 1 Source Frame Index register DMA Channel 1 Source Element Index register DMA Channel 1 Source Address Counter register DMA Channel 1 Destination Address Counter register DMA Channel 1 Destination Element Index register DMA Channel 1 Destination Frame Index register 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1000 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1000 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000 0000 RESET VALUE

118

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 358. DMA Configuration Registers (Continued)

WORD ADDRESS 0x0C40 0x0C41 0x0C42 0x0C43 0x0C44 0x0C45 0x0C46 0x0C47 0x0C48 0x0C49 0x0C4A 0x0C4B 0x0C4C 0x0C4D 0x0C4E 0x0C4F 0x0C60 0x0C61 0x0C62 0x0C63 0x0C64 0x0C65 0x0C66 0x0C67 0x0C68 0x0C69 0x0C6A 0x0C6B 0x0C6C 0x0C6D 0x0C6E 0x0C6F REGISTER NAME DMA_CSDP2 DMA_CCR2(15:0) DMA_CICR2(5:0) DMA_CSR2(6:0) DMA_CSSA_L2 DMA_CSSA_U2 DMA_CDSA_L2 DMA_CDSA_U2 DMA_CEN2 DMA_CFN2 DMA_CSFI2 DMA_CSEI2 DMA_CSAC2 DMA_CDAC2 DMA_CDEI2 DMA_CDFI2 DMA_CSDP3 DMA_CCR3(15:0) DMA_CICR3(5:0) DMA_CSR3(6:0) DMA_CSSA_L3 DMA_CSSA_U3 DMA_CDSA_L3 DMA_CDSA_U3 DMA_CEN3 DMA_CFN3 DMA_CSFI3 DMA_CSEI3 DMA_CSAC3 DMA_CDAC3 DMA_CDEI3 DMA_CDFI3 DESCRIPTION CHANNEL #2 REGISTERS DMA Channel 2 Source Destination Parameters Register DMA Channel 2 Control Register DMA Channel 2 Interrupt Control register DMA Channel 2 Status register DMA Channel 2 Source Start Address, lower bits, register DMA Channel 2 Source Start Address, upper bits, register DMA Channel 2 Source Destination Address, lower bits, register DMA Channel 2 Source Destination Address, upper bits, register DMA Channel 2 Element Number register DMA Channel 2 Frame Number register DMA Channel 2 Source Frame Index register DMA Channel 2 Source Element Index register DMA Channel 2 Source Address Counter register DMA Channel 2 Destination Address Counter register DMA Channel 2 Destination Element Index register DMA Channel 2 Destination Frame Index register CHANNEL #3 REGISTERS DMA Channel 3 Source Destination Parameters Register DMA Channel 3 Control Register DMA Channel 3 Interrupt Control register DMA Channel 3 Status register DMA Channel 3 Source Start Address, lower bits, register DMA Channel 3 Source Start Address, upper bits, register DMA Channel 3 Source Destination Address, lower bits, register DMA Channel 3 Source Destination Address, upper bits, register DMA Channel 3 Element Number register DMA Channel 3 Frame Number register DMA Channel 3 Source Frame Index register DMA Channel 3 Source Element Index register DMA Channel 3 Source Address Counter register DMA Channel 3 Destination Address Counter register DMA Channel 3 Destination Element Index register DMA Channel 3 Destination Frame Index register 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1000 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1000 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RESET VALUE

December 2002 Revised November 2008

SPRS206K

119

Functional Overview

Table 358. DMA Configuration Registers (Continued)

WORD ADDRESS REGISTER NAME DESCRIPTION CHANNEL #4 REGISTERS 0x0C80 0x0C81 0x0C82 0x0C83 0x0C84 0x0C85 0x0C86 0x0C87 0x0C88 0x0C89 0x0C8A 0x0C8B 0x0C8C 0x0C8D 0x0C8E 0x0C8F DMA_CSDP4 DMA_CCR4(15:0) DMA_CICR4(5:0) DMA_CSR4(6:0) DMA_CSSA_L4 DMA_CSSA_U4 DMA_CDSA_L4 DMA_CDSA_U4 DMA_CEN4 DMA_CFN4 DMA_CSFI4 DMA_CSEI4 DMA_CSAC4 DMA_CDAC4 DMA_CDEI4 DMA_CDFI4 DMA Channel 4 Source Destination Parameters Register DMA Channel 4 Control Register DMA Channel 4 Interrupt Control register DMA Channel 4 Status register DMA Channel 4 Source Start Address, lower bits, register DMA Channel 4 Source Start Address, upper bits, register DMA Channel 4 Source Destination Address, lower bits, register DMA Channel 4 Source Destination Address, upper bits, register DMA Channel 4 Element Number register DMA Channel 4 Frame Number register DMA Channel 4 Source Frame Index register DMA Channel 4 Source Element Index register DMA Channel 4 Source Address Counter register DMA Channel 4 destination Address Counter register DMA Channel 4 Destination Element Index register DMA Channel 4 Destination Frame Index register CHANNEL #5 REGISTERS 0x0CA0 0x0CA1 0x0CA2 0x0CA3 0x0CA4 0x0CA5 0x0CA6 0x0CA7 0x0CA8 0x0CA9 0x0CAA 0x0CAB 0x0CAC 0x0CAD 0x0CAE 0x0CAF DMA_CSDP5 DMA_CCR5(15:0) DMA_CICR5(5:0) DMA_CSR5(6:0) DMA_CSSA_L5 DMA_CSSA_U5 DMA_CDSA_L5 DMA_CDSA_U5 DMA_CEN5 DMA_CFN5 DMA_CSFI5 DMA_CSEI5 DMA_CSAC5 DMA_CDAC5 DMA_CDEI5 DMA_CDFI5 DMA Channel 5 Source Destination Parameters Register DMA Channel 5 Control Register DMA Channel 5 Interrupt Control register DMA Channel 5 Status register DMA Channel 5 Source Start Address, lower bits, register DMA Channel 5 Source Start Address, upper bits, register DMA Channel 5 Source Destination Address, lower bits, register DMA Channel 5 Source Destination Address, upper bits, register DMA Channel 5 Element Number register DMA Channel 5 Frame Number register DMA Channel 5 Source Frame Index register DMA Channel 5 Source Element Index register DMA Channel 5 Source Address Counter register DMA Channel 5 Destination Address Counter register DMA Channel 5 Destination Element Index register DMA Channel 5 Destination Frame Index register 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1000 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1000 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RESET VALUE

120

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 359. Instruction Cache Registers

WORD ADDRESS 0x1400 0x1401 0x1402 0x1409 ICGC ICFLARL ICFLARH ICWMC REGISTER NAME DESCRIPTION ICache Global Control Register ICache Flush Line Address Register Low Part ICache Flush Line Address Register High Part ICache Way Miss-Counter Register

Table 360. Trace FIFO

WORD ADDRESS 0x2000 0x203F 0x2040 0x204F 0x2050 0x2051 0x2052 0x2053 REGISTER NAME TRC00 TRC63 TRC64 TRC79 TRC_LPCOFFSET1 TRC_LPCOFFSET2 TRC_PTR TRC_CNTL DESCRIPTION Trace Register Discontinuity Section Trace Register Last PC Section Trace LPC Offset Register 1 Trace LPC Offset Register 2 Trace Pointer Register Trace Control Register

0x2054 TRC_ID Trace ID Register The Trace FIFO registers are used by the emulator only and do not require any intervention from the user.

Table 361. Timer Signal Selection Register

WORD ADDRESS 0x8000 REGISTER NAME TSSR DESCRIPTION Timer Signal Selection Register RESET VALUE 0000 0000 0000 0000

Table 362. Timers

WORD ADDRESS 0x1000 0x1001 0x1002 0x1003 0x1004 0x1005 0x1006 0x1007 0x1008 0x1009 0x100A 0x100B 0x100C 0x100D 0x100E 0x100F 0x1010 0x1011 0x1012 0x1013 0x2400 0x2401 0x2402 0x2403 0x2404 GPTPID1_1 GPTPID2_1 GPTEMU_1 GPTCLK_1 GPTGPINT_1 REGISTER NAME GPTPID1_0 GPTPID2_0 GPTEMU_0 GPTCLK_0 GPTGPINT_0 GPTGPEN_0 GPTGPDAT_0 GPTGPDIR_0 GPTCNT1_0 GPTCNT2_0 GPTCNT3_0 GPTCNT4_0 GPTPRD1_0 GPTPRD2_0 GPTPRD3_0 GPTPRD4_0 GPTCTL1_0 GPTCTL2_0 GPTGCTL1_0 DESCRIPTION Peripheral ID register 1, Timer #0 Peripheral ID register 2, Timer #0 Emulation Management Register, Timer #0 Timer Clock Speed Register, Timer #0 GPIO Interrupt Control Register, Timer #0 GPIO Enable Register, Timer #0 GPIO Data Register, Timer #0 GPIO Direction Register, Timer #0 Timer Counter 1 Register, Timer #0 Timer Counter 2 Register, Timer #0 Timer Counter 3 Register, Timer #0 Timer Counter 4 Register, Timer #0 Period Register 1, Timer #0 Period Register 2, Timer #0 Period Register 3, Timer #0 Period Register 4, Timer #0 Timer Control Register 1, Timer #0 Timer Control Register 2, Timer #0 Global Timer Control Register 1, Timer #0 Reserved Peripheral ID register 1, Timer #1 Peripheral ID register 2, Timer #1 Emulation Management Register, Timer #1 Timer Clock Speed Register, Timer #1 GPIO Interrupt Control Register, Timer #1 0000 0111 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0111 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

December 2002 Revised November 2008

SPRS206K

121

Functional Overview

Table 362. Timers (Continued)

WORD ADDRESS 0x2405 0x2406 0x2407 0x2408 0x2409 0x240A 0x240B 0x240C 0x240D 0x240E 0x240F 0x2410 0x2411 0x2412 0x2413 0x4000 0x4001 0x4002 0x4003 0x4004 0x4005 0x4006 0x4007 0x4008 0x4009 0x400A 0x400B 0x400C 0x400D 0x400E 0x400F 0x4010 0x4011 0x4012 0x4013 0x4014 0x4015 WDTWCTL1 WDTWCTL2 WDTPID1 WDTPID2 WDTEMU WDTCLK WDTGPINT WDTGPEN WDTGPDAT WDTGPDIR WDTCNT1 WDTCNT2 WDTCNT3 WDTCNT4 WDTPRD1 WDTPRD2 WDTPRD3 WDTPRD4 WDTCTL1 WDTCTL2 WDTGCTL1 REGISTER NAME GPTGPEN_1 GPTGPDAT_1 GPTGPDIR_1 GPTCNT1_1 GPTCNT2_1 GPTCNT3_1 GPTCNT4_1 GPTPRD1_1 GPTPRD2_1 GPTPRD3_1 GPTPRD4_1 GPTCTL1_1 GPTCTL2_1 GPTGCTL1_1 DESCRIPTION GPIO Enable Register, Timer #1 GPIO Data Register, Timer #1 GPIO Direction Register, Timer #1 Timer Counter 1 Register, Timer #1 Timer Counter 2 Register, Timer #1 Timer Counter 3 Register, Timer #1 Timer Counter 4 Register, Timer #1 Period Register 1, Timer #1 Period Register 2, Timer #1 Period Register 3, Timer #1 Period Register 4, Timer #1 Timer Control Register 1, Timer #1 Timer Control Register 2, Timer #1 Global Timer Control Register 1, Timer #1 Reserved Peripheral ID register 1, Watchdog Timer Peripheral ID register 2, Watchdog Timer Emulation Management Register, Watchdog Timer Timer Clock Speed Register, Watchdog Timer GPIO Interrupt Control Register, Watchdog Timer GPIO Enable Register, Watchdog Timer GPIO Data Register, Watchdog Timer GPIO Direction Register, Watchdog Timer Timer Counter 1 Register, Watchdog Timer Timer Counter 2 Register, Watchdog Timer Timer Counter 3 Register, Watchdog Timer Timer Counter 4 Register, Watchdog Timer Period Register 1, Watchdog Timer Period Register 2, Watchdog Timer Period Register 3, Watchdog Timer Period Register 4, Watchdog Timer Timer Control Register 1, Watchdog Timer Timer Control Register 2, Watchdog Timer Global Timer Control Register 1, Watchdog Timer Reserved WD Timer Control Register 1, Watchdog Timer WD Timer Control Register 2, Watchdog Timer 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

122

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 363. Multichannel Serial Port #0

WORD ADDRESS 0x2800 0x2801 0x2802 0x2803 0x2804 0x2805 0x2806 0x2807 0x2808 0x2809 0x280A 0x280B 0x280C 0x280D 0x280E 0x280F 0x2810 0x2811 0x2812 0x2813 0x2814 0x2815 0x2816 0x2817 0x2818 0x2819 0x281A 0x281B 0x281C 0x281D 0x281E 0x281F RCERC_0 RCERD_0 XCERC_0 XCERD_0 RCERE_0 RCERF_0 XCERE_0 XCERF_0 RCERG_0 RCERH_0 XCERG_0 XCERH_0 REGISTER NAME DRR1_0 DRR2_0 DXR1_0 DXR2_0 SPCR1_0 SPCR2_0 RCR1_0 RCR2_0 XCR1_0 XCR2_0 SRGR1_0 SRGR2_0 MCR1_0 MCR2_0 RCERA_0 RCERB_0 XCERA_0 XCERB_0 PCR0 DESCRIPTION Data Receive Register 1, McBSP #0 Data Receive Register 2, McBSP #0 Data Transmit Register 1, McBSP #0 Data Transmit Register 2, McBSP #0 Serial Port Control Register 1, McBSP #0 Serial Port Control Register 2, McBSP #0 Receive Control Register 1, McBSP #0 Receive Control Register 2, McBSP #0 Transmit Control Register 1, McBSP #0 Transmit Control Register 2, McBSP #0 Sample Rate Generator Register 1, McBSP #0 Sample Rate Generator Register 2, McBSP #0 Multichannel Control Register 1, McBSP #0 Multichannel Control Register 2, McBSP #0 Receive Channel Enable Register Partition A, McBSP #0 Receive Channel Enable Register Partition B, McBSP #0 Transmit Channel Enable Register Partition A, McBSP #0 Transmit Channel Enable Register Partition B, McBSP #0 Pin Control Register, McBSP #0 Reserved Receive Channel Enable Register Partition C, McBSP #0 Receive Channel Enable Register Partition D, McBSP #0 Transmit Channel Enable Register Partition C, McBSP #0 Transmit Channel Enable Register Partition D, McBSP #0 Receive Channel Enable Register Partition E, McBSP #0 Receive Channel Enable Register Partition F, McBSP #0 Transmit Channel Enable Register Partition E, McBSP #0 Transmit Channel Enable Register Partition F, McBSP #0 Receive Channel Enable Register Partition G, McBSP #0 Receive Channel Enable Register Partition H, McBSP #0 Transmit Channel Enable Register Partition G, McBSP #0 Transmit Channel Enable Register Partition H, McBSP #0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

December 2002 Revised November 2008

SPRS206K

123

Functional Overview

Table 364. Multichannel Serial Port #1

WORD ADDRESS 0x2C00 0x2C01 0x2C02 0x2C03 0x2C04 0x2C05 0x2C06 0x2C07 0x2C08 0x2C09 0x2C0A 0x2C0B 0x2C0C 0x2C0D 0x2C0E 0x2C0F 0x2C10 0x2C11 0x2C12 0x2C13 0x2C14 0x2C15 0x2C16 0x2C17 0x2C18 0x2C19 0x2C1A 0x2C1B 0x2C1C 0x2C1D 0x2C1E 0x2C1F RCERC_1 RCERD_1 XCERC_1 XCERD_1 RCERE_1 RCERF_1 XCERE_1 XCERF_1 RCERG_1 RCERH_1 XCERG_1 XCERH_1 REGISTER NAME DRR1_1 DRR2_1 DXR1_1 DXR2_1 SPCR1_1 SPCR2_1 RCR1_1 RCR2_1 XCR1_1 XCR2_1 SRGR1_1 SRGR2_1 MCR1_1 MCR2_1 RCERA_1 RCERB_1 XCERA_1 XCERB_1 PCR1 DESCRIPTION Data Receive Register 1, McBSP #1 Data Receive Register 2, McBSP #1 Data Transmit Register 1, McBSP #1 Data Transmit Register 2, McBSP #1 Serial Port Control Register 1, McBSP #1 Serial Port Control Register 2, McBSP #1 Receive Control Register 1, McBSP #1 Receive Control Register 2, McBSP #1 Transmit Control Register 1, McBSP #1 Transmit Control Register 2, McBSP #1 Sample Rate Generator Register 1, McBSP #1 Sample Rate Generator Register 2, McBSP #1 Multichannel Control Register 1, McBSP #1 Multichannel Control Register 2, McBSP #1 Receive Channel Enable Register Partition A, McBSP #1 Receive Channel Enable Register Partition B, McBSP #1 Transmit Channel Enable Register Partition A, McBSP #1 Transmit Channel Enable Register Partition B, McBSP #1 Pin Control Register, McBSP #1 Reserved Receive Channel Enable Register Partition C, McBSP #1 Receive Channel Enable Register Partition D, McBSP #1 Transmit Channel Enable Register Partition C, McBSP #1 Transmit Channel Enable Register Partition D, McBSP #1 Receive Channel Enable Register Partition E, McBSP #1 Receive Channel Enable Register Partition F, McBSP #1 Transmit Channel Enable Register Partition E, McBSP #1 Transmit Channel Enable Register Partition F, McBSP #1 Receive Channel Enable Register Partition G, McBSP #1 Receive Channel Enable Register Partition H, McBSP #1 Transmit Channel Enable Register Partition G, McBSP #1 Transmit Channel Enable Register Partition H, McBSP #1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

124

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 365. HPI

WORD ADDRESS 0xA000 0xA001 0xA002 0xA003 0xA004 0xA005 0xA006 0xA007 0xA008 0xA009 0xA00A 0xA00B 0xA00C 0xA00D 0xA00E 0xA00F 0xA017 0xA018 0xA019 0xA01A 0xA01B 0xA01C 0xA01D 0xA020 x denotes a dont care. HPIAR HPIAW HPIC HGPIODAT2 HGPIODIR2 HGPIODAT1 HGPIODIR1 HGPIOINT1 HGPIOINT2 HGPIOEN REGISTER NAME PID LSW PID MSW HPWREMU PID [15:0] PID [31:16] Power and Emulation Management Register Reserved General-Purpose I/O Interrupt Control Register 1 General-Purpose I/O Interrupt Control Register 2 General-Purpose I/O Enable Register Reserved General-Purpose I/O Direction Register 1 Reserved General-Purpose I/O Data Register 1 Reserved General-Purpose I/O Direction Register 2 Reserved General-Purpose I/O Data Register 2 Reserved Host Port Control Register Reserved Host Port Write Address Register Reserved Host Port Read Address Register Reserved xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 1000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DESCRIPTION 0000 0000 0000 0000 RESET VALUE

Table 366. GPIO

WORD ADDRESS 0x3400 0x3401 0x4400 0x4401 0x4402 0x4403 0x4404 0x4405 0x4406 0x4407 0x4408 REGISTER NAME IODIR IODATA PGPIOEN0 PGPIODIR0 PGPIODAT0 PGPIOEN1 PGPIODIR1 PGPIODAT1 PGPIOEN2 PGPIODIR2 PGPIODAT2 DESCRIPTION General-purpose I/O Direction Register General-purpose I/O Data Register Parallel GPIO Enable Register 0 Parallel GPIO Direction Register 0 Parallel GPIO Data Register 0 Parallel GPIO Enable Register 1 Parallel GPIO Direction Register 1 Parallel GPIO Data Register 1 Parallel GPIO Enable Register 2 Parallel GPIO Direction Register 2 Parallel GPIO Data Register 2 RESET VALUE 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

x denotes a dont care.

December 2002 Revised November 2008

SPRS206K

125

Functional Overview

Table 367. Device Revision ID

WORD ADDRESS 0x3800 0x3803 0x3804 0x3805 0x3806 REGISTER NAME Die ID Chip ID (LSW) Chip ID (MSW) Sub ID Die ID Defines F# 3LS digits and PG rev Defines F# 3MS digits Defines subsytem ID 1001 0100 0110 xxxx 0000 0111 0101 0001 0000 0000 0000 0000 DESCRIPTION RESET VALUE

x denotes a dont care. Denotes single core

Table 368. I2C

WORD ADDRESS 0x3C00 0x3C01 0x3C02 0x3C03 0x3C04 0x3C05 0x3C06 0x3C07 0x3C08 0x3C09 0x3C0A 0x3C0B 0x3C0C 0x3C0D 0x3C0E REGISTER NAME I2COAR I2CIER I2CSTR I2CCLKL I2CCLKH I2CCNT I2CDRR I2CSAR I2CDXR I2CMDR I2CISRC I2CGPIO I2CPSC PID1 PID2 I2CXSR DESCRIPTION I2C Own Address Register I2C Interrupt Enable Register I2C Status Register I2C Clock Low-Time Divider Register I2C Clock High-Time Divider Register I2C Data Count I2C Data Receive Register I2C Slave Address Register I2C Data Transmit Register I2C Mode Register I2C Interrupt Source Register I2C General-Purpose Register (Not supported) I2C Prescaler Register I2C Peripheral ID Register 1 I2C Peripheral ID Register 2 I2C Transmit Shift Register I2C Receive Shift Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000

I2CRSR x denotes a dont care. Specifies a unique 5501 I2C address. This register is fully programmable in both 7-bit and 10-bit modes and must be set by the programmer. When this device is used in conjunction with another I2C device, it must be programmed to the I2C slave address (01011A2A1A0) allocated by Philips Semiconductor for the 5501 (allocation number: 1946). A2, A1, and A0 are programmable address bits.

126

SPRS206K

December 2002 Revised November 2008

Functional Overview

Table 369. UART

WORD ADDRESS 0x9C00 REGISTER NAME URRBR/ URTHR/ URDLL URIER/ URDLM URIIR/ URFCR URLCR URMCR URLSR URSCR URDLL URDLM URPID1 URPID2 URPECR DESCRIPTION Receive Buffer Register Transmit Holding Register Divisor Latch LSB Register Interrupt Enable Register Divisor Latch MSB Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Scratch Register Divisor Latch LSB Register Divisor Latch MSB Register Peripheral ID Register (LSW) Peripheral ID Register (MSW) Power and Emulation Control Register RESET VALUE xxxx xxxx

0x9C01 0x9C02 0x9C03 0x9C04 0x9C05 0x9C07 0x9C08 0x9C09 0x9C0A 0x9C0B 0x9C0C

0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0110 0000 xxxx xxxx 0000 0000 0000 0000

x denotes a dont care. The registers URRBR, URTHR, and URDLL share one address. URDLL also has a dedicated address. When using the dedicated address, the DLAB bit can be kept cleared, so that URRBR and URTHR are always selected at the shared address. If DLAB = 0 : Read Only: URRBR Write Only: URTHR If DLAB = 1: Read/Write: URDLL The registers URIER and URDLM share one address. URDLM also has a dedicated address. When using the dedicated address, the DLAB bit can be kept cleared, so that URIER is always selected at the shared address. If DLAB = 0: Read/WRite: URIER If DLAB = 1: Read/Write: URDLM The registers URIIR and URFCR share one address. Read Only: URIIR Write Only: URFCR

Table 370. External Bus Selection

WORD ADDRESS 0x6C00 0x8800 REGISTER NAME XBSR XBCR DESCRIPTION External Bus Selection Register External Bus Control Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000

Table 371. Clock Mode Register

WORD ADDRESS 0x8C00 REGISTER NAME CLKMD DESCRIPTION Clock Mode Control Register RESET VALUE 0000 0000 0000 0000

Table 372. CLKOUT Selector Register

WORD ADDRESS 0x8400 REGISTER NAME CLKOUTSR DESCRIPTION CLKOUT Selection Register RESET VALUE 0000 0000 0000 0010

December 2002 Revised November 2008

SPRS206K

127

Functional Overview

Table 373. Clock Controller Registers

WORD ADDRESS 0x1C80 0x1C82 0x1C88 0x1C8A 0x1C8C 0x1C8E 0x1C90 0x1C92 0x1C98 REGISTER NAME PLLCSR CK3SEL PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 WKEN DESCRIPTION PLL Control Status Register CLKOUT3 Select Register PLL Multiplier Control Register PLL Divider 0 Register PLL Divider 1 Register PLL Divider 2 Register PLL Divider 3 Register Oscillator Divider 1 Register Oscillator Wakeup Control Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 1011 0000 0000 0000 0000 1000 0000 0000 0000 1000 0000 0000 0011 1000 0000 0000 0011 1000 0000 0000 0011 0000 0000 0000 0000 0000 0000 0000 0000

Table 374. IDLE Control Registers

WORD ADDRESS 0x9400 0x9401 0x9402 0x9403 REGISTER NAME PICR PISTR MICR MISR DESCRIPTION Peripheral IDLE Control Register Peripheral IDLE Status Register Master IDLE Control Register Master IDLE Status Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

128

SPRS206K

December 2002 Revised November 2008

Functional Overview

3.16 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 375. For more information on setting up and using interrupts, please refer to the TMS320C55x DSP CPU Reference Guide (literature number SPRU371). Table 375. Interrupt Table
NAME RESET NMI INT0 INT2 TINT0 RINT0 RINT1 XINT1 LCKINT DMAC1 DSPINT INT3/WDTINT UART DMAC4 DMAC5 INT1 XINT0 DMAC0 DMAC2 DMAC3 TINT1 IIC BERR DLOG RTOS SOFTWARE (TRAP) EQUIVALENT SINT0 SINT1 SINT2 SINT3 SINT4 SINT5 SINT6 SINT7 SINT8 SINT9 SINT10 SINT11 SINT12 SINT13 SINT14 SINT15 SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 LOCATION (HEX BYTES) 0 8 10 18 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 PRIORITY 0 1 3 5 6 7 9 10 11 13 14 15 17 18 21 22 4 8 12 16 19 20 23 24 2 25 26 27 28 29 30 FUNCTION Reset (hardware and software) Nonmaskable interrupt External interrupt #0 External interrupt #2 Timer #0 interrupt McBSP #0 receive interrupt McBSP #1 receive interrupt McBSP #1 transmit interrupt PLL lock interrupt DMA Channel #1 interrupt Interrupt from host External interrupt #3 or Watchdog timer interrupt UART interrupt Software interrupt #13 DMA Channel #4 interrupt DMA Channel #5 interrupt External interrupt #1 McBSP #0 transmit interrupt DMA Channel #0 interrupt Software interrupt #19 DMA Channel #2 interrupt DMA Channel #3 interrupt Timer #1 interrupt I2C interrupt Bus Error interrupt Data Log interrupt Real-time Operating System interrupt Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30

SINT31 F8 31 Software interrupt #31 WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.

December 2002 Revised November 2008

SPRS206K

129

Functional Overview

3.16.1

IFR and IER Registers

The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are currently pending. The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1) is used and DBIER0/1 are ignored. A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an interrupt enable register (IER0 or IER1). Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using the real-time emulation mode. A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears IFR0/1 to 0 but does not affect IER0/1 and DBIER0/1. The bit layouts of these registers for each interrupt are shown in Figure 351 and Figure 352. For more information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).
15 DMAC5 R/W, 0 14 DMAC4 R/W, 0 13 Reserved R/W, 0 12 UART R/W, 0 11 INT3/ WDTINT R/W, 0 10 DSPINT R/W, 0 9 DMAC1 R/W, 0 8 Reserved R/W, 0

7 XINT1 R/W, 0

6 RINT1 R/W, 0

5 RINT0 R/W, 0

4 TINT0 R/W, 0

3 INT2 R/W, 0

2 INT0 R/W, 0

1 Reserved R, 0

LEGEND: R = Read, W = Write, n = value at reset This bit must be kept zero when writing to IER0. WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.

Figure 351. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout

130

SPRS206K

December 2002 Revised November 2008

Functional Overview
15 Reserved R, 0 11 10 RTOS R/W, 0 9 DLOG R/W, 0 8 BERR R/W, 0

7 I2C R/W, 0

6 TINT1 R/W, 0

5 DMAC3 R/W, 0

4 DMAC2 R/W, 0

3 INT4 R/W, 0

2 DMAC0 R/W, 0

1 XINT0 R/W, 0

0 INT1 R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 352. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout

3.16.2

Interrupt Timing

The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer. The interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of 1000 on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration on the external interrupts on the 5501 is three CPU clock periods. TIM0, TIM1, WDTOUT, and HPI.HAS can be configured to generate interrupts to the CPU. When they are used for this function, these pins will generate the interrupt associated with that module, i.e., TIM0 will generate TINT0, HPI.HAS will generate DSPINT, etc. Three SYSCLK1 clock cycles must be allowed to pass between consecutive interrupts generated using the HPI.HAS signal; otherwise, the last interrupt will be ignored (i.e., a sequence of 01110 on consecutive cycles is required for consecutive interrupts). For more information on configuring TIM0, TIM1, WDTOUT, and HPI.HAS as interrupt pins, please refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for the timer pins and to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for the HPI pin.

3.16.3

Interrupt Acknowledge

The IACK pin is used to indicate the receipt of an interrupt and that the program counter is fetching the interrupt vector location designated on the address bus. As the CPU fetches the first word or the software vector, it generates the IACK signal, which clears the appropriate interrupt flag bit. The IACK signal will go low for a total of one CPU clock pulse and then go high again. For maskable interrupts, note that the CPU will not jump to an interrupt service routine if the appropriate interrupt enable bit is not set; consequently, the IACK pin will not go low when the interrupt is generated.

December 2002 Revised November 2008

SPRS206K

131

Functional Overview

3.17 Notice Concerning TCK

Under certain conditions, the emulation hardware may corrupt the emulation control state machine or may cause it to lose synchronization with the emulator software. When emulation commands fail as a result of the problem, Code Composer Studio Integrated Development Environment (IDE) may be unable to start or it may report errors when interacting with the TMS320C55x DSP (for example, when halting the CPU, reaching a breakpoint, etc.). This phenomenon is observed when an erroneous clock edge is generated from the TCK signal inside the C55x DSP. This can be caused by several factors, acting independently or cumulatively: TCK transition times (as measured between 2.4 V and 0.8 V) in excess of 3 ns. Operating the C55x DSP in a socket, which can aggravate noise or glitches on the TCK input. Poor signal integrity on the TCK line from reflections or other layout issues.

A TCK edge that can cause this problem might look similar to the one shown in Figure 353. A TCK edge that does not cause the problem looks similar to the one shown in Figure 354. The key difference between the two figures is that Figure 354 has a clean and sharp transition whereas Figure 353 has a knee in the transition zone. Problematic TCK signals may not have a knee that is as pronounced as the one in Figure 353. Due to the TCK signal amplification inside the chip, any perturbation of the signal can create erroneous clock edges. As a result of the faster edge transition, there is increased ringing in Figure 354. As long as the ringing does not cross logic input thresholds (0.8 V for falling edges, and 2.4 V for rising edges), this ringing is acceptable. When examining a TCK signal for this issue, either in board simulation or on an actual board, it is very important to probe the TCK line as close to the DSP input pin as possible. In simulation, it should not be difficult to probe right at the DSP input. For most physical boards, this means using the via for the TCK pad on the back side of the board. Similarly, ground for the probe should come from one of the nearby ground pad vias to minimize EMI noise picked up by the probe.

Code Composer Studio, TMS320C55x, and C55x are trademarks of Texas Instruments. 132

SPRS206K

December 2002 Revised November 2008

Functional Overview
4 3 2.5 V Volts (V) 2 1 0.6 V 0 1 0 15 5 10 nanoseconds (ns) 20

Figure 353. Bad TCK Transition

4 3 2.5 V Volts (V) 2 1 0.6 V 0 1 0 15 5 10 nanoseconds (ns) 20

Figure 354. Good TCK Transition As the problem may be caused by one or more of the above factors, one or more of the steps outlined below may be necessary to fix it: Avoid using a socket Ensure the board design achieves rise times and fall times of less than 3 ns with clean monotonic edges for the TCK signal. For designs where TCK is supplied by the emulation pod, implement noise filtering circuitry on the target board. A sample circuit is shown in Figure 355.

December 2002 Revised November 2008

SPRS206K

133

Functional Overview
3.3 V XDS TRST

TMS TDI TDO

XDS TMS XDS TDI XDS TDO XDS TCK RTN XDS TCK XDS EMU0

1 3 5 7 9 11 13

2 4 8 10 12 14

TRST

XDS EMU1

EMU1/OFF

EMU0 3.3 V 3.3 V

0.1 mF SN74LVC1G32

0.1 mF SN74LVC1G32

R32 33 W

TCK

Figure 355. Sample Noise Filtering Circuitry

134

SPRS206K

December 2002 Revised November 2008

Support

4
4.1

Support
Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability

4.1.1 Initialization Requirements for Boundary Scan Test

The TMS320VC5501 uses the JTAG port for boundary scan tests, emulation capability and factory test purposes. To use boundary scan test, the EMU0 and EMU1/OFF pins must be held HIGH through a rising edge of the TRST signal prior to the first scan. This operation selects the appropriate TAP control for boundary scan. If at any time during a boundary scan test a rising edge of TRST occurs when EMU0 or EMU1/OFF are not high, a factory test mode may be selected preventing boundary scan test from being completed. For this reason, it is recommended that EMU0 and EMU1/OFF be pulled or driven high at all times during boundary scan test.

4.1.2 Boundary Scan Description Language (BSDL) Model

BSDL models are available on the web in the TMS320VC5501 product folder under the simulation models section.

4.2

Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the TMS320C5000 platform of DSPs: Device-specific data sheets Complete users guides Development support tools Hardware and software application reports MicroStar BGAE Packaging Reference Guide (literature number SSYZ015)

TMS320C55x reference documentation that includes, but is not limited to, the following: TMS320C55x DSP CPU Reference Guide (literature number SPRU371) TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374) TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375) TMS320C55x DSP Programmers Guide (literature number SPRU376) TMS320C55x Assembly Language Tools Users Guide (literature number SPRU280) TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630) TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146) TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613) TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592) TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU621) TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide (literature number SPRU597) TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number SPRZ020D or later) TMS320VC5501/02 Power Consumption Summary Application Report (literature number SPRA993)

TMS320 and TMS320C5000 are trademarks of Texas Instruments. 135

December 2002 Revised November 2008

SPRS206K

Support

The reference guides describe in detail the TMS320C55x DSP products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

4.3

Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320VC5501). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX TMP TMS Experimental device that is not necessarily representative of the final devices electrical specifications Final silicon die that conforms to the devices electrical specifications but has not completed quality and reliability verification Fully qualified production device

Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: Developmental product is intended for internal evaluation purposes. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TIs standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

136

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320VC5501 DSP. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified.

5.1

Absolute Maximum Ratings

The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those listed under Section 5.2, Electrical Specifications, may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3, Recommended Operating Conditions, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltage values (core and I/O) are with respect to VSS. Figure 51 provides the test load circuit values for a 3.3-V device. Measured timing information contained in this data manual is based on the test load setup and conditions shown in Figure 51.

5.2

Electrical Specifications
This section provides the absolute maximum ratings for the TMS320VC5501 DSP. Supply voltage I/O range, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4.0 V Supply voltage core range, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 2.0 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4.5 V Output voltage range, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4.5 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55_C to 150_C

5.3

Recommended Operating Conditions

This section provides the recommended operating conditions for the TMS320VC5501 DSP.
MIN NOM 3.3 1.26 3.3 0 Hysteresis inputs DVDD = 3.0 3.6 V All other inputs DVDD = 3.0 3.6 V Hysteresis inputs DVDD = 3.0 3.6 V All other inputs DVDD = 3.0 3.6 V All outputs All outputs 40 2.2 2 0.3 0.3 DVDD + 0.3 V DVDD + 0.3 0.8 V 0.8 300 1.5 85 A mA C MAX 3.6 1.32 3.6 UNIT V V V V

DVDD CVDD PVDD VSS

Device supply voltage, I/O Device supply voltage, core Device supply voltage, PLL Supply voltage, GND

3.0 1.20 3.0

VIH

High-level input voltage, I/O

VIL

Low-level input voltage, I/O

IOH IOL TC

High-level output current Low-level output current Operating case temperature

December 2002 Revised November 2008

SPRS206K

137

Electrical Specifications

5.4

Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS DVDD = 3.3 0.3 V, IOH = MAX IOL = MAX Output-only or input/output pins with bus holders All other output-only or input/output pins Input pins with internal pulldown X2/CLKIN Bus holders enabled DVDD = MAX, VO = VSS to DVDD DVDD = MAX, VI = VSS to DVDD 300 MIN 2.4 0.4 300 A 5 5 TYP MAX UNIT V V High-level output voltage Low-level output voltage

VOH VOL

IIZ

Input current for outputs in high impedance

DVDD = MAX, VI = VSS to DVDD DVDD = MAX, VI = VSS to DVDD Pullup enabled DVDD = MAX, VI = VSS to DVDD DVDD = MAX, VI = VSS to DVDD CVDD = Nominal CPU clock = 300 MHz TC = 25C DVDD = Nominal CPU clock = 300 MHz TC = 25C PVDD = Nominal 20-MHz clock input, APLL mode = x15

5 50 300 5

300 50 5 5 A

II

Input current

Input pins with internal pullup All other input-only pins

IDDC

CVDD supply current

239

mA

IDDD

DVDD supply current

39

mA

IDDP Ci Co

PVDD supply current Input capacitance Output capacitance

11 3 3

mA pF pF

Current draw is highly application-dependent. The power numbers quoted here are for the sample application described in the TMS320VC5501/02 Power Consumption Summary application report (literature number SPRA993). The spreadsheet provided with the application report can be used to estimate the power consumption for a particular application. The spreadsheet also contains the current consumption that can be expected when running the DSP in its idle configurations. The sample application can be summarized as follows: Case temperature: 25C APLL: 300 MHz CPU: 85% utilization Instruction cache enabled CLKOUT off EMIF: 75 MHz, 118% utilization, 100% writes, 32 bits, 100% switching ECLKOUT1 and ECLKOUT2: Off HPI: 5Mwords/second, 100% utilization, 100% writes, 100% switching DMA: Channel 0: 35% utilization, 32-bit elements, 100% switching (for internal memory to external memory transfers) Channel 1: 1.56% utilization, 32-bit elements, 100% switching (for internal memory to McBSP0 transfers) Channel 2: 1.56% utilization, 32-bit elements, 100% switching (for McBSP1 to internal memory transfers) Channels 3 and 4: 0% utilization (reserved for UART transfers) Channel 5: 60% utilization (for internal memory to internal memory transfers using Watchdog Timer event) McBSP0: 25 MHz, 100% utilization, 100% switching Timer0: 5 MHz, 100% utilization, 100% switching Timer1: 10 MHz, 100% utilization, 100% switching WD Timer: 30 MHz, 100% utilization, 100% switching UART: 9600 baud, 100% utilization All other peripherals use 0 MHz, 0% utilization

138

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

Tester Pin Electronics

Data Sheet Timing Reference Point

42

3.5 nH Transmission Line Z0 = 50 (see note)

Output Under Test Device Pin (see note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 51. 3.3-V Test Load Circuit

5.5

Timing Parameter Symbology

Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings: a c d dis en f h r su t v w X access time cycle time (period) delay time disable time enable time fall time hold time rise time setup time transition time valid time pulse duration (width) Unknown, changing, or dont care level Letters and symbols and their meanings: H L V Z High Low Valid High impedance

December 2002 Revised November 2008

SPRS206K

139

Electrical Specifications

5.6

Clock Options
This section provides the timing requirements and switching characteristics for the various clock options available on the 5501.

5.6.1 Internal System Oscillator With External Crystal

The 5501 includes an internal oscillator which can be used in conjunction with an external crystal to generate the input clock to the DSP. The oscillator requires an external crystal connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock source must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator can be used as a clock source to the PLL, the crystal oscillation frequency can be multiplied to generate the input clock to the different clock groups of the DSP. GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0 bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and the input clock will be taken directly from the X2/CLKIN pin. The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance (ESR) as specified in Table 51. The connection of the required circuit is shown in Figure 52. Under some conditions, all the components shown are not required. The capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL in the equation is the load specified for the crystal that is also specified in Table 51. CL + C 1C 2 ( C 1 ) C 2)

X2/CLKIN

X1 RS Crystal

C1

C2

Figure 52. Internal System Oscillator With External Crystal Table 51. Recommended Crystal Parameters
FREQUENCY RANGE (MHz) 2015 1512 1210 108 86 65 MAXIMUM ESR SPECIFICATIONS () 40 40 40 60 60 80 CLOAD (pF) 10 16 16 18 18 18 MAXIMUM CSHUNT (pF) 7 7 7 7 7 7 RS (k) 0 0 2.8 2.2 8.8 14

140

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum ESR might seem to meet these specifications. However, it is recommended that crystals with actual maximum ESR specifications as shown in Table 51 be used since this will result in maximum crystal performance reliability.

5.6.2 Layout Considerations

Since parasitic capacitance, inductance, and resistance can be significant in this and any circuit, good PC board layout practices should always be observed when planning trace routing to the discrete components used in this oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close to the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible after routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should be run between these two signal lines. This also helps to minimize stray capacitance between these two signals.

December 2002 Revised November 2008

SPRS206K

141

Electrical Specifications

5.6.3 Clock Generation in Bypass Mode (APLL Synthesis Disabled)

Table 52 and Table 53 assume testing over recommended operating conditions (see Figure 53). Table 52. CLKIN in Bypass Mode Timing Requirements
NO. C7 C8 C9 C10 tc(CI) tf(CI) tr(CI) tw(CIL) Cycle time, CLKIN Fall time, CLKIN Rise time, CLKIN Pulse duration, CLKIN low 0.4 * tc(CI) APLL Synthesis Disabled MIN 20 MAX 10 10 UNIT ns ns ns ns

C11 tw(CIH) Pulse duration, CLKIN high 0.4 * tc(CI) ns If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 51. This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz.

Table 53. CLKOUT in Bypass Mode Switching Characteristics

NO. C1 C3 C4 C5 C6 tc(CO) tf(CO) tr(CO) tw(COL) PARAMETER Cycle time, CLKOUT Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low K * tc(CI)/2 1 MIN 20 TYP K * tc(CI) MAX 3 3 K * tc(CI)/2 + 1 UNIT ns ns ns ns

tw(COH) Pulse duration, CLKOUT high K * tc(CI)/2 1 K * tc(CI)/2 + 1 ns K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when SYSCLK1 is selected as CLKOUT and SYSCLK1 is set to the CPU clock divided by four, use K = 4. This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz.

C9 C7 CLKIN C10 C11 C8

C3 C1 CLKOUT C4

C6 C5

NOTE: The relationship of CLKIN to CLKOUT depends on the system clock selected to drive CLKOUT. The waveform relationship shown in Figure 53 is intended to illustrate the timing parameters only and may differ based on configuration.

Figure 53. Bypass Mode Clock Timings

142

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.6.4 Clock Generation in Lock Mode (APLL Synthesis Enabled)

The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N to generate the internal CPU clock cycle. The synthesis factor is determined by: N+ M D0 where: M = D0 = the multiply factor set in the PLLM field of the PLL Multiplier Control Register (PLLM) the divide factor set in the PLLDIV0 field of the PLL Divider 0 Register (PLLDIV0)

Valid values for M are (multiply by) 2 to 15. Valid values for D0 are (divide by) 1 to 32. For detailed information on clock generation configuration, see Section 3.9, System Clock Generator. Table 54 and Table 55 assume testing over recommended operating conditions (see Figure 54). Table 54. CLKIN in Lock Mode Timing Requirements
NO. C7 C8 C9 tc(CI) tf(CI) tr(CI) Cycle time, CLKIN Fall time, CLKIN Rise time, CLKIN APLL synthesis enabled MIN 10 MAX 83.3 10 10 UNIT ns ns ns

If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 51. The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range [tc(CO)].

Table 55. CLKOUT in Lock Mode Switching Characteristics

NO. C1 C3 C4 C5 C6 tc(CO) tf(CO) tr(CO) tw(COL) tw(COH) PARAMETER Cycle time, CLKOUT Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low Pulse duration, CLKOUT high K * tc(CI)/2N 1 K * tc(CI)/2N 1 MIN 6.66 TYP K * tc(CI)/N MAX 14.29 3 3 K * tc(CI)/2N + 1 K * tc(CI)/2N + 1 UNIT ns ns ns ns ns

N = Clock frequency synthesis factor. K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when SYSCLK1 is selected as CLKOUT and SYSCLK1 is set to the CPU clock divided by four, use K = 4.

December 2002 Revised November 2008

SPRS206K

143

Electrical Specifications
C8 C9 C7 CLKIN C6 C3 C5 C4

C1

CLKOUT

Bypass Mode

NOTE: The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen for the APLL synthesis and on the system clock selected to drive CLKOUT. The waveform relationship shown in Figure 54 is intended to illustrate the timing parameters only and may differ based on configuration.

Figure 54. External Multiply-by-N Clock Timings

144

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.6.5 EMIF Clock Options

Table 56 through Table 58 assume testing over recommended operating conditions (see Figure 55 through Figure 57). Table 56. EMIF Timing Requirements for ECLKIN
NO. E7 E8 E9 E10 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN low Transition time, ECLKIN MIN 10 0.4 * tc(EKI) 0.4 * tc(EKI) 2 MAX 16P UNIT ns ns ns ns

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

Table 57. EMIF Switching Characteristics for ECLKOUT1#

NO. E1 E2 E3 E4 E5 E6 tc(EKO1) tw(EKO1H) tw(EKO1L) tt(EKO1) td(EKIH-EKO1H) td(EKIL-EKO1L) PARAMETER Cycle time, ECLKOUT1 Pulse duration, ECLKOUT1 high Pulse duration, ECLKOUT1 low Transition time, ECLKOUT1 Delay time, ECLKIN high to ECLKOUT1 high Delay time, ECLKIN low to ECLKOUT1 low 3 3 MIN E1 EH 1 EL 1 MAX E+1 EH + 1 EL + 1 1 13 13 UNIT ns ns ns ns ns ns

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF. # EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF.

E7 E8 ECLKIN E9

E10

E10

Figure 55. ECLKIN Timings for EMIF

ECLKIN E1 E6 E5 ECLKOUT1 E2 E3 E4 E4

Figure 56. ECLKOUT1 Timings for EMIF Module

December 2002 Revised November 2008

SPRS206K

145

Electrical Specifications

Table 58. EMIF Switching Characteristics for ECLKOUT2

NO. E11 E12 E13 E14 E15 tc(EKO2) tw(EKO2H) tw(EKO2L) tt(EKO2) td(EKIH-EKO2H) td(EKIH-EKO2L) PARAMETER Cycle time, ECLKOUT2 Pulse duration, ECLKOUT2 high Pulse duration, ECLKOUT2 low Transition time, ECLKOUT2 Delay time, ECLKIN high to ECLKOUT2 high 3 3 MIN NE 1 0.5NE 1 0.5NE 1 MAX NE + 1 0.5NE + 1 0.5NE + 1 1 13 13 UNIT ns ns ns ns ns ns

E16 Delay time, ECLKIN high to ECLKOUT2 low The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF. N = the EMIF input clock divider; N = 1, 2, or 4.

E16 E15 ECLKIN E11 E12 ECLKOUT2 E13 E14 E14

Figure 57. ECLKOUT2 Timings for EMIF Module

146

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.7

Memory Timings

5.7.1 Asynchronous Memory Timings

Table 59 and Table 510 assume testing over recommended operating conditions (see Figure 58 and Figure 59). Table 59. Asynchronous Memory Cycle Timing Requirements for ECLKIN
NO. A3 A4 A6 A7 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, EMIF.Dx valid before EMIF.ARE high Hold time, EMIF.Dx valid after EMIF.ARE high Setup time, EMIF.ARDY valid before ECLKOUT1 high Hold time, EMIF.ARDY valid after ECLKOUT1 high MIN 6 1 3.5 1 MAX UNIT ns ns ns

ns To ensure data setup time, simply program the strobe width wide enough. EMIF.ARDY is internally synchronized. The EMIF.ARDY signal is recognized in the cycle for which the setup and hold time is met. To use EMIF.ARDY as an asynchronous input, the pulse width of the EMIF.ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.

Table 510. Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1

NO. A1 A2 A5 A8 A9 A10 tosu(SELV-AREL) toh(AREH-SELIV) td(EKO1H-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKO1H-AWEV) PARAMETER Output setup time, select signals valid to EMIF.ARE low Output hold time, EMIF.ARE high to select signals invalid Delay time, ECLKOUT1 high to EMIF.ARE valid Output setup time, select signals valid to EMIF.AWE low Output hold time, EMIF.AWE high to select signals invalid Delay time, ECLKOUT1 high to EMIF.AWE valid MIN RS * E 1.5 RH * E 1.5 1.5 WS * E 1.5 WH * E 1.5 1.5 5 5 MAX UNIT ns ns ns ns ns

ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT1 period in ns for EMIF. Select signals for EMIF include: EMIF.CEx, EMIF.BE[3:0], EMIF.A[21:2], and EMIF.AOE; and for EMIF writes, include EMIF.D[31:0].

December 2002 Revised November 2008

SPRS206K

147

Electrical Specifications
Setup = 2 ECLKOUT1 A1 EMIF.CEx A1 EMIF.BE[3:0] A1 EMIF.A[21:2] Address A3 A4 EMIF.D[31:0] A1 EMIF.AOE/SOE/SDRAS A5 EMIF.ARE/SADS/SDCAS/SRE EMIF.AWE/SWE/SDWE A6 EMIF.ARDY EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals), EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses. A7 A6 A5 Read Data A2 BE A2 A2 A2 Strobe = 3 Not Ready Hold = 2

A7

Figure 58. Asynchronous Memory Read Timings

148

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
Setup = 2 ECLKOUT1 A8 EMIF.CEx A8 EMIF.BE[3:0] A8 EMIF.A[21:2] A8 EMIF.D[31:0] EMIF.AOE/SOE/SDRAS EMIF.ARE/SADS/SDCAS/SRE A10 EMIF.AWE/SWE/SDWE A7 A6 EMIF.ARDY EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals), EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses. A6 A7 A10 Write Data Address A9 BE A9 A9 A9 Hold = 2

Strobe = 3

Not Ready

Figure 59. Asynchronous Memory Write Timings

December 2002 Revised November 2008

SPRS206K

149

Electrical Specifications

5.7.2 Programmable Synchronous Interface Timings

Table 511 and Table 512 assume testing over recommended operating conditions (see Figure 510 through Figure 512). Table 511. Programmable Synchronous Interface Timing Requirements
NO. PS6 PS7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EMIF.Dx valid before ECLKOUTx high Hold time, read EMIF.Dx valid after ECLKOUTx high MIN 2 1.5 MAX UNIT ns ns

Table 512. Programmable Synchronous Interface Switching Characteristics

NO. PS1 PS2 PS3 PS4 PS5 PS8 PS9 PS10 PS11 PS12 td(EKOxH-CEV) td(EKOxH-BEV) td(EKOxH-BEIV) td(EKOxH-EAV) td(EKOxH-EAIV) td(EKOxH-ADSV) td(EKOxH-OEV) td(EKOxH-EDV) td(EKOxH-EDIV) td(EKOxH-WEV) PARAMETER Delay time, ECLKOUTx high to EMIF.CEx valid Delay time, ECLKOUTx high to EMIF.BEx valid Delay time, ECLKOUTx high to EMIF.BEx invalid Delay time, ECLKOUTx high to EMIF.Ax valid Delay time, ECLKOUTx high to EMIF.Ax invalid Delay time, ECLKOUTx high to EMIF.SADS/SRE valid Delay time, ECLKOUTx high to, EMIF.SOE valid Delay time, ECLKOUTx high to EMIF.Dx valid Delay time, ECLKOUTx high to EMIF.Dx invalid Delay time, ECLKOUTx high to EMIF.SWE valid 0.8 0.8 7 0.8 0.8 0.8 7 7 7 0.8 7 MIN 0.8 MAX 7 7 UNIT ns ns ns ns ns ns ns ns ns

ns The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2): Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1). Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1). Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

150

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
READ latency = 2 ECLKOUTx PS1 EMIF.CEx EMIF.BE[3:0] EMIF.A[21:2] PS2 BE1 PS4 A1 A2 PS6 EMIF.D[31:0] EMIF.ARE/SADS/ SDCAS/SRE EMIF.AOE/SOE/SDRAS EMIF.AWE/SWE/SDWE The read latency and the length of EMIF.CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2). In the figure, SYNCRL = 2 and CEEXT = 0. The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2): Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1). Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1). Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and EMIF.SWE, respectively, during programmable synchronous interface accesses. PS8 PS9 Q1 A3 PS3 BE2 BE3 BE4 PS5 EA3 PS7 Q2 PS1

A4

Q3

Q4 PS8

PS9

Figure 510. Programmable Synchronous Interface Read Timings (With Read Latency = 2)

December 2002 Revised November 2008

SPRS206K

151

Electrical Specifications
ECLKOUTx EMIF.CEx PS1 PS2 BE1 PS4 A1 PS10 EMIF.D[31:0] EMIF.ARE/SADS/SDCAS/SRE EMIF.AOE/SOE/SDRAS PS12 EMIF.AWE/SWE/SDWE The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 0 and CEEXT = 0. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and EMIF.SWE, respectively, during programmable synchronous interface accesses. PS12 PS10 Q1 PS8 PS1 PS3 BE2 BE3 BE4 PS5 A2 A3 A4 PS11 Q2 Q3 Q4 PS8

EMIF.BE[3:0]

EMIF.A[21:2]

Figure 511. Programmable Synchronous Interface Write Timings (With Write Latency = 0)

152

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
Write Latency = 1 ECLKOUTx PS1 EMIF.CEx EMIF.BE[3:0] EMIF.A[21:2] PS10 EMIF.D[31:0] PS8 EMIF.ARE/SADS/ SDCAS/SRE EMIF.AOE/SOE/SDRAS PS12 EMIF.AWE/SWE/SDWE PS12 PS2 BE1 PS4 A1 PS3 BE2 A2 PS10 Q1 BE3 A3 Q2 BE4 PS5 A4 PS11 Q3 Q4 PS8 PS1

The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 1 and CEEXT = 0. The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2): Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1). Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1). Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and EMIF.SWE, respectively, during programmable synchronous interface accesses.

Figure 512. Programmable Synchronous Interface Write Timings (With Write Latency = 1)

December 2002 Revised November 2008

SPRS206K

153

Electrical Specifications

5.7.3 Synchronous DRAM Timings

Table 513 and Table 514 assume testing over recommended operating conditions (see Figure 513 through Figure 520). Table 513. Synchronous DRAM Cycle Timing Requirements
NO. SD6 SD7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EMIF.Dx valid before ECLKOUT1 high Hold time, read EMIF.Dx valid after ECLKOUT1 high MIN 2 2 MAX UNIT ns ns

Table 514. Synchronous DRAM Cycle Switching Characteristics

NO. SD1 SD2 SD3 SD4 SD5 SD8 SD9 SD10 SD11 SD12 SD13 td(EKO1H-CEV) td(EKO1H-BEV) td(EKO1H-BEIV) td(EKO1H-EAV) td(EKO1H-EAIV) td(EKO1H-CASV) td(EKO1H-EDV) td(EKO1H-EDIV) td(EKO1H-WEV) td(EKO1H-RASV) td(EKO1H-CKEV) PARAMETER Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid Delay time, ECLKOUT1 high to EMIF.BEx valid Delay time, ECLKOUT1 high to EMIF.BEx invalid Delay time, ECLKOUT1 high to EMIF.Ax valid Delay time, ECLKOUT1 high to EMIF.Ax invalid Delay time, ECLKOUT1 high to EMIF.SDCAS valid Delay time, ECLKOUT1 high to EMIF.Dx valid Delay time, ECLKOUT1 high to EMIF.Dx invalid Delay time, ECLKOUT1 high to EMIF.SDWE valid Delay time, ECLKOUT1 high to EMIF.SDRAS valid Delay time, ECLKOUT1 high to EMIF.SDCKE valid 0.8 0.8 0.8 0.8 7 7 7 0.8 0.8 7 7 0.8 7 MIN 0.8 MAX 7 7 UNIT ns ns ns ns ns ns ns ns ns ns ns

READ ECLKOUT1 SD1 EMIF.CEx EMIF.BE[3:0] SD4 EMIF.A[21:13] EMIF.A[11:2] Bank SD4 Column SD4 SD5 SD2 BE1 SD5 SD3 BE2 BE3 BE4 SD1

SD5 SD6

EMIF.A12 EMIF.D[31:0] EMIF.AOE/SOE/SDRAS SD8 EMIF.ARE/SADS/ SDCAS/SRE EMIF.AWE/SWE/SDWE EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses. SD8 D1 SD7 D2 D3 D4

Figure 513. SDRAM Read Command (CAS Latency 3)

154

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
WRITE ECLKOUT1 SD1 EMIF.CEx SD2 EMIF.BE[3:0] BE1 SD4 Bank SD4 Column SD4 EMIF.A12 SD9 EMIF.D[31:0] EMIF.AOE/SOE/SDRAS SD8 EMIF.ARE/SADS/ SDCAS/SRE SD11 EMIF.AWE/SWE/SDWE EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses. SD11 SD8 D1 SD9 D2 D3 D4 SD10 SD2 BE2 SD5 BE3 BE4 SD3 SD1

EMIF.A[21:13]

SD5

EMIF.A[11:2]

SD5

Figure 514. SDRAM Write Command

ACTV ECLKOUT1 SD1 EMIF.CEx EMIF.BE[3:0] SD4 Bank Activate SD4 Row Address SD4 Row Address SD5 SD1

EMIF.A[21:13] EMIF.A[11:2]

SD5

SD5

EMIF.A12 EMIF.D[31:0]

SD12 EMIF.AOE/SOE/SDRAS EMIF.ARE/SADS/ SDCAS/SRE EMIF.AWE/SWE/SDWE

SD12

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 515. SDRAM ACTV Command

December 2002 Revised November 2008

SPRS206K

155

Electrical Specifications
DCAB ECLKOUT1 SD1 EMIF.CEx EMIF.BE[3:0] EMIF.A[21:13, 11:2] SD4 EMIF.A12 EMIF.D[31:0] SD12 EMIF.AOE/SOE/SDRAS EMIF.ARE/SADS/SDCAS/SRE SD11 EMIF.AWE/SWE/SDWE EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses. SD11 SD12 SD5 SD1

Figure 516. SDRAM DCAB Command

DEAC ECLKOUT1 SD1 EMIF.CEx EMIF.BE[3:0] SD4 EMIF.A[21:13] EMIF.A[11:2] SD4 EMIF.A12 EMIF.D[31:0] SD12 EMIF.AOE/SOE/SDRAS EMIF.ARE/SADS/SDCAS/SRE SD11 EMIF.AWE/SWE/SDWE EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses. SD11 SD12 SD5 Bank SD5 SD1

Figure 517. SDRAM DEAC Command

156

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
REFR ECLKOUT1 SD1 EMIF.CEx EMIF.BE[3:0] EMIF.A[21:13, 11:2] SD1

EMIF.A12 EMIF.D[31:0] SD12 EMIF.AOE/SOE/SDRAS EMIF.ARE/SADS/ SDCAS/SRE SD8 SD8 SD12

EMIF.AWE/SWE/SDWE EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 518. SDRAM REFR Command

MRS ECLKOUT1 SD1 EMIF.CEx EMIF.BE[3:0] SD4 MRS value SD5 SD1

EMIF.A[21:2] EMIF.D[31:0]

SD12 EMIF.AOE/SOE/SDRAS SD8 EMIF.ARE/SADS/ SDCAS/SRE SD11 EMIF.AWE/SWE/SDWE

SD12

SD8

SD11

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 519. SDRAM MRS Command

December 2002 Revised November 2008

SPRS206K

157

Electrical Specifications
TRAS cycles Self Refresh ECLKOUT1 EMIF.CEx EMIF.BE[3:0] EMIF.A[21:13, 11:2] EMIF.A12 EMIF.D[31:0] EMIF.AOE/SOE/SDRAS EMIF.ARE/SADS/ SDCAS/SRE EMIF.AWE/SWE/SDWE SD13 EMIF.SDCKE EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses. SD13 End Self-Refresh

Figure 520. SDRAM Self-Refresh Timings

158

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.8

HOLD/HOLDA Timings
Table 515 and Table 516 assume testing over recommended operating conditions (see Figure 521). Table 515. EMIF.HOLD/HOLDA Timing Requirements

NO. toh(HOLDAL-HOLDL) Hold time, EMIF.HOLD low after EMIF.HOLDA low E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF. H3

MIN E

MAX

UNIT ns

Table 516. EMIF.HOLD/HOLDA Switching Characteristics

NO. H1 H2 H4 H5 H6 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) PARAMETER Delay time, EMIF.HOLD low to EMIF Bus high impedance Delay time, EMIF Bus high impedance to EMIF.HOLDA low Delay time, EMIF.HOLD high to EMIF Bus low impedance Delay time, EMIF Bus low impedance to EMIF.HOLDA high Delay time, EMIF.HOLD low to ECLKOUTx high impedance MIN 4E 0 2E 0 4E MAX 2E 7E 2E UNIT ns ns ns ns ns

H7 Delay time, EMIF.HOLD high to ECLKOUTx low impedance 2E 7E ns E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF. EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE, EMIF.SDCKE, and EMIF.SOE3. The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during EMIF.HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode, as shown in Figure 521. All pending EMIF transactions are allowed to complete before EMIF.HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

DSP Owns Bus

External Requestor Owns Bus H3

DSP Owns Bus

EMIF.HOLD H2 EMIF.HOLDA EMIF Bus H1 5501 H4 H5

ECLKOUTx H6 ECLKOUTx EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE, EMIF.SDCKE, and EMIF.SOE3. H7

Figure 521. EMIF.HOLD/HOLDA Timings

December 2002 Revised November 2008

SPRS206K

159

Electrical Specifications

5.9

Reset Timings
Table 517 and Table 518 assume testing over recommended operating conditions (see Figure 522). Table 517. Reset Timing Requirements

NO. R1

MIN

MAX

UNIT ns

tw(RSL) Pulse width, RESET low 2P + 5 P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

Table 518. Reset Switching Characteristics

NO. R2 R3 R4 R5 R6 R7 R8 R9 td(RSL-EMIFHZ) td(RSH-EMIFV) td(RSL-HIGHIV) td(RSH-HIGHV) td(RSL-ZHZ) td(RSH-ZV) td(RSL-IOIM) td(RSL-TGLD) PARAMETER Delay time, RESET low to EMIF group high impedance Delay time, RESET high to EMIF group valid Delay time, RESET low to high group invalid Delay time, RESET high to high group valid GPIO4 = 0 (CLKMOD = 0) GPIO4 = 0 (CLKMOD = 0) GPIO4 = 1 (CLKMOD = 1) MIN MAX 12 41115P + 21 148P + 22 12 41044P + 17 77P + 18 10 41044P + 18 77P + 19 13 11 + 14P ns ns ns ns ns ns ns UNIT ns

GPIO4 = 1 (CLKMOD = 1) Delay time, RESET low to Z group high impedance Delay time, RESET high to Z group invalid GPIO4 = 0 (CLKMOD = 0)

GPIO4 = 1 (CLKMOD = 1) Delay time, RESET low to Input/Output group switch to input mode# Delay time, RESET low to Toggle group switch to default toggle frequency||

P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns. EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0, EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA, ECLKOUT1. EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply for completeness. High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO. Z group: HRDY, HINT, DX1, DX0 # Input/Output group: PGPIO[45:0], HPI.HD[7:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, HR/W, HDS1, HDS2, NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, EMU0, EMU1/OFF. Signals in this group switch to input mode with reset. || Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.

160

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
R1 RESET R2 EMIF Group R4 High Group R6 Z Group R7 R5 R3

R8 Input/Output Group#

R9 Toggle Group||

The state of the DSP pins during power up is undefined until RESET is asserted. It is recommended that the RESET pin be kept low during power up. EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0, EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA, ECLKOUT1. EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply for completeness. High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO. Z group: HRDY, HINT, DX1, DX0 # Input/Output group: PGPIO[45:0], HPI.HD[7:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, HR/W, HDS1, HDS2, NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, EMU0, EMU1/OFF. Signals in this group switch to input mode with reset. || Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.

Figure 522. Reset Timings

December 2002 Revised November 2008

SPRS206K

161

Electrical Specifications

5.10 External Interrupt and Interrupt Acknowledge (IACK) Timings

Table 519 and Table 520 assume testing over recommended operating conditions (see Figure 523 and Figure 524). Table 519. External Interrupt and Interrupt Acknowledge Timing Requirements
NO. I1 tw(INTL)A Pulse width, interrupt low, CPU active MIN 3P 1P MAX UNIT ns ns

I2 tw(INTH)A Pulse width, interrupt high, CPU active P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

Table 520. External Interrupt and Interrupt Acknowledge Switching Characteristics

NO. I3 PARAMETER MIN MAX UNIT td(COH-IACKV) Delay time, CLKOUT high to IACK valid 0 8 ns In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra delay of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For example, if SYSCLK2 is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of one CPU clock period between the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the CPU clock, there might be an extra delay of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra delay must be taken into account when considering the MAX value for the timing under question. Note that if the CPU clock and the system clock shown on CLKOUT are operating at the same frequency, there will be no extra delay in the specified timing.

I1 INTx, NMI

I2

Figure 523. External Interrupt Timings

CLKOUT

I3

I3

IACK

NOTE: The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as the CPU clock.

Figure 524. External Interrupt Acknowledge Timings

162

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.11 XF Timings
Table 521 assumes testing over recommended operating conditions (see Figure 525). Table 521. XF Switching Characteristics
NO. X1 td(XF) PARAMETER Delay time, CLKOUT high to XF high Delay time, CLKOUT high to XF low MIN 0 0 MAX 5 6 ns UNIT

In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra delay of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For example, if SYSCLK2 is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of one CPU clock period between the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the CPU clock, there might be an extra delay of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra delay must be taken into account when considering the MAX value for the timing under question. Note that if the CPU clock and the system clock shown on CLKOUT are operating at the same frequency, there will be no extra delay in the specified timing.

CLKOUT X1 XF

NOTE: The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as the CPU clock.

Figure 525. XF Timings

December 2002 Revised November 2008

SPRS206K

163

Electrical Specifications

5.12 General-Purpose Input/Output (GPIOx) Timings

Table 522 and Table 523 assume testing over recommended operating conditions (see Figure 526).

Table 522. GPIO Pins Configured as Inputs Timing Requirements

NO. G2 G3 tsu(GPIOCOH) th(COHGPIO) Setup time, GPIOx input valid before CLKOUT high Hold time, GPIOx input valid after CLKOUT high MIN 5 0 MAX UNIT ns

ns In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

Table 523. GPIO Pins Configured as Outputs Switching Characteristics

NO. PARAMETER Delay time, CLKOUT high to GPIOx output change MIN MAX UNIT

G1 td(COHGPIO) 0 8 ns In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

CLKOUT

G2 G3 GPIOx Input Mode G1 GPIOx Output Mode

Figure 526. General-Purpose Input/Output (GPIOx) Signal Timings

164

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.13 Parallel General-Purpose Input/Output (PGPIOx) Timings

Table 524 and Table 525 assume testing over recommended operating conditions (see Figure 527). Table 524. PGPIO Pins Configured as Inputs Timing Requirements
NO. PG2 PG3 tsu(PGPIOCOH) th(COHPGPIO) Setup time, PGPIOx input valid before CLKOUT high Hold time, PGPIOx input valid after CLKOUT high MIN 6 0 MAX UNIT ns ns

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

Table 525. PGPIO Pins Configured as Outputs Switching Characteristics

NO. PG1 td(COHPGPIO) PARAMETER Delay time, CLKOUT high to PGPIOx output change MIN 0 MAX 10 UNIT ns

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

CLKOUT

PG2 PG3 PGPIOx Input Mode PG1 PGPIOx Output Mode

Figure 527. Parallel General-Purpose Input/Output (PGPIOx) Signal Timings

December 2002 Revised November 2008

SPRS206K

165

Electrical Specifications

5.14 TIM0/TIM1/WDTOUT Timings 5.14.1 TIM0/TIM1/WDTOUT Timer Pin Timings

Table 526 and Table 527 assume testing over recommended operating conditions (see Figure 528 and Figure 529). Table 526. TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements
NO. T4 T5 tw(TIML) tw(TIMH) Pulse width, TIM0/TIM1/WDTOUT low Pulse width, TIM0/TIM1/WDTOUT high MIN 4P 4P MAX UNIT ns

ns P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

Table 527. TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics
NO. T1 T2 T3 td(COHTIMH) td(COHTIML) PARAMETER Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low MIN 0 0 P MAX 6 7 UNIT ns ns

tw(TIM) Pulse duration, TIM0/TIM1/WDTOUT ns P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

T5 T4 TIM0/TIM1/WDTOUT as Input

Figure 528. TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins

CLKOUT T2 T1 TIM0/TIM1/WDTOUT as Output T3

Figure 529. TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins

166

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.14.2

TIM0/TIM1/WDTOUT General-Purpose I/O Timings

Table 528. TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements

Table 528 and Table 529 assume testing over recommended operating conditions (see Figure 530).

NO. T9 T10 T11 T12 T13 T14 tsu(TIM0GPIOCOH) th(COHTIM0GPIO) tsu(TIM1GPIOCOH) th(COHTIM1GPIO) tsu(WDTGPIOCOH) th(COHWDTGPIO) Setup time, TIM0-GPIO input mode before CLKOUT high Hold time, TIM0-GPIO input mode after CLKOUT high Setup time, TIM1-GPIO input mode before CLKOUT high Hold time, TIM1-GPIO input mode after CLKOUT high Setup time, WDTOUT-GPIO input mode before CLKOUT high Hold time, WDTOUT-GPIO input mode after CLKOUT high

MIN 5 0 5 0 5 0

MAX

UNIT ns ns ns ns ns ns

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

Table 529. TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics

NO. T6 T7 T8 td(COHTIM0GPIO) td(COHTIM1GPIO) td(COHWDTGPIO) PARAMETER Delay time, CLKOUT high to TIM0-GPIO output mode Delay time, CLKOUT high to TIM1-GPIO output mode Delay time, CLKOUT high to WDTOUT-GPIO output mode MIN MAX 10 10 10 UNIT ns ns ns

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

CLKOUT T9 T10 TIM0 GPIO Input Mode T6 TIM0 GPIO Output Mode T11 T12 TIM1 GPIO Input Mode T7 TIM1 GPIO Output Mode T13 T14 WDTOUT GPIO Input Mode T8 WDTOUT GPIO Output Mode

Figure 530. TIM0/TIM1/WDTOUT General-Purpose I/O Timings

December 2002 Revised November 2008

SPRS206K

167

Electrical Specifications

5.14.3

TIM0/TIM1/WDTOUT Interrupt Timings

Table 530 assumes testing over recommended operating conditions (see Figure 531). Table 530. TIM0/TIM1/WDTOUT Interrupt Timing Requirements
NO. T15 T16 T17 T18 T19 T20 T21 T22 tsu(TIM0LCOH) th(COHTIM0L) tw(TIM0L) tsu(TIM1LCOH) th(COHTIM1L) tw(TIM1L) tsu(WDTLCOH) th(COHWDTL) Setup time, TIM0 low before CLKOUT rising edge Hold time, TIM0 low after CLKOUT rising edge Pulse width, TIM0 low Setup time, TIM1 low before CLKOUT rising edge Hold time, TIM1 low after CLKOUT rising edge Pulse width, TIM1 low Setup time, WDTOUT low before CLKOUT rising edge Hold time, WDTOUT low after CLKOUT rising edge Pulse width, WDTOUT low MIN 5 0 P 5 0 P 5 0 MAX UNIT ns ns ns ns ns ns ns ns

T23 tw(WDTL) P ns In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT. P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. An interrupt can be triggered by setting the timer pins high or low, depending on the setting of the TIN1INV bit in the GPIO Interrupt Control Register (GPINT). Refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for more information on the interrupt capability of the timer pins.

CLKOUT T15 T16 T17 TIM0 T18 T19 T20 TIM1 T21 T22 T23 WDTOUT

Figure 531. TIM0/TIM1/WDTOUT Interrupt Timings

168

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.15 Multichannel Buffered Serial Port (McBSP) Timings 5.15.1 McBSP Transmit and Receive Timings

Table 531 and Table 532 assume testing over recommended operating conditions (see Figure 532 and Figure 533). Table 531. McBSP Transmit and Receive Timing Requirements
NO. M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 tc(CKRX) tw(CKRX) tr(CKRX) tf(CKRX) tsu(FRHCKRL) th(CKRLFRH) tsu(DRVCKRL) th(CKRLDRV) tsu(FXHCKXL) th(CKXLFXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Rise time, CLKR/X Fall time, CLKR/X Setup time, external FSR high before CLKR low Hold time, external FSR high after CLKR low Setup time, DR valid before CLKR low Hold time, DR valid after CLKR low Setup time, external FSX high before CLKX low Hold time, external FSX high after CLKX low CLKR/X ext CLKR/X ext CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext 5 1 1 6 3 1 1 6 5 1 1 6 ns ns ns ns ns ns MIN 2P P2 5 5 MAX UNIT ns ns ns ns

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

December 2002 Revised November 2008

SPRS206K

169

Electrical Specifications

Table 532. McBSP Transmit and Receive Switching Characteristics

NO. M1 M2 M3 M4 M5 M6 tc(CKRX) tw(CKRXH) tw(CKRXL) td(CKRHFRV) td(CKXHFXV) Cycle time, CLKR/X Pulse duration, CLKR/X high Pulse duration, CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid PARAMETER CLKR/X int CLKR/X int CLKR/X int CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int DXENA = 0 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes Enable time, CLKX high to DX driven DXENA = 0 M8 ten(CKXHDX) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes Delay time, FSX high to DX valid DXENA = 0 M9 td(FXHDXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. Enable time, FSX high to DX driven DXENA = 0 M10 ten(FXHDX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode CLKX ext CLKX int DXENA = 1 CLKX ext CLKX int CLKX ext CLKX int DXENA = 1 CLKX ext FSX int FSX ext FSX int DXENA = 1 FSX ext FSX int FSX ext FSX int DXENA = 1 FSX ext 0 6 2P P+6 ns 0 6 2P 2P+6 2 7 2P+2 2P+7 ns ns MIN 2P D1 C1 2 4 0 4 5 1 MAX D+1 C+1 6 16 6 16 5 11 6 16 6 16 2P+2 2P+8 ns ns ns ns UNIT ns ns ns

Disable time, CLKX high to DX high impedance tdis(CKXHDXHZ) following last data bit Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. Delay time, CLKX high to DX valid

M7

td(CKXHDXV)

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even See the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592) for a description of the DX enable (DXENA) and data delay features of the McBSP.

170

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
M1, M11 M2, M12 M13 M3, M12 CLKR M4 FSR (Int) M15 FSR (Ext) M17 DR (RDATDLY=00b) M18 Bit (n1) M17 DR (RDATDLY=01b) Bit (n1) M17 DR (RDATDLY=10b) Bit (n1) (n2) M18 (n2) M18 (n2) (n3) (n3) (n4) M16 M4 M14

Figure 532. McBSP Receive Timings

M1, M11 M2, M12 M3, M12 CLKX M5 FSX (Int) M19 FSX (Ext) M9 M10 DX (XDATDLY=00b) DX (XDATDLY=01b) Bit 0 Bit (n1) M8 Bit 1 M6 DX (XDATDLY=10b) NOTE A: Bit 2 Bit 1 Bit 0 Bit (n1) M8 Bit 0 Bit (n1) (n2) (n2) M7 (n2) M7 (n3) M7 (n3) (n4) M20 M5 M13 M14

This figure does not include first or last frames. For first frame, no data will be present before frame synchronization. For last frame, no data will be present after frame synchronization.

Figure 533. McBSP Transmit Timings

December 2002 Revised November 2008

SPRS206K

171

Electrical Specifications

5.15.2

McBSP General-Purpose I/O Timings

Table 533 and Table 534 assume testing over recommended operating conditions (see Figure 534). Table 533. McBSP General-Purpose I/O Timing Requirements
NO. M22 tsu(MGPIOCOH) th(COHMGPIO) Setup time, MGPIOx input mode before CLKOUT high Hold time, MGPIOx input mode after CLKOUT high MIN 4 MAX UNIT ns

M23 0 ns MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input. In this case, CLKOUT reflects SYSCLK2. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK2 as CLKOUT.

Table 534. McBSP General-Purpose I/O Switching Characteristics

NO. M21 PARAMETER MIN MAX UNIT td(COHMGPIO) Delay time, CLKOUT high to MGPIOx output mode 0 6 ns In this case, CLKOUT reflects SYSCLK2. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK2 as CLKOUT. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.

M22 CLKOUT M21 M23 MGPIO Input Mode

MGPIO Output Mode MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.

Figure 534. McBSP General-Purpose I/O Timings

172

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.15.3

McBSP as SPI Master or Slave Timings

Table 535 to Table 542 assume testing over recommended operating conditions (see Figure 535 through Figure 538). Table 535. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER NO. M30 M31 M32 M33 tsu(DRVCKXL) th(CKXLDRV) tsu(FXLCKXH) tc(CKX) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low Setup time, FSX low before CLKX high Cycle time, CLKX 2P MIN 13 1 MAX SLAVE MIN 0 5P 9 + 6P 10 16P MAX UNIT ns ns ns

ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 536. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER NO. M24 M25 M26 M27 M28 td(CKXLFXL) td(FXLCKXH) td(CKXHDXV) tdis(CKXLDXHZ) tdis(FXHDXHZ) PARAMETER Delay time, CLKX low to FSX low# Delay time, FSX low to CLKX high|| Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high MIN T2 C6 4 C2 MAX T+6 C+4 6 C +10 2P+ 4 4P + 10 4P 6P SLAVE MIN MAX UNIT ns ns ns ns ns

M29 td(FXLDXV) Delay time, FSX low to DX valid 2P + 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592). T = BCLKX period = (1 + CLKGDV) * 2P C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even # FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP || FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

December 2002 Revised November 2008

SPRS206K

173

Electrical Specifications
LSB CLKX M25 M24 FSX M28 M27 DX Bit 0 M30 M31 DR Bit 0 Bit (n1) (n2) (n3) (n4) M29 Bit (n1) (n2) (n3) (n4) M26 M32 MSB M33

Figure 535. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

174

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

Table 537. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER NO. M39 M40 M41 tsu(DRVCKXH) th(CKXHDRV) tsu(FXLCKXH) tc(CKX) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high Setup time, FSX low before CLKX high MIN 13 1 MAX SLAVE MIN 0 5P 9 + 6P 10 MAX UNIT ns ns ns

M42 Cycle time, CLKX 2P 16P ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 538. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER NO. M34 M35 M36 M37 td(CKXLFXL) td(FXLCKXH) td(CKXLDXV) tdis(CKXLDXHZ) PARAMETER Delay time, CLKX low to FSX low# Delay time, FSX low to CLKX high|| Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low MIN C2 T6 4 2 MAX C+6 T+4 6 10 4P 3P + 4 6P 4P + 18 SLAVE MIN MAX UNIT ns ns ns ns

M38 td(FXLDXV) Delay time, FSX low to DX valid D2 D +10 2P 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592). T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even # FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP || FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). MSB LSB CLKX M35 M34 FSX M38 M36 M41 M42

M37 DX Bit 0 M39

Bit (n1)

(n2) M40

(n3)

(n4)

DR

Bit 0

Bit (n1)

(n2)

(n3)

(n4)

Figure 536. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

December 2002 Revised November 2008

SPRS206K

175

Electrical Specifications

Table 539. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER NO. M49 M50 M51 tsu(DRVCKXH) th(CKXHDRV) tsu(FXLCKXL) tc(CKX) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high Setup time, FSX low before CLKX low MIN 13 1 MAX SLAVE MIN 0 5P 9 + 6P 10 MAX UNIT ns ns ns

M52 Cycle time, CLKX 2P 16P ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 540. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER NO. M43 M44 M45 M46 M47 td(CKXHFXL) td(FXLCKXL) td(CKXLDXV) tdis(CKXHDXHZ) tdis(FXHDXHZ) PARAMETER Delay time, CLKX high to FSX low# Delay time, FSX low to CLKX low|| Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high MIN T2 D6 4 D2 MAX T+6 D+4 6 D +10 2P + 4 4P + 10 4P 6P SLAVE MIN MAX UNIT ns ns ns ns ns

M48 td(FXLDXV) Delay time, FSX low to DX valid 2P 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592). T = CLKX period = (1 + CLKGDV) * P D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even # FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP || FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

176

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
LSB CLKX M44 M43 FSX M47 M46 DX Bit 0 M49 M50 DR Bit 0 Bit (n1) (n2) (n3) (n4) M48 Bit (n1) (n2) (n3) (n4) M45 M51 MSB M52

Figure 537. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

December 2002 Revised November 2008

SPRS206K

177

Electrical Specifications

Table 541. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER NO. M58 M59 M60 tsu(DRVCKXL) th(CKXLDRV) tsu(FXLCKXL) tc(CKX) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low Setup time, FSX low before CLKX low MIN 13 1 MAX SLAVE MIN 0 5P 9 + 6P 10 MAX UNIT ns ns ns

M61 Cycle time, CLKX 2P 16P ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 542. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
MASTER NO. M53 M54 M55 M56 td(CKXHFXL) td(FXLCKXL) td(CKXHDXV) tdis(CKXHDXHZ) PARAMETER Delay time, CLKX high to FSX low# Delay time, FSX low to CLKX low|| Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high MIN D2 T6 4 2 MAX D+6 T+4 6 10 4P 3P + 4 6P 4P + 18 SLAVE MIN MAX UNIT ns ns ns ns

M57 td(FXLDXV) Delay time, FSX low to DX valid C2 C +10 2P 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592). T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even # FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP || FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). LSB CLKX M54 M53 FSX M57 M55 M60 MSB M61

M56 DX Bit 0

Bit (n1) M58

(n2) M59

(n3)

(n4)

DR

Bit 0

Bit (n1)

(n2)

(n3)

(n4)

Figure 538. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

178

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.16 Host-Port Interface Timings 5.16.1 HPI Read and Write Timings

Table 543 and Table 544 assume testing over recommended operating conditions (see Figure 539 through Figure 543). Table 543. HPI Read and Write Timing Requirements
NO. H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H37 tsu(HASLDSL) th(DSLHASL) tsu(HADHASL) th(HASLHAD) tw(DSL) tw(DSH) tsu(HADDSL) th(DSLHAD) tsu(HDDSH) th(DSHHD) tsu(HCSL-DSL) Setup time, HPI.HAS low before DS falling edge Hold time, HPI.HAS low after DS falling edge Setup time, HAD valid before HPI.HAS falling edge Hold time, HAD valid after HPI.HAS falling edge Pulse duration, DS low Pulse duration, DS high Setup time, HAD valid before DS falling edge Hold time, HAD valid after DS falling edge Setup time, HD valid before DS rising edge Hold time, HD valid after DS rising edge Setup time, HCS low before DS falling edge MIN 5 2 5 5 15 2P 5 5 5 0 0 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns

H38 th(HRDYH-DSL) Hold time, DS low after HRDY rising edge 0 ns P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1, HPI.HBIL, and HR/W. A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.7, Host-Port Interface (HPI), for more details.

December 2002 Revised November 2008

SPRS206K

179

Electrical Specifications

Table 544. HPI Read and Write Switching Characteristics

NO. PARAMETER Case 1. HPIC or HPIA read Case 2. HPID read with no auto-increment H1 td(DSLHDV) Delay time, DS low to HD valid Case 3. HPID read with auto-increment and read FIFO initially empty K = 1|| K = 2|| K = 4|| K = 1|| K = 2|| K = 4|| 5 1 3 MIN 5 MAX 15 9 * 2H + 20 10 * 2H + 20 11 * 2H + 20 9 * 2H + 20 10 * 2H + 20 11 * 2H + 20 15 4 15 12 12 Case 1. HPID read with no auto-increment H6 td(DSLHRDYH) Delay time, DS low to HRDY high Case 2. HPID read with auto-increment and read FIFO initially empty K = 1|| K = 2|| K = 4|| K = 1|| K = 2|| K = 4|| 0 8 K = 1, 2, 4|| K = 1|| Case 2. HPID write with no auto-increment K = 2|| K = 4|| K = 1|| H35 td(DSL-HRDYH) Delay time, DS low to HRDY high for HPIA write and FIFO not empty Delay time, HPI.HAS low to HRDY low K = 2|| K = 4|| H36 td(HASL-HRDYL) 5 * 2H + 20 5 * 2H + 20 5 * 2H + 20 6 * 2H + 20 40 * 2H + 20 40 * 2H + 20 24 * 2H + 20 12 ns ns ns 10 * 2H + 20 11 * 2H + 20 12 * 2H + 20 10 * 2H + 20 11 * 2H + 20 12 * 2H + 20 ns ns ns ns ns ns ns ns ns UNIT

Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO H2 H3 H4 H5 tdis(DSHHDV) ten(DSLHDD) td(DSLHRDYL) td(DSHHRDYL) Disable time, HD high-impedance from DS high Enable time, HD driven from DS low Delay time, DS low to HRDY low Delay time, DS high to HRDY low

H7 H8

td(HDVHRDYH) td(COHHINT)

Delay time, HD valid to HRDY high Delay time, CLKOUT high to HINT change# Case 1. HPIA write

H34

td(DSH-HRDYH)

Delay time, DS high to HRDY high

DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1, HPI.HBIL, and HR/W. H is half the SYSCLK1 clock cycle. A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.7, Host-Port Interface (HPI), for more details. Assumes no other DMA or CPU memory activity. # In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT. || K = divider ratio between CPU clock and SYSCLK1. For example, when SYSCLK1 is set to the CPU clock divided by four, use K = 4.

180

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
HCS

HPI.HAS H12 H11 HCNTL[1:0] H12 H11 HR/W H12 H11 HPI.HBIL H10 H9 H37 DS H1 H3 HPI.HD[7:0] H7 H36 HRDY NOTE: Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)]. H6 H38 H1 H3 H2 H10 H13 H37 H14 H9 H13 H11 H12 H11 H12 H12 H11

H2

Figure 539. Multiplexed Read Timings Using HPI.HAS

December 2002 Revised November 2008

SPRS206K

181

Electrical Specifications
HCS HPI.HAS HCNTL[1:0] HR/W HPI.HBIL H13 H16 H15 H37 DS H3 H1 HPI.HD[7:0] H38 H4 H6 HRDY NOTE: Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)]. H7 H3 H2 H1 H2 H37 H14 H15 H13 H16

Figure 540. Multiplexed Read Timings With HPI.HAS Held High

182

SPRS206K

December 2002 Revised November 2008

Electrical Specifications
HCS

HPI.HAS H12 H11 HCNTL[1:0] H12 H11 HR/W H12 H11 HPI.HBIL H10 H9 H37 DS H13 H18 H17 HPI.HD[7:0] H35 H36 HRDY NOTE: Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)]. H38 H34 H5 H5 H34 H17 H14 H37 H13 H9 H10 H11 H12 H11 H12 H11 H12

H18

Figure 541. Multiplexed Write Timings Using HPI.HAS

December 2002 Revised November 2008

SPRS206K

183

Electrical Specifications
HCS HPI.HAS HCNTL[1:0] HR/W HPI.HBIL H16 H13 H15 H37 DS H18 H17 HPI.HD[7:0] H38 H35 HRDY NOTE: Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)]. H34 H5 H5 H17 H18 H14 H16 H15 H37 H13

H4

H34

Figure 542. Multiplexed Write Timings With HPI.HAS Held High

CLKOUT

H8 HINT

Figure 543. HINT Timings

184

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.16.2

HPI General-Purpose I/O Timings

Table 545 and Table 546 assume testing over recommended operating conditions (see Figure 544). Table 545. HPI General-Purpose I/O Timing Requirements
NO. H27 H28 H29 tsu(HDGPIOCOH) th(COHHDGPIO) tsu(HCGPIOCOH) Setup time, HDGPIO input mode before CLKOUT high Hold time, HDGPIO input mode after CLKOUT high Setup time, HCGPIO input mode before CLKOUT high Hold time, HCGPIO input mode after CLKOUT high MIN 5 0 5 MAX UNIT ns ns ns

H30 th(COHHCGPIO) 0 ns In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT. HDGPIO refers to HPI.HD[7:0] configured as general-purpose input. HCGPIO refers to HPI.HAS, HPI.HBIL, HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2, HRDY, and HINT configured as general-purpose input.

Table 546. HPI General-Purpose I/O Switching Characteristics

NO. H21 H22 td(COHHDGPIO) PARAMETER Delay time, CLKOUT high to HDGPIO output mode MIN MAX 10 UNIT ns

td(COHHCGPIO) Delay time, CLKOUT high to HCGPIO output mode# 10 ns In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT. HDGPIO refers to HPI.HD[7:0] configured as general-purpose output. # HCGPIO refers to HPI.HAS, HPI.HBIL, HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2, HRDY, and HINT configured as general-purpose output.

CLKOUT H27 H28 HDGPIO Input Mode H21 HDGPIO Output Mode H29 H30 HCGPIO Input Mode H22 HCGPIO Output Mode

Figure 544. HPI General-Purpose I/O Timings

December 2002 Revised November 2008

SPRS206K

185

Electrical Specifications

5.16.3

HPI.HAS Interrupt Timings

Table 547 assumes testing over recommended operating conditions (see Figure 545). Table 547. HPI.HAS Interrupt Timing Requirements
NO. H31 H32 tsu(HASLCOH) th(COHHASL) Setup time, HPI.HAS low before CLKOUT rising edge Hold time, HPI.HAS low after CLKOUT rising edge Pulse width, HPI.HAS low MIN 5 0 P MAX UNIT ns ns

H33 tw(HASL) ns In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT. An interrupt can be triggered by setting the HPI.HAS signal high or low, depending on the setting of the HAS bit in the General-Purpose I/O Interrupt Control Register 2 (HPGPIOINT2). Refer to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for more information on the interrupt capability of the HPI.HAS signal. P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

CLKOUT H31 H32 H33 HPI.HAS

Figure 545. HPI.HAS Interrupt Timings

186

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.17 Inter-Integrated Circuit (I2C) Timings

Table 548 and Table 549 assume testing over recommended operating conditions (see Figure 546 and Figure 547). Table 548. I2C Signals (SDA and SCL) Timing Requirements
NO. IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 tc(SCL) tsu(SCLH-SDAL) th(SCLL-SDAL) tw(SCLL) tw(SCLH) tsu(SDA-SCLH) th(SDA-SCLL) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(SCLH-SDAH) tw(SP) Cb Cycle time, SCL Setup time, SCL high before SDA low for a repeated START condition Hold time, SCL low after SDA low for a START and a repeated START condition Pulse duration, SCL low Pulse duration, SCL high Setup time, SDA valid before SCL high Hold time, SDA valid after SCL low Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Setup time, SCL high before SDA high (for STOP condition) Pulse duration, spike (must be suppressed) 4.0 For I2C bus devices Pulse duration, SDA high between STOP and START conditions STANDARD MODE MIN 10 4.7 4 4.7 4 250 0 4.7 1000 1000 300 300 MAX FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 0 1.3 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0.6 0 50 MAX s s s s s ns 0.9 300 300 300 300 s s ns ns ns ns s ns UNIT

IC15 Capacitive load for each bus line 400 400 pF A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDASCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDASCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDASCLL) has only to be met if the 5501 I2C operates in master-receiver mode and the slave device does not stretch the LOW period [tw(SCLL)] of the SCL signal. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

IC11 SDA IC8 IC4 IC10 SCL IC1 IC7 IC3 Stop Start Repeated Start IC12 IC3 IC2 IC5 IC6 IC14 IC13

IC9

Stop

Figure 546. I2C Receive Timings

I2C Bus is a trademark of Koninklijke Philips Electronics N.V. December 2002 Revised November 2008 SPRS206K 187

Electrical Specifications

Table 549. I2C Signals (SDA and SCL) Switching Characteristics

NO. IC16 IC17 IC18 IC19 IC20 IC21 IC22 IC23 IC24 IC25 IC26 IC27 IC28 IC29 tc(SCL) td(SCLH-SDAL) td(SDAL-SCLL) tw(SCLL) tw(SCLH) td(SDA-SCLH) tv(SCLL-SDAV) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) td(SCLH-SDAH) Cp PARAMETER Cycle time, SCL Delay time, SCL high to SDA low for a repeated START condition Delay time, SDA low to SCL low for a START and a repeated START condition Pulse duration, SCL low Pulse duration, SCL high Delay time, SDA valid to SCL high Valid time, SDA valid after SCL low Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Delay time, SCL high to SDA high for a STOP condition Capacitance for each I2C pin 4 10 For I2C bus devices Pulse duration, SDA high between STOP and START conditions STANDARD MODE MIN 10 4.7 4 4.7 4 250 0 4.7 1000 1000 300 300 MAX FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 0 1.3 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0.6 10 300 300 300 300 MAX s s s s s ns s s ns ns ns ns s pF UNIT

Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

IC26 SDA IC23 IC19 IC25 SCL IC16 IC22 IC18 Stop Start Repeated Start IC27 IC18 IC17 IC20 IC21

IC24

IC28

Stop

Figure 547. I2C Transmit Timings

188

SPRS206K

December 2002 Revised November 2008

Electrical Specifications

5.18 Universal Asynchronous Receiver/Transmitter (UART) Timings

Table 550 to Table 551 assume testing over recommended operating conditions (see Figure 548). Table 550. UART Timing Requirements
NO. U4 U5 tw(UDB)R tw(USB)R Pulse width, receive data bit Pulse width, receive start bit MIN 0.96U 0.96U MAX 1.05U 1.05U UNIT ns ns

U = UART baud time = 1/programmed baud rate

Table 551. UART Switching Characteristics

NO. U1 U2 U3 fbaud tw(UDB)X PARAMETER Maximum programmable baud rate Pulse width, transmit data bit U 2 U 2 MIN MAX 5 U+2 U + 2 UNIT MHz ns ns

tw(USB)X Pulse width, transmit start bit U = UART baud time = 1/programmed baud rate

U3 Data Bits UART.TX Start Bit

U2

Data Bits UART.RX Start Bit

U4 U5

Figure 548. UART Timings

December 2002 Revised November 2008

SPRS206K

189

Mechanical Data

Mechanical Data
Some TMX samples were shipped in the GGW package. For more information on the GGW package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number SPRZ020D or later). TMS320VC5501PGF has completed Temp Cycle reliability qualification testing with no failures through 1500 cycles of 55C to 125C following an EIA/JEDEC Moisture Sensitivity Level 4 pre-condition at 220+5/0C peak reflow. Exceeding this peak reflow temperature condition or storage and handling requirements may result in either immediate device failure post-reflow, due to package/die material delamination (popcorning), or degraded Temp cycle life performance. Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life information on a bar-code label affixed to dry-pack shipping bags. Shelf life, temperature and humidity storage conditions and re-bake instructions are prominently displayed on a nearby screen-printed label.

6.1

Package Thermal Resistance Characteristics

Table 61 and Table 62 provide the thermal resistance characteristics for the recommended package types used on the TMS320VC5501 DSP. NOTE: Some TMX samples were shipped in the GGW package. For more information on the GGW package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number SPRZ020D or later). Table 61. Thermal Resistance Characteristics (Ambient)
PACKAGE RJA (C/W) 94 93 91 87 (Without thermal vias) 117 114 GZZ, ZZZ 109 101 39 (With thermal vias) 37 36 34 BOARD TYPE High-K High-K High-K High-K Low-K Low-K Low-K Low-K High-K High-K High-K High-K AIRFLOW (LFM) 0 150 250 500 0 150 250 500 0 150 250 500

Board types are as defined by JEDEC. Reference JEDEC Standard JESD519, Test Boards for Area Array Surface Mount Package Thermal Measurements. Adding thermal vias will significantly improve the thermal performance of the device. To use the thermal balls on the GZZ and ZZZ packages: An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted. The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability Temperature Cycle performance. The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be connected to the ground plane for heat dissipation. A solid internal plane is preferred for spreading the heat. Refer to the MicroStar BGAE Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount, and reliability considerations.

190

SPRS206K

December 2002 Revised November 2008

Mechanical Data

Table 61. Thermal Resistance Characteristics (Ambient) (Continued)

PACKAGE RJA (C/W) 60 52 49 45 PGF 104 81 73 64 BOARD TYPE High-K High-K High-K High-K Low-K Low-K Low-K Low-K AIRFLOW (LFM) 0 150 250 500 0 150 250 500

Board types are as defined by JEDEC. Reference JEDEC Standard JESD519, Test Boards for Area Array Surface Mount Package Thermal Measurements. Adding thermal vias will significantly improve the thermal performance of the device. To use the thermal balls on the GZZ and ZZZ packages: An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted. The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability Temperature Cycle performance. The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be connected to the ground plane for heat dissipation. A solid internal plane is preferred for spreading the heat. Refer to the MicroStar BGAE Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount, and reliability considerations.

Table 62. Thermal Resistance Characteristics (Case)

PACKAGE GZZ, ZZZ PGF RJC (C/W) 22 13.2 BOARD TYPE 2s JEDEC Test Card 2s JEDEC Test Card

Board types are as defined by JEDEC. Reference JEDEC Standard JESD519, Test Boards for Area Array Surface Mount Package Thermal Measurements.

December 2002 Revised November 2008

SPRS206K

191

Mechanical Data

6.2

Packaging Information
The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document.

192

SPRS206K

December 2002 Revised November 2008

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION
Orderable Device TMS320VC5501GZZ300 Status
(1)

Package Type Package Pins Package Drawing Qty BGA MICROSTAR LQFP GZZ 201 126

Eco Plan
(2)

Lead/Ball Finish SNPB

MSL Peak Temp

(3)

Op Temp (C) -40 to 85

Top-Side Markings
(4)

Samples

ACTIVE

TBD

Level-3-220C-168 HR

320VC5501GZZ TMS 300 320VC5501PGF TMS 300 320VC5501ZZZ TMS 300

TMS320VC5501PGF300

ACTIVE

PGF

176

40

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD

CU NIPDAU

Level-4-260C-72 HR

-40 to 85

TMS320VC5501ZZZ300

ACTIVE

BGA MICROSTAR BGA MICROSTAR LQFP

ZZZ

201

126

SNAGCU

Level-3-260C-168 HR

-40 to 85

TMX320VC5501GZZ300 TMX320VC5501PGF300
(1)

OBSOLETE OBSOLETE

GZZ PGF

201 176

Call TI Call TI

Call TI Call TI

-40 to 85 -40 to 85

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/omap TI E2E Community e2e.ti.com www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2013, Texas Instruments Incorporated Applications Automotive and Transportation Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Video and Imaging www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video