Scribd
Upload
288 views

hw4 Sol

The document discusses page replacement policies and their effect on CPU utilization. It provides examples to calculate the number of page faults that would occur under FIFO and LRU policies given a sample reference string and limited page frames. Specifically, it finds that for the given reference string 0172327103, FIFO would result in 6 page faults while LRU would result in 7 page faults.

Uploaded by

adviful
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
288 views

hw4 Sol

The document discusses page replacement policies and their effect on CPU utilization. It provides examples to calculate the number of page faults that would occur under FIFO and LRU policies given a sample reference string and limited page frames. Specifically, it finds that for the given reference string 0172327103, FIFO would result in 6 page faults while LRU would result in 7 page faults.

Uploaded by

adviful
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

CSE 120: Homework #4

Fall 2010
1. Suppose a machine has the following hardware characteristics and current state (a) It takes 0.1 nanoseconds to access a cache line from its physical memory (b) It takes 1millisecond to access a page of 4Kbytes from the disk (c) It takes 0 second to access TLB, L1 & L2 processor caches (for simplicity) (d) All page tables can fit into the physical memory Suppose that we need to access the first word in page P, please list ALL possible latencies for this access and explain the reason for each case. A: Assuming page P is not in memory. The process will be along the lines of the following. There will be 0 seconds to access TLB cache for the entry for page P. This will result in a miss so the page table for this process will be accessed. Assume the page table is in memory. Itll take 0.1 ns to access the page table and get the entry. Since page P is not in memory, the entry will be invalid. Itll take 1 ms to get the page from disk into memory. Then another 0.1 ns to get page P from memory. So in total, itll take 1000000.2 ns. 2. Consider a demand-paging system with the following time-measured utilizations: CPU utilization: 20% Paging disk: 97.7% (demand, not storage) Other I/O devices: 5% For each of the following, say whether it will (or is likely to) improve CPU utilization. Briefly explain your answers. a. Install a faster CPU A: This will likely have no effect. The limiting factor is available memory per program. b. Install a bigger paging disk A: This should have no affect really. c. Increase the degree of multiprogramming A: This typically decreases CPU utilization because less memory is available to each program and the chances of page faults increase. d. Decrease the degree of multiprogramming A: This typically increases CPU utilization by keeping more of the working set of each program in memory, thereby reducing the number of page faults. e. Install more main memory A: This is increase CPU utilization as there will be less paging taking CPU time to service. f. Install a faster hard disk, or multiple controllers with multiple hard disks

A: This will decrease the time spent waiting for pages to be brought in so itll increase responsiveness of the system, but since the CPU context switches to other programs anyway, this might not increase CPU utilization that much, if at all. Its possible that the faster page retrieval limits the number of context switches but, thrashing will still be occuring. g. Add prepaging to the page-fetch algorithms A: This is increase CPU utilization by avoiding page faults by having the pages pulled into memory before theyre needed. h. Increase the page size A: This will increase CPU utilization because spatial locality will reduce the number of page faults. This comes at the cost of more internal fragmentation. If taken too far, can reduce the number of programs that can have a working set in memory. 3. If a large number of programs is kept in main memory, then there is almost always another ready program when a page fault occurs. Thus, CPU utilization is kept high. If, however, we allocate a large memory space to each of a few programs, then each program produces a smaller number of page faults. Thus, CPU utilization is kept high. Are these two arguments correct? Which policy, if either, should be preferred? Why? A: If a large number of programs are kept in memory, then a page fault will result in a context switch to one of the other programs, true. However, theres overhead in the context switch and it is more than likely that the program switch to will cause a page fault of its own due to the limited memory. So CPU utilization is probably not going to be high. The CPU will spend most of its time context switching and servicing page faults. If a few programs are given a lot of memory then each program will probably have fewer faults (depends on the working set size and the amount of memory allocated to each program). But CPU utilization is not solely dependent on page fault rate. The behavior of the programs may produce poor CPU utilization if they are I/O bound. Generally however, having a few programs in memory will reduce the number of page faults and generally have higher CPU utilization. 4. Suppose we have a computer system with a 44-bit virtual address, page size of 64K, and 4 bytes per page table entry. 0. How many pages are in the virtual address space? A: 44 bit addr - 16 bits for offset = 28 bits = 228 = 256M pages 1. Suppose we use two-level paging and arrange for all page tables to fit into a single page frame. How will the bits of the address be divided up? A: 64K bytes per frame / 4 byte per PTE = 16K PTE per frame = 214 = 14 bits needed for second level page table. Since we still need 16 bits for offset, address is: 14 bits for top level page table entries, 14 bits for second level page table entries, 16 bits for offset. 2. Suppose we have a 4 GB program such that the entire program and all necessary page tables (using two-level pages from above) are in memory. (Note: It will be a lot of memory.) How much memory, in page frames, is used by the program, including its page tables? A: 4 GB of pages is 232/216 = 216 level two page table entries. Since each level two page

table holds at most 214 entries, well need 216/214 = 22 = 4 level two page tables to hold all the pages for the program. Additionally, well need 1 level one page table to point to the 4 level two page tables. So well need 5 page tables in memory, in total. Total sum is 216 page frames + 5. 5. If FIFO page replacement is used with a memory that only has four page frames, and there are only eight pages in the system (0-7), how many page faults will occur with the reference string 0172327103 if the four frames are initially empty? Now repeat this problem for LRU. A: For FIFO, 4 to fill, one for 3, one for 0 = total of 6. For LRU, 4 to fill, one for 3, one for 0, one for 3 = total of 7 [email protected]!

You might also like