4a - SDH Mapping
4a - SDH Mapping
Objectives
Standards Frame Structure Multiplexing Regenerator Section Overhead Mutiplexing Section Overhead Path Overhead Advantages
PDH
Notation E0 E1 E2 E3 E4 Data Rate 64 Kbps 2048 Kbps 8448 Kbps 34368 Kbps 139264 Kbps Notation T0/DS0 T1/DS1 T2/DS2 T3/DS3 T4/DS4 Data Rate 64 Kbps 1544 Kbps 6312 Kbps 44736 Kbps 139264 Kbps
SDH Standards
Optical Signal STM-0 STM-1 STM- 4 STM-16 STM-64 STM-256 Bit Rate 51.84 Mbps 155.52 Mbps 622.080 Mbps 2488.320 Mbps 9953.280 Mbps 39813.12 Mbps Abbreviated as 51 Mbps 155 Mbps 622 Mbps 2.4 Gbps 10 Gbps 40 Gbps
Tx End
Rx End
Administrative Unit
Capacity of the Virtual Container + Pointers 9 Rows
Pointers 4
5 6 7 8 9
H1H1 H1 H2 H2 H2 H3 H3H3
RSOH
AU Pointer
PAY LOAD
5-9 rows
MSOH
9 Columns
STM-N is got by Byte Interleaved Multiplexing of Lower Order Frame. For Example STM-4 is got by Multiplexing 4 STM-1 Frames.
SDH
M U X Line Signal
STM -4 STM-3
Mapping in SDH
Multiplexing Elements
container POH PTR virtual container tributary unit tributary unit group PTR SOH administration unit C-n VC-n TU-n TUG-2 AU-n STM-1 STM-n N=4,16 n=3,4 n=1,2,3,4 m=1,2 n=3,4 n=1,2,3,4 bitrates G.702 C1, C2 C3, C4 VC-n TU-1, -2 VC-n AU-n, n=3,4 AU-n, n=3,4 Payload
Abbreviation
32 Bytes
Stuffing Bytes
C-12
1 23
32
34 Bytes
VC-12
1 23
32
35 Bytes
R: D:
Fixed Stuff Bits Data-Bits (of 2Mb/s Tributary-Signal) Overhead-Bits (For future use) Justification Indication-Bits - C1 = 0 -> S1 = Data-Bit - C1 = 1 -> S1 = Stuff-Bit - C2 = 0 -> S2 = Data-Bit - C2 = 1 -> S2 = Stuff-Bit Actual Justification-Bits -Justification is indicated by C1, C2 (Majority-Vote out of 3)
Block 1
O: C1, C2:
Block 2
S1, S2:
Block 3
Justification Capacity +/- 1 Bit every 500 ms -> +/- 2000 Bits (~+/- 1000 ppm) Speed of C-12 136 Byte x 8 Bit / 500 ms = 2.176 MBit/s
Block 4
TUG-3
TUG-2
TU-12
VC-12
C-12
2Mbit/s
Basic unit for tributary signals of the PDH Synchronous to the STM-1 signal Adaptation of bitrates through positive stuffing in case of plesiochronous tributary signals Adaptation of synchronous tributaries through fixed stuffing bits Bit stuffing mechanism
10
#1 #2
1 Byte V5
BIP-2
BIP-2: REI:
REI
RFI
Signal Label
RDI
RFI: Remote Failure Indication Signal Label: Specifies the content of the VC
J2
RDI:
Path Trace J2
#70 #71 #72 J2: Repetitively transmitted 16-Byte Frame containing a Path Access Point Identifier
N2
K4: APS-Channel: Automatic Protection Switching Signaling #140 Spare: For Future use
STM-N
TU-12
VC-12
C-12
2Mbit/s
11
Creation through addition of the POH Is transported through the network as one unit If the VC contains several VCs, it will have a pointer area Multi container payload through concatenation
1 4 VC-12
12
TU-12
36 Bytes
9 Rows
4 Columns
N N N N S S P P V1 (TU-Pointer #1) Cell #105 Cells #106 #138 Cell #139 V2 (TU-Pointer #2) Cell #0 V1+V2
P P P P P P P P
N: New Data Flag (NDF) - Flag NOT active -> NNNN = 0110 - Flag active -> NNNN = 1001 (Inverted) S: Size Indication - For TU-12 SS=10 P: 10-Bit Pointer Value - Range for TU-12 is 0.139 - Points to that Cell, Where the VC-12 starts (Location of V5)
Cells #1 #33 Cell #34 V3 (TU-Pointer #3) Cell #35 Cells #36 #68 V3 Cell #69 V4 (TU-Pointer #4) Cell #70 Cells #71 #103 Cell #104
Used for justification - Incase of Negative Pointer Justification, this Byte is used as Auxiliary-Cell V4 Reserved (For future Use)
STM-N
AUG
AU-4
VC-4
TUG-3
TUG-2
TU-12
VC-12
C-12
2Mbit/s
13
Important Facts: V1 The TU-12 must be locked to the HigherOrder VC (VC-3 or VC-4) The 10-Bit TU-Pointer points to that cell, where the V5-Byte Of the VC-12 is located (Start of VC-12) The VC-12 can float within the TU-12 since both may have Different Clock rates If the incoming VC-12 is too fast, the excess data is carried By V3. The V5-Byte moves 1 cell up in the TU-12 and the pointer value decrements by 1 -> Negative Pointer Justification If the incoming VC-12 is too slow, the byte immediately after V3 (Cell #35) is used as Stuff-Byte to stuff the excess transport capacity of the TU-12. The V5-byte moves 1 cell down in the TU-12 and the pointer value increments by 1. -> Positive Pointer Justification
35 Byte
V2
VC-12
35 Byte
V3
35 Byte
35 Byte
V4
14
V1 Cell #105
V2 D I D I D I D
Negative Justification Opportunity (Used to carry Data) Positive Justification Opportunity (Used as Stuff-Byte)
Inverted value of all D-Bits (Decrease) Indicates Negative Justification Inverted value of all I-Bits (Increase) Indicates Positive Justification
Under normal conditions the pointer is justified by 1 (Increase or Decrease as soon as the phase different between the VC-12 and TU-12 exceeds 8 Bits (1Byte). This is Indicated by inverting either the I or the D Bits of the 10-Bit Pointer (Majority vote out of 5). If a random change of the pointer value becomes necessary, this is indicated by activating (inverting) the new Data Flag.
Cell #104
15
Creation through addition of a pointer to the VC Slip free transmission of a VC also in case of plesiochronous behaviour of the network element The TU definition refers to the VC, the AU to STM-1 Identical to AU
1
Pointer TU-12
9
V5
VC-12 POH
16
TU-12
TU-12
TU-12
9 Rows
4 Columns Multiplexing
4 Columns
4 Columns
TUG-2
9 Rows
12 Columns
V1, 1 #105, 1
V1, 2 #105, 2
V1, 3 #105, 3
Column
1
V1,1
2
V1,2
3
V1,3
10
11
12
TUG-2 multiframe
V3,1 V3,2 V3,3 #35,1 #35,2 #35,3
#104, 1
#104, 2
#104, 3
TU-12 #1
TU-12 #2
TU-12 #3
STM-N
AUG
AU-4
VC-4
TUG-3
TUG-2
TU-12
VC-12
C-12
2Mbit/s
125 ms
125 ms
125 ms
125 ms
17
Stuffing Bytes
X 7 TUG-2
TUG-3(multiplexing)
TUG 3
84 Columns 86 Columns
18
TUG-2 #1
Column 1 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9
TUG-2 #2
10 11 12 Column 1 2 3 12 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9
TUG-2 #3
Column 1 2 3 12 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9
TUG-2 #7
Column 1 2 3 12
NPI
Bit Row 1 Row 2 Row 3 1--------------------------8 1 0 0 1 X X 1 1 1 1 1 0 0 0 0 0 X X X X X X X X
Column 1 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
17 18 19
20 21 22 76 23 77 24 78 79 80 81 82
83 84 85 86
STM-N
TUG-3 STUFF
TUG-3
AUG
AU-4
VC-4
TUG-3
TUG-2
TU-12
VC-12
C-12
2Mbit/s
19
VC - 4
X 3 TUG3
TUG-3 #1
Column 1 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9 2 3 4 5 6 84 85 86 Column 1 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9 2 3
TUG-3 #2
4 5 6 84 85 86 Column 1 Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9 2 3
TUG-3 #3
4 5 6 84 85 86
NPI
NPI
TUG-3 # 2 STUFF
TUG-3 # 2 STUFF
Column Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9
3 4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 251 252 253 254 255 256 257 258 259 260 261
NPI #2
NPI #1
NPI #3
TUG-3 # 1 STUFF
TUG-3 # 2 STUFF
TUG-3 # 3 STUFF
TUG-3 # 1 STUFF
TUG-3 # 2 STUFF
TUG-3 # 3 STUFF
VC-4 Path OH
VC-4 Stuff
VC-4 Stuff
TUG-3 # 2 STUFF
TUG-3 # 2 STUFF
VC-4
STM-N
AUG
AU-4
VC-4
TUG-3
TUG-2
TU-12
VC-12
TUG-3 # 2 STUFF
C-12
2Mbit/s
20
21
Pay Load
AU Pointer 4 th Row
Pay Load
9 Columns
261 Columns
264
265
266
267
268
269
Column 1 2 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9
H1
9 10 11 12 13 14 15 16 17
#522 #609 #523 #610 #697 #1 #88 #175 #262 #349 #436 #524 #611 #698 #2 #89 #176 #263 #350 #437
AU-4 Pointer
Y Y H2 1* 1* H3 H3
AU-4 Payload
N N N N S S P P
H1+H2
P P P P P P P P
Y-Bytes: Stuff Byte (Value=93 hex) -Used as H1 in AU-3 Pointer Stuff Byte (Value=FF hex) -Used as H2 in AU-3 Pointer Used for justification - Incase of Negative pointer justification, these bytes are used as Auxiliary-Cells
N: New Data Flag (NDF) -Flag NOT active -> NNNN = 0110 -Flag active -> NNNN = 1001 (Inverted) S: Size Indication -Not Specified on AU-4 Level (Dont care
1*-Bytes:
Bits) P: 10-Bit Pointer Value -Range for TU-12 is 0.728 -Points to that Cell, Where the VC-4 starts
STM-N AUG AU-4 VC-4
TUG-3 TUG-2
H3-Bytes:
TU-12
VC-12
C-12
270
2Mbit/s
22
Column 1 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9
10 11 12 13 14 15 16
17
H1 Y
H2
1*
1* H3
H3
H3
H1 0 1 1 0 1 0
New Data Flag Size
I D
H2 D I D I D
I D
Inverted value of all D-Bits (Decrease) Indicates Negative Justification Inverted value of all I-Bits (Increase) Indicates Positive Justification
Under normal conditions the pointer is justified by 1 (Increase or Decrease) as soon as The phase different between the VC-4 and AU-4 exceeds (3 Byte). This is Indicated by inverting either the I- or the D-Bits of the 10-Bit Pointer (Majority vote out of 5) If a random change of the pointer value becomes necessary, this is indicated by activating (inverting the new Data Flag
23
AU-Pointer(s) Payload
TU-12
VC-12
C-12
269
270
2Mbit/s
24
9 Byte
261 Bytes
9 Bytes
STM-1
SOH AU
ADMINISTRATIV E UNIT (AU) POINTERS
POH
HIGHER LEVEL VC
B a
C b c
TU
VC
PLESIOCHRONOU S STREAM
25
15 16 R R R R R R R R R
17 18 19 R R R C C S
20
R R R
R R R
R R R
R R R
R R R
R R R
R R R
R R R
C C C
R R R
R R R
R R R
R R R
R R R
R R
4 Bytes
1 Byte 84 Bytes
Byte 1
R-Block
Byte 2
DDD...
Byte 3
24 x D
RRRRRRRR
C-Block
R R R R R R C1C2
DDD...
24 x D
...DDD
R: Fixed Stuff Bits O: Overhead-Bits (For future use) C1, C2: Justification Indication-Bits Cx = 0 -> Sx = Data-Bit Cx = 1 -> Sx = Stuff-Bit S1, S2: Actual Justification-Bits Justification is indicated by C1, C2-Bits (Majority-Vote out of 5)
S-Block
RRRRRRRR
R R R R R R R S1
S2 D D D D D D D
DDDDDDDD
-Block
RRRRRRRR
C3
TU-3
VC-3
83
C-3
85
34M
26
Tributary Unit
82 83 84 85
Column Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 1 H1 H2 H3 2 3 4 5 6 7 8 9
Fixed Stuff
TU-3 Payload
TU-3 Pointer
N N N N S S P P H1+H2
P P P P P P P P
N: New Data Flag (NDF) -Flag NOT active -> NNNN = 0110 -Flag active -> NNNN = 1001 (Inverted)
H3-Bytes: Used for justification - Incase of Negative pointer S: Size Indication justification, these bytes -Not Specified on TU-3 Level (Dont care Bits) are used as Auxiliary-Cell. P: 10-Bit Pointer Value -Range for TU-3 is 0.764 -Points to that Cell, Where the VC-3 starts (Location of J1)
Fixed Stuff
0 1
H1 1 0 1
Size
Under normal conditions the pointer is justified by 1 (Increase or Decreases soon as The phase different between the VC-3 and TU-3 exceeds 1Byte. This is Indicated by inverting either the I- or the D-Bits of the 10-Bit Pointer (Majority vote out of 5) If a random change of the pointer value Inverted value of all D-Bits (Decrease) becomes necessary, this is indicated by Indicates Negative Justification activating (inverting the new Data Flag Inverted value of all I-Bits (Increase) Indicates Positive Justification
H2 D I D
STM-N
AUG
AU-4
VC-4
TUG-3
TU-3
VC-3
C-3
85
34M
86
86
27
TU-Pointer
Row 4
TUG-3 Payload
TU-3
VC-3
84
85
C-3
86
34M
TUG-3 #2
84 85 86 Column Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9 1
H1 H2 H3
TUG-3 #3
84 85 86 Column Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9 1
H1 H2 H3
84 85 86
H3
TUG-3 # 2 STUFF
TUG-3 # 2 STUFF
TUG-3 # 2 STUFF
TUG-3 # 2 STUFF
Column Row Row Row Row Row Row Row Row Row 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
17 18 19
20 21 22 23 24251 252 253 254 255 256 257 258 259 260 261
VC-4 Path OH
VC-4 Stuff
H1 H1 H1 H2 H2 H2 H3 H3 H3
VC-4 Stuff
STM-N
TUG-3 # 1 STUFF
AUG
TUG-3 # 2 STUFF
TUG-3 # 3 STUFF
VC-4
AU-4
VC-4
TUG-3
TU-3
VC-3
TUG-3 # 2 STUFF
TUG-3 # 2 STUFF
C-3
34M
28
1 x 140 Mbps PDH Signal 3 x 34 Mbps PDH Signals 63 x 2 Mbps PDH Signals Combinations, eg. 21 x 2 Mbit/s and 2 x 34 Mbit/s PDH Signals ATM cells, FDDI, DQDB Protocols, etc.
29