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VHDL For Wave Generation

This document contains VHDL code for generating different types of waves including square, triangular, sawtooth, and sine waves. The code defines entities and architectures to generate each wave type using a clock input and output the wave as an integer. It also contains a testbench entity that instantiates the wave generators and selects the output of one to pass to the main output based on a selection input.

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Denise Nelson
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149 views

VHDL For Wave Generation

This document contains VHDL code for generating different types of waves including square, triangular, sawtooth, and sine waves. The code defines entities and architectures to generate each wave type using a clock input and output the wave as an integer. It also contains a testbench entity that instantiates the wave generators and selects the output of one to pass to the main output based on a selection input.

Uploaded by

Denise Nelson
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as EHTML, PDF, TXT or read online on Scribd
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VHDL CODE: ---------------------------------------------------- square wave------------------------------------library ieee; use ieee.std_logic_1164.

all;

entity sqwav is port(clk:in std_logic; n :in integer; op:out integer); end sqwav;

architecture sqwav_arch of sqwav is begin process(clk) variable count:integer:=0; variable s:integer:=127; begin if (clk = '1' and clk'EVENT) then count := count + 1; end if; if(count>=n/2 and count<n) then s:= 0; elsif (count>=n) then count:=0; s:=127; end if; op<=s; end process;

end sqwav_arch; ---------------------------------------------------------------- Triangular wave-----------------------------------------

library ieee; use ieee.std_logic_1164.all;

entity triwav is port(clk:in std_logic; n :in integer; op:out integer); end triwav;

architecture triwav_arch of triwav is begin process(clk) variable count:integer:=0; variable s:std_logic:='0'; begin if (clk = '1' and clk'EVENT) then count := count + 1; end if; if(count>=n/2) then count:=0; s := NOT s; end if; if(s='0') then op <= count*255/n; else op <= 127-count*255/n; end if; end process; end triwav_arch;

--------------------------------------------------- sawtooth wave library ieee;

use ieee.std_logic_1164.all;

entity sawtoothwav is port(clk:in std_logic; n :in integer; op:out integer); end sawtoothwav;

architecture sawtoothwav_arch of sawtoothwav is begin process(clk) variable count:integer:=0; variable s:integer:=10; begin if (clk = '1' and clk'EVENT) then count := count + 1; end if; if(count>=n) then count:=0; end if; op<= count*127/n; end process;

end sawtoothwav_arch; ---------------------------------------------------------- sine wave library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sine_package.all;

entity sine_wave is port( clock, reset, enable: in std_logic;

wave_out: out sine_vector_type); end;

architecture arch1 of sine_wave is type state_type is ( counting_up, change_down, counting_down, change_up ); signal state, next_state: state_type; signal table_index: table_index_type; signal positive_cycle: boolean; begin

process( clock, reset ) begin if reset = '1' then state <= counting_up; elsif rising_edge( clock ) then if enable = '1' then state <= next_state; end if; end if; end process;

process( state, table_index ) begin next_state <= state; case state is when counting_up => if table_index = max_table_index then next_state <= change_down; end if; when change_down =>

next_state <= counting_down; when counting_down => if table_index = 0 then next_state <= change_up; end if; when others => -- change_up next_state <= counting_up; end case; end process;

process( clock, reset ) begin if reset = '1' then table_index <= 0; positive_cycle <= true; elsif rising_edge( clock ) then if enable = '1' then case next_state is when counting_up => table_index <= table_index + 1; when counting_down => table_index <= table_index - 1; when change_up => positive_cycle <= not positive_cycle; when others => -- nothing to do end case; end if; end if; end process;

process( table_index, positive_cycle ) variable table_value: table_value_type; begin table_value := get_table_value( table_index ); if positive_cycle then wave_out <= std_logic_vector(to_signed(table_value,sine_vector_type'length)); else wave_out <= std_logic_vector(to_signed(-table_value,sine_vector_type'length)); end if; end process; end; --------------------------------------------------------- total project entity

library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Std_logic_unsigned.all; use IEEE.Std_logic_arith.all; use IEEE.Numeric_Std.all; use IEEE.Std_logic_unsigned.all; use work.sine_package.all;

entity final_tb is port( clk:in std_logic; select_lines: in std_logic_vector(2 downto 0); hi: out sine_vector_type); end;

architecture bench of final_tb is component sine_wave port( clock, reset, enable: in std_logic;

wave_out: out sine_vector_type); end component; component sqwav is port(clk:in std_logic; n :in integer; op:out integer); end component; component triwav is port(clk:in std_logic; n :in integer; op:out integer); end component; component sawtoothwav is port(clk:in std_logic; n :in integer; op:out integer); end component;

signal clock, reset, enable: std_logic:='0'; signal wave_out: sine_vector_type; signal op,sqr_out,tri_out,saw_out,sin_out: integer; constant clock_period: time := 37 ns; signal stop_the_clock: boolean; signal n: integer:=1;

begin n<=512; enable <= '1'; sin_block: sine_wave port map ( clock, reset, enable, wave_out ); sqr_block: sqwav port map ( clock, n, sqr_out ); tri_block: triwav port map (clock, n, tri_out ); saw_block: sawtoothwav port map(clock, n, saw_out);

sin_out<=conv_integer((wave_out)); hi <= conv_std_logic_vector(op,8);

choice: process(select_lines,clock) begin if(select_lines="000") then op <= sqr_out; elsif select_lines="001" then op <= saw_out; elsif select_lines="010" then op <= tri_out;

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