DESIGN Of LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER

lackuline Moni D, Anu Priyadharsini K

Associate Professor, ECE dept. Karunya University PG Student, ECE dept. Karunya University
Decision Diagrams and the other is a library based design. Various type of full adder has been investigated in [67].Various technique of multiplier has been investigated in [8-12].
II. Analysis of adders

Abstract-A

One-bit

adder

is

designed

using

modified

complementary pass transistor logic (MCPL). The proposed adder is implemented in 4x4 bit high radix multiplier to achieve high speed, low area and less power dissipation. This circuit is simulated by using DSCH2 schematic design tool and layout is taken by Microwind 2 VLSI layout CAD tool, and the analysis is done by using the BSIM4 analyzer. The 4x4 bit high radix multiplier is then compared with Carry Save Array multiplier (CSA multiplier), Baugh-Wooley multiplier, and high radix multiplier to show the better performance in terms of power, area and delay.

One-bit

adder

is

proposed

by

using

the

modified

complementary pass transistor logic. Advantages of using this method are high speed, lower area, low propagation delay. This full adder is then implemented in high radix mUltiplier. It is then compared with the carry save array mUltiplier and Baugh-Wooley multiplier. Simulation results

Keywords-

Radix-4

Multiplier,

Baugh-Wooley

must be

fully based on Complementary Metal Oxide One-bit full adder can be implemented by using

Multiplier, Carry Save array Multiplier.

Semiconductor (CMOS) design rule. the combination of both the multiplexing control input techniques and complementary pass transistor logic. The proposed full adder is shown in the Figure 1.

There are infmite number of ways to perfonn multiplication but still many researchers working in this field, show the importance of mUltiplication. Many multiplier circuit designs have been proposed, which manage to operate at lower propagation delays with lesser power dissipation and a lower power rating of input bits [I].Multiplier is generally used in Digital Signal Processor (DSP) devices. In VLSI design, researchers mainly concentrate on area, speed and power dissipation. High speed multipliers include Braun mUltiplier, Booth mUltiplier, Parallel multiplier and high radix multiplier. [2]. Basic mUltiplication can be realized by the shift add algorithm by generating partial products and adding successive properly shifted partial products. Thus multiplication is proportional to the number of partial products to be added [3]. In all multiplier circuits, two types of adder cells are present. They are half adder and full adder. For the adder to work in high speed, implementing the adder in any one of the high speed techniques is essential. Circuit delay depends on the number of inversion levels. Circuit size depends on the number of transistors in the circuit. Power dissipation depends on the switching activity[4]. Pass transistor can be synthesized by using two methods. One is using Binary Decision Diagrams and the other is a library based design [5 ]. Pass transistor can be synthesized by using two methods. One is using Binary

Figure I: Proposed Full Adder

Complementary Pass transistor Logic (CPL)

partial product. In four bit radix 4 multiplier, 2 partial products will be produced. Partial product is reduced (CPL) to half as compared to the shift and add method.lt is then simulated and then fmally compared with other multipliers. For example consider 1 0 11 x 111 0 . In this , 1 0 1 0is the multiplier value, X . 111 0 is the multiplicand value, a. 2a value is the shift version of a i.e.0 111 0 . 3a is the addition of 1a + 2a i.e. (111 0+0 111 0 = 100 0 1 0 ). is The calculation is as follows.

Complementary

Pass

Transistor

Logic

provides high-speed, full-swing operation and good driving capabilities due to the output static inverters and fast differential stage of cross-coupled PMOS transistors. But due to the presence, of a lot of internal nodes and static inverters, there is a large power dissipation.
Multiplexing Control Input Techniques (MCIT)

The

mUltiplexing

control

input

technique

developed using the kamaugh map which is drawn from the truth table of full adder. According to sum and carry Boolean identities, we can generate the pass-transistor functions. When expression result=l pass transistor function is represented by the input variables and when expression result= 0 pass transistor function is represented by the complement of the input variables. To generate the Pass Transistor Function for 'n' input variable functions, we use 'n-1' as control input data. Simplified sum and carry expression are given as: C=AB+AC+BC S= A'B'C+ A'BC'+ AB'C'+ ABC (2.1) (2.2) 1 1 10 101 1 0 0 0 0 101010 101010 0 0101010
o 1 1 10

(a) Multiplicand value (X) Multiplier value O p( ) initially its equal to zero 2a x l XO(l1) p (O) + 2a Xl XO (J) p shift twice the above value

2a X2 X3 (1 0 )

In CPL techniques, there are many drawbacks. To overcome this, we combine both the CPL techniques and MCIT techniques. Drawbacks occur in CPL due to the body effects, source follower action, low performance and limited fanout.
III.Analysis Of Multipliers A. Radix 4 Multiplier

10 01 1010 0 010 01 1010 2 p( ) shift twice the above value

and high power

leakage. If the CPL is not cross coupled, then it results in

The final product value is p.

The Carry Save Array (CSA) multiplier is a linear array multiplier. The linear multiplier propagates data down through the array cell. Each row of CSAs adds one additional partial-product to the partial sum. As the operand size increases, linear arrays grow at a rate equal to the square of the operand size because the number of rows in the array is equal to the width of multiplicand. The Carry Save Multiplier is shown in the Figure 3.
C. Baugh-Wooley Multiplier:

The MULTIPLEXER is functioned such that the first two bits of the multiplexer, x, will be grabbed to determine the first partial product and shifted to the next 2 bits of the multiplier to determine the successive partial products by repeating the same process. For a 4 bit radix 4 multiplier, two partial products will be generated. As a result, half of the partial product will be reduced compared to other method. The radix-4 multiplier is shown in the figure 2.1t consists of the following:Partial product selector, Partial product pre computation blocks, Half adder, Full adder. In this multiplier, two bits per cycle is considered. Four multiples are precomputed; 1a is the multiplicand value, 2a is the shifted version of a and 3a is the combination of both half adder and full adder. In half adder, CPL technique is applied, and in full adder, the proposed one is implemented. Partial Product Selector is formed by OR and AND gates. All PPS and pre computation block are connected with MUX. The function of the first two bits of the MUX determine the successive

Baugh-Wooley

multiplier

is

an

enhanced

version of the Braun multiplier. It is

designed to allow for

the multiplication of both signed and unsigned operands, which are represented in the 2's complement number systems. The Figure 2: Radix-4 Multiplier Baugh-Wooley proposes a single modification to 2's complement addition to obtain a simple signed multiplier array. It uses inputs A and B which are n bit operands, so their product is a 2n-bit number. Consequently the most significant weight is 2n-1, and the first term is taken in to account by adding a 1 in the most significant cell of the multiplier. The conventional Baugh-Wooley multiplier is shown in figure 4.

i
a:

4 2

cpl _mirror ..... 14t 2 2.5 3 3.5 10t tfa

Q.

VDD (V)

(a)

20
....

CPL _MIRROR ..... 14T 2 2.5 3 3.5 10T TFA

u..

10 c
Q.

Figure 2: Radix-4 Multiplier

VDD (V)

(b)
800 Vi 600
Q.

CPL _MIRROR ..... 14T 10T 2V 2.5V 3V 3.5V TFA _TGA

400 200 o

VDD (V)

(c) Figure. 3: Carry Save Array Multiplier

Figure. 5: (a)power, (b)delay and (c)PDP of various adders Graphs are plotted based on the, comparison of Multiplier with various techniques in terms of power, delay and power delay product is shown in the Figure 6(a),(b),(c).
1.5

a: w

Radix-4 _Baugh ..... CSA 3.5 2.5 1.8 1.2

o
Q.

3: 0.5
o

Figure.4: Baugh-Wooley Multiplier Different adder techniques like CPL, MIRROR, 14T, lOT, TFA , TGA and the proposed adder power, delay and PDP of different values are shown in Figure 5 (a),(b),(c).

VDD (V)

(a)

Compared with other adder, this adder has less power of

1 96mw, delay of 25 2ps and PDP of 4468Fj

80 Vi 60
Q. > 111

References -+-Radix-4

[I]

E Costa, S Bambi, and Jose Monteiro

"A New Architecture fur

40 20 o 3.5 2.5 1.8 1.2 ...... CSA Baugh

[2]

[3]

VDD (V) (b)

[4]

-+-RADIX

[5]

[6]

Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD.02). B Park, M Shin, I C Park, and C M Kyung, "Radix-4 multiplier with regular layout structure," Electronics letter, vol.34, no. 15, pp.1446-7, 1998. Y K Yamanaka, T Nishidha, T Saito, M Shimohigashi, and K Shimizu, A. Hitachi Ltd., Tokyo " A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic," IEEE Journal of Solid-State Circuits, vo1.25, no 2,pp.388-95, 1990. R Zimmermann and W Fichtner, Fellow, IEEELow-Power" Logic Styles: CMOS Versus Pass-Transistor Logic," IEEE Journal Of Solid-State Circuits, vol. 32, no. 7,pp.107990,1997. D Markovic, B Nikolic, and V G Oklobdzija, "A general method in synthesis of pass-transistor circuits," Microelectr. J, vol. 31,pp. 991-8,2000. C H Chang, J Gu, and M Zhang, "A review of O.J8-mm full
adder performances for tree structured arithmetic circuits,"

Multipliers"

[7]

3.5

2.5

1.8

1.2

[8]

VDD (V)

(c) Figure 6 (a)power, (b)Delay and (c)PDP of Radix-4 Multiplier, Baugh Wooley MUltiplier and Carry Save Array Multiplier
IV.Conclusion and Future work

[9]

IEEE Trans. Very Large Scale Integr. (VLSI) Syst. Vol. 13 pp. 686-95, 2005. Massimo Alioto, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE, "Analysis and Comparision on Full Adder Block in Submicron Technology," IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 806-23, 2002. L Sousa and R Chaves, "A universal architecture for designing effiCient modulo 2n+ 1 multipliers," IEEE Trans. Circuits Syst. I:Regular Papers, vol. 52, pp.1166-78, 2005. T Oscal, C Chen, S Wang, and Y W Wu, "Minimization of
switching activities of Partial Products for Designing Low Power Multipliers, "IEEE

The adder cell was designed using a modified CPL technique. The I-bit adder cell was implemented in radix-4, Baugh-Woolley and CSA multipliers. The proposed Radix4 MUltiplier may be used in DSP applications because it gives better performance in terms of power, delay and PDP. The proposed adder based multiplier can be used delay.

Transaction on Very Large Scale Integration (VLSI) Systems,vol. II, no. 3, pp. 418-433,2008. [10] J D Lee, Y J Yooney, K H Leez, and B G Park, "Application of dynamic pass-transistor logic to an 8-bit multiplier," J Kor Phys Soc, vo1.38, pp.220-23, 2001. [II] R Mudassir and Z Abid," New parallel multipliers based on low power adders," 2005 IEEE CCECE/CCGEI, Saskatoon, pp. 694-7,2005. [12] M C Wen, S J Wang, and Y N Lin, " Low-Power parallel multiplier with column bypassing ," lEE Electr Lett, vol. 41, pp. 1-2, 2001.

in high

speed application because of its less power dissipation and