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SCRM Vinitseed, Vsrc2, Vdest, #Offset1 (5 Bit) : Required Functionality

This instruction performs shift register clocking mechanism (SCRM) using vector registers. It takes input shift registers VInitSeeD, mask registers Vsrc2, output register Vdest and offset value. It calculates intermediate bits for I/Q paths, feedback bits, shifts and stores feedback bits in VInitSeeD. The output Vdest is populated with 16-bit complex data generated from shift registers after each iteration.

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68 views

SCRM Vinitseed, Vsrc2, Vdest, #Offset1 (5 Bit) : Required Functionality

This instruction performs shift register clocking mechanism (SCRM) using vector registers. It takes input shift registers VInitSeeD, mask registers Vsrc2, output register Vdest and offset value. It calculates intermediate bits for I/Q paths, feedback bits, shifts and stores feedback bits in VInitSeeD. The output Vdest is populated with 16-bit complex data generated from shift registers after each iteration.

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mkrao_kiran
Copyright
© Attribution Non-Commercial (BY-NC)
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Instruction: SCRM

SCRM VInitSeeD, Vsrc2, Vdest, #offset1(5 bit) Here, VInitSeeD => VInitSeeD[31-0] contains x-shift register bits, VInitSeeD[63-32] contains y-shift register bits Vsrc2 => Vsrc2[127-96] contains 32 bit Mask for feedforward path of x-shift register Vsrc2[95-64] contains 32 bit Mask for feedforward path of y-shift register Vsrc2[63-32] contains 32 bit Mask for feedback path of x-shift register Vsrc2[31-0] contains 32 bit Mask for feedback path of y-shift register Vdest => Vdest[real0[127:112],imag0[111:96],real1[95:80],imag1[79:60],real2[59:48],imag2[47:32],real3[31 :16],imag3[15:0]] contains the result of I and Q path offset1 => This 32 bit immidiate data indicates the position to store the corresponding register's feedback bit. For example, in the above pattern generator the feedback bit position is 17.This gives the 4 output of complex data of each 16bit for real and complex number. VinitSeeD gets updated after the excexution of cycle.

Required Functionality:
Let q1 & q2 be intermediate bits requires for Q-path chip generation, fb1 & fb2 be the feedback bits of shift registers x & y respectively #Note: gated XOR(N1, N2) performs XOR on some of the bits of register N1 as specified by mask register N2. The operation is similar to the scalar instruction XORG q1 =gated XOR(VInitSeeD[31-0],Vsrc2[127-96]); q2 = gated XOR(VInitSeeD[63-32],Vsrc2[95-64]); /* Calculating the chips for Ipath & Q path */ BitRealX = q1 XOR q2; BitImagY = VInitSeeD[0] XOR VInitSeeD[32]; /* Calculating the feedback bit */ fb1 = gated XOR(VInitSeeD[31-0] ,Vsrc2[63-32]); fb2 = gated XOR(VInitSeeD[63-32] , Vsrc2[31-0]); /* Shifting the register to the right by one bit & store the bit at the position indicated by offset1 */ VInitSeeD[31-0] = VInitSeeD[31-0] >> 1; VInitSeeD[63-32] = VInitSeeD[63-32] >> 1;

VInitSeeD[offset1] = fb1; VInitSeeD[offset1+32] = fb2; Vdest(Itr3)[127-112]: Vdest(Itr2)[95-80]: Vdest(Itr1)[63-48]: Vdest(Itr0)[31-16] = BitRealX*0x7fff Vdest(Itr3)[111-96]: Vdest(Itr2)[79-64]: Vdest(Itr1)[47-32]: Vdest(Itr0)[15-0] = BitRealY*0x7fff For the given diagram, Vsrc2 => Vsrc2[127-96] = 0x00001050 --> 32 bit Mask for feedforward path of x-shift register Vsrc2[95-64] = 0x0000ff60 --> 32 bit Mask for feedforward path of y-shift register Vsrc2[63-32] = 0x00020081 --> 32 bit Mask for feedback path of x-shift register Vsrc2[31-0] = 0x000204a1 --> 32 bit Mask for feedback path of y-shift register VInitSeeD : VInitSeed is loaded with Initial Seed and is updated at the end of each operation Vdest is updated after each iteration with 16bits complex data

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