920

IEEE J O U R N A L OF SOLID-STATE CIRCUITS, VOL.

25, NO. 4, ALJGUST1990

An Analytical Maximum Toggle Frequency Expression and its Application to Optimizing High-speed ECL Frequency Dividers

Abstruct -A novel method has been used to analyze static and regenerative frequency dividers by relating their performance to that of the gates. It has been found that the behavconstituent EXCLUSIVE-OR (XOR) ior of the propagation delay of XOR gates is quite linear and this has allowed the derivation of a propagation delay expression for XOR gates using a sensitivity analysis. The validity of the expression has been carefully checked by comparison with SPICE simulations and with reported results in the literature, and agreement to 10% has been obtained. In order to optimize frequency dividers, figures of merit for frequency dividers realized in silicon and AIGaAs/GaAs technologies are proand hence posed. Expressions for optimum load resistance R,,,,,, optimum collector current density J,, are then derived from these figure-of-merit expressions. By comparing the optimum collector current densities with the current densities at which the maximum f T occurs, it is found that improved performance can be obtained for silicon technology by designing transistors in which the maximum f T occurs at a higher collector current density. For AIGaAs/GaAs technology, im, and RE. proved performance requires general reductions in T ~ R,, This conclusion is consistent with results obtained on ECL and CML ring oscillators Ul, thereby demonstrating that the use of a ring oscillator to optimize the fabrication process and transistor design should automatically lead to an optimum value for the maximum toggle frequency of a frequency divider.

20

15 -

10 -

5-

o t f
0
5 10 15 20 Reported Maximum Toggle Frequency (GHz) 25

Fig. 1. Comparison between predicted and reported maximum toggle frequency of frequency dividers.

NOMENCLATURE Propagation delay of logic circuit. Transistor forward transit time. Transistor cutoff frequency. Maximum toggle frequency of frequency divider. Transistor base parasitic series resistance. Transistor collector parasitic series resistance. Transistor emitter parasitic series resistance. Load resistance of logic gate. Optimized load resistance of logic gate. Intrinsic base-collector junction capacitance. Extrinsic base-collector junction capacitance.
Manuscript received November 28, 1989; revised March 5 , 1990. The authors are with the Department of Electronics and Computet Science, University of Southampton, Southampton SO9 5NH, England IEEE Log Number 9036474.

C,, C,, C,, C, C,

Total base-collector junction capacitance. Base-emitter junction depletion capacitance. Collector-substrate junction capacitance. Base-emitter junction diffusion capacitance. Estimated metal track loading capacitance.

I. INTRODUCTION
ITH advances in gigabit-per-second communication systems, the need for very high-speed frequency dividers has become more important. Static and regenerative frequency dividers can operate up to 15 121 and 18.0 GHz [3], respectively, utilizing silicon bipolar technology. For AIGaAs/GaAs heterojunction bipolar transistor (HBT) static frequency dividers, an even higher frequency of 22.15 GHz [4] has been reported in the literature. The maximum toggle frequency of a frequency divider is commonly used as a benchmark to assess the performance of a technology for digital circuits. In order to predict the maximum toggle frequency and optimize the circuit of the frequency divider, it is desirable to have an expression which relates the maximum

0018-9200/90/0800-0920$01.00 01990 IEEE

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FANG

et al. : ANALYTICAL

M A X I M U M TOGGLE FREQUENCY EXPRESSION

921

* -

T-F.F. Circuit

Buffer Circuit

Fig. 2. Circuit diagram of static frequency divider.

toggle frequency to the electrical parameters of the divider. However, up to now, no such expression has been available in the literature. The objective of this work is to derive a maximum toggle frequency expression for frequency dividers that relates circuit electrical parameters to the maximum toggle frequency. The predicted results using the expression agree very well with the reported data in the literature as shown in Fig. 1.

lin&ut

fin-lout
Low Pass Finer

lout

lout

Fig. 3 . Principle of regenerative frequency divider

11. DERIVATION OF MAXIMUM TOGGLE FREQUENCY EXPRESSIONS

According to previous results published in 111, a sensitivity analysis can be used to generate accurate propagation delay expressions for bipolar circuits. Therefore, the sensitivity analysis is used here to derive the maximum toggle frequency expressions for bipolar frequency dividers.

A. Types of Frequency Dicider Investigated

There are two categories of frequency divider which have been described in the literature. One is a static frequency divider (SFD) [5] and the other is a regenerative frequency divider (RFD) [31. Both types will be included in the following discussion since each of them has some advantages over the other. The typical circuit of a divide-by-two static frequency divider is shown in Fig. 2 [5]. The circuit design is based on the well-known T-connected master-slave D-type flip-flop which uses the CML two-level series gating technique. To achieve low power dissipation, two power supply voltages of VEEand V T r have been adopted. It is also reported that all the transistors in the T-type flip-flop are the same and that they operate at the same current

density, i.e., = I,, in Fig. 2. The internal buffers operate as signal amplifiers and level shifters between each T-type flip-flop. The advantage of static frequency dividers is that they can operate from dc to the maximum toggle frequency. Therefore, they are very useful in digital circuit design. However, the static frequency divider contains more transistors and consumes more power than the regenerative frequency divider. Moreover, the maximum toggle frequency of a static frequency divider is lower than that of a regenerative frequency divider. Another very popular circuit for frequency dividers is the regenerative frequency divider which was described by Miller in 1939 [6]. The maximum toggle frequency reported for regenerative frequency dividers in silicon technology is 18.0 GHz [3],which is twice as high as the value of 9.1 GHz reported for a static frequency divider [SI using the same SST technology. The block diagram of a regenerative frequency divider is shown in Fig. 3. The input frequency f is applied to one mixer input, and the output of the mixer is fed back to the other mixer input. The output signal of the mixer contains the frequency f/2 and its harmonics 3 f / 2 , 5 f / 2 , . . . . The high-order harmonic components are filtered out by the low-pass filter and the wanted frequency f / 2 is amplified and is fed back to the mixer. The circuit diagram of the regenerative frequency divider is depicted in Fig. 4 [ 3 ] using a double-balanced modulator. Transistors e,-Q,, act as the modulators

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922

I E F E J O U R N A L OF SOLID-STATE CIRCUITS, VOL.

25, NO. 4, AUGLJST 1990

TABLE I ELECTRICAL PARAMETERS FOR

O.s-/.LmTRANSISTOR

123.0

'JEE

Fig. 4. Circuit diagram of regenerative frequency divider.

active load. The single-ended input frequency is fed to the f,, node and the output frequency can be obtained at the f i n /2 node. The disadvantage of regenerative frequency dividers is that they have a higher minimum toggle frequency f M v l l N because the harmonic 3f/2 may no longer be suppressed if the input frequency f falls below f M A X / 3 . This is a major disadvantage in some applications.

30

2 4 .E
r

20

E
LL

10

B. Choosing the Electrical Parameters The electrical parameters used for deriving the maximum toggle frequency expression of bipolar frequency dividers are based on a 0.5-pm self-aligned transistor and are listed in Table I. The electrical parameters in Table I are the same as those published in [l]with the exception of the wiring capacitance C, which has been increased to take account of the longer interconnections and the higher fan-out in the frequency divider. Second-order effects in the SPICE bipolar junction transistor model have been neglected in order to get a simple and general expression for frequency dividers. The most important of these is the increase in T~ with collector current at very high current density. This mechanism can reasonably be neglected provided the transistors operate below the current density of maximum f7., where T~ is a constant [7], [SI as shown in Fig. 5. This can be justified by noting that the propagation delay of bipolar circuits as a function of collector current is very flat at high current density as shown in 111. This implies that any increase in T~ at high current density will increase the propagation delay significantly because r F is a dominant time constant in bipolar logic circuits [l]. Therefore, for optimum speed, the maximum collector current in logic circuits should be designed to be below that of the maximum f r which corresponds to the onset of T~ rise. The output voltage swing of the frequency divider was
0 0.1
Collector Current (mA)
100

Fig. S.

The behavior of a bipolar transistor at high current density as predicted by SPICE.

chosen as 400 mV because of the compromise between the speed and the noise immunity [l]. It should be noted that, for all types of frequency divider, the maximum toggle frequency depends only on the first stage-1/2 frequency divider. It is therefore only necessary to study 1/2 frequency dividers since the results for 1/4 or 1/8 frequency dividers will be the same.

C. Maximum Toggle Frequency Expression

Ideally, to optimize the performance of frequency dividers, one would like to have an expression that relates the maximum toggle frequency to the electrical parameters of the divider: 1 1 fM*X=f(%~,>G)=-+ + . . . . (1) KPF K,R,C,c, However, it is difficult to derive the weighting factors in the above expression since the maximum toggle frequency of a frequency divider is difficult to estimate accurately using SPICE simulations.

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FANG

et al.: ANALYTICAL MAXIMUM TOGGLE

FREQUENCY EXPRESSION

923

Q7

yq
I
1

SFD, which agrees well with the experimental data published in the literature [31, [51.

D. Converting the XOR Gate into an Inuerter

The XOR gate shown in Fig. 6 has two inputs A and B and two outputs S and Since the circuit is fully symmetrical, the propagation delays of the complementary outputs S and 5 are identical. If we select S as the output to study the propagation delay of the circuit, there are two ways to convert the XOR gate into an inverter: let B = 1 then S = A a n d let A = 1 then S = B.The XOR gate is implemented by stacking CML circuits vertically and simulation shows that the propagation delay through input A is longer than that through input B. According to the operating concept of the frequency dividers, the maximum toggle frequency of a frequency divider is determined by the critical path which is the longest propagation path. Therefore, we let B = 1 and use A as the input node to study the propagation delay of the XOR gate. In Fig. 6, notice that the input voltage of node A requires - 1.8 f0.2 V, while the output voltage from the emitter of Q7 is about - 1kO.2 V. In order to form a propagation delay chain, a voltage source is inserted in the emitter follower to shift the output voltage to the required value. In real circuits, the voltage source would be replaced by another emitter follower or a diode.

s.

t
XOR

Fig. 6. Equivalent

gate for frequency dividers.

In order to overcome this problem, a novel method for deriving the maximum toggle frequency expression is proposed as follows. Firstly, all the feedback wires in the frequency divider are cut, thereby converting the sequential frequency divider circuit into a combinational circuit. Secondly, the constituent circuit is configured as an inverter to form an inverter chain, and the propagation delay T~ of the inverter is then derived using a sensitivity analysis. Finally, the maximum toggle frequency of the frequency divider is expressed as
1
fMAX =

KTD

(2)

E. Linearity of the Propagation Delay In order to predict the maximum toggle frequency accurately, we must make sure that the propagation delay of the XOR gate is linear over a reasonable electrical parameter range as represented in (3). Although the linearity of ECL and CML inverters has been confirmed in a previous paper [l], the linearity of the propagation delay of XOR gates is not necessarily the same as ECL and CML inverters. Therefore, a linearity study has been carried out in order to determine the ranges of electrical parameter values over which the weighting factors are valid. The SPICE program has been used to study the linearity of the propagation delay of XOR gates. A plot of the propagation delay of XOR gates as a function of the parasitic capacitances is shown in Fig. 7. This figure is obtained by changing the transistor parameters listed in Table I one by one and plotting the propagation delay as a function of the element values. From the plot shown, it is seen that the behavior of the propagation delay of XOR gates is approximately linear over a reasonable range of electrical parameter values, and so a general-purpose propagation delay expression for XOR gates is achievable. All of the 24 weighting factors for the XOR gate propagation delay expression in (3) have been extracted using a sensitivity analysis [1] and they are listed in Table 11. It is necessary to clarify here that the fan-in of the XOR gate is 2 and the fan-out of the XOR gate is 1 in the derivation of the XOR propagation delay expression. How-

where K is a weighting factor depending on the particular circuit configuration used for the frequency divider. The propagation delay T~ can be expressed as the linear weighted sum of all the time constants of the inverter [l]:
rD = KOlrF

+ RL(

K02CJCl

+ K03CJCX

+ K04C./E + K 0 5 C J S + + RB(
K07CJCI

+ K08CJCX + K09CJE

-k KIOCD

+ KllCJS + K 1 2 C L )

+ R C ( K i 3 C J C I + K,,CJCx + Ki,CJE
+ K 1 6 C D + KllCJS + K 1 8 C L )

+ RE(

K19CJCl

+ K20CJCX + K 2 i C J E

+ K 2 2 C D + K23CJS + K 2 4 C L ) .

(3)

For the static frequency divider shown in Fig. 2, if we cut all the feedback wires in the circuit, the frequency divider is converted into two identical XOR gates as depicted in Fig. 6. Since these two XOR gates are identical, the weighting factor K in (2) for the SFD can be expected to be 2. Similarly, the regenerative frequency divider shown in Fig. 4 is converted into a single XOR gate, and so in this case the weighting factor K in (2) for the RFD can be expected to be unity. This implies that for the same set of transistor parameters the maximum toggle frequency of an RFD will be approximately twice as high as that of an

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924
90 60

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.

25, NO. 4, AUGUST 1990

TABLE I1

DELAY CONSTANTS AND CORRESPONDING WEIGHTING FACTORS

30

I,
0
2
4

1
6 6

Various Capacitances (B)

Fig. 7 . SPICE-simulated propagation delay as a function of various capacitances for an XOR gate with FI = 2, FO = 1.

I 11
RECD RBCL
K13 R&JCI

1 : 5 .

1.56

0.14

0.25
0.07 3.13 3.23

ever, the propagation delay of XOR gates with fan-out greater than 1 can be calculated by adding an equivalent load capacitance to the output of the XOR gate because the base current which is required to drive the second stage is negligibly small compared to the output current of the emitter follower. It should also be noted that the propagation delay expression derived by this method is general, because the propagation delay characteristics of bipolar logic circuits are linear, as demonstrated in Fig. 7. Moreover, because ECL circuit design is quite unique, there is not much room to maneuver after the collector current and output voltage swing are determined. For example, if the voltage supply V,, is increased, the bias voltages of the operating transistors remain the same, and the extra voltage will be dropped across the current source. Therefore, the choice of electrical parameters for the bipolar transistors in the derivation of the propagation delay expression is not important.

1.72 1.62

KM

R&JCX

0.09

111. VERIFICATION In order to validate the maximum toggle frequency expression for the two types of frequency divider, a strict verification procedure is carried out in the following sections.

From the plots shown in Fig. 8, it can be concluded that the weighting factors of the XOR gate propagation delay expression are accurate and the discrepancy between the SPICE simulation and the expression is within 10% for most types of bipolar transistor. For example, a propagation delay of 51.1 ps is obtained from SPICE simulation using the 0.5-pm silicon transistor parameters listed in Table I while the value predicted by the propagation delay expression is 51.0 ps.

A.

EXCLUSIVE-OR

Gate

B. Static Frequency Divider

The motivation of deriving the propagation delay expression for an XOR gate is to predict the maximum toggle frequency of frequency dividers. For example, if the propagation delay of an XOR gate using 0.5-pm self-aligned transistors is 51.0 ps, according to (21, the maximum toggle frequency of the static frequency divider should be around 9.8 GHz. In order to verify this relationship, direct SPICE simulations have been carried out as follows. The circuit diagram of a static frequency divider is shown in Fig. 2. In the following simulations, the singleended sinusoidal input signal was connected to the clock was coninput C and the complementary clock input

Since the maximum toggle frequency of frequency dividers is based on the propagation delay of XOR gates, verification is initially obtained by comparing the results of SPICE simulations with the values predicted by the propagation delay expression. The electrical parameters used for verification are the parameters of the 0.5-pm state-of-the-art silicon transistor listed in Table I. The plot verification method [1] has also been used to provide verification over a wide range of parameter values as shown in Fig. 8. The curves marked as SPICE are SPICE simulation results and the curves marked as TD Equation are the predicted values of the XOR propagation delay expression.

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FANG

et al. : ANALYTICAL MAXIMUM TOGGLE

FREOUENCY E X P R E S S I O N

925

50

1
0

55

Intrinsic Collector Capacitance (F)

Extrinsic Collector Capacitance (fF)

(a)
70

(b)

-1

55

7
0

55

,
0
2
4
6

Emitter Capacitance (fF)

Substrate Capacitance (fF)

(c)
!

'

'

'

'

'

l!

30

3
0
2
Load Capacitance (fF) Forward Transit Time (psec)

(e)

(f)

extrinsic collector Fig. 8. Propagation delay as a function of (a) intrinsic collector capacitance for an XOR gate, (b) XOR gate, (e) load capacitance for an XOR gate, (c) emitter capacitance for an XOR gate, (d) substrate capacitance for an capacitance for an XOR gate, and (f) forward transit time for an XOR gate.

nected to a reference voltage. Since only one flip-flop is necessary for the SPICE simulation, the internal buffer operating as a signal amplifier and a level shifter was omitted and the output frequency was obtained directly from the emitters of Q14 and Q15.The amplitude of the input signal was 400 mV. In order to verify that the static frequency dividers can operate at low frequency, a 1-GHz input frequency was

used initially and satisfactory operation obtained. On increasing the input frequency gradually up to 9.6 GHz, the frequency divider still operated correctly. Fig. 9(a) shows the input and output waveforms of the frequency divider at an input frequency of 9.6 GHz. However, if the input frequency was increased to 9.8 GHz, the frequency divider stopped working properly, as shown in Fig. 9(b). Therefore, the maximum toggle frequency of the 0.5-pm

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926

I E E E JOURNAL OF SOLID-STATE CIRCUITS, VOL.

25, NO. 4, AUGUST 1990

TABLE 111 RECENTLY DEVELOPED ECL STATIC FREQUENCY DIVIDERS

--

Input output

1/8divider 1/8 divider 1/8 divider 1/4divider 1/4divider 1/4divider

s p -

I
-1.9

I I

10.38GHz 9.1GHz

-2.2 -2.2
0

I I I I
100
200

I
I I I

6.0GHz
22.15GHz 2O.lGHz 13.7GHz

I SiliconSST-1A I I Silicon SST I I SiliconHE I I HBTSSBE I I HBTSADLO I I HBTSSBE I

NTT NTI Plessev

NTI
Rockwell
NlT

1 I I I

[111

[5]

1121 141
1131

I I I I

I
I

I
I

1141

300

400

500

600

Time (psec)

(a) -0.7

TABLE IV RFPORTED ELECTRICAL PARAMETFRS FOR STATIC FREOUENCY DIVIDFR~

1'

L m
0

-1

t-

Parameter
SE

Unit
llm2

Si[12] 1x5

HBT[14] 2x5

HBT[13] 2x4

HBT [4] 2x5

-1.3

8 E

2
-1.6

:
-

--

Input output

-1.9

RL

n
f F f F f F

400 3.20 13.8 19.0

270 8.50
0

185 8.00
0

250 8.50
0

cJCI

-2.2
0

C J C X

200

400 Time (psec)

600

800

CJE

15.0

12.0

15.0

(b) Fig. 9. SPICE-simulated input and output waveforms of a static frequency divider at an input frequency of (a) 9.6 GHz and (b) 9.8 GHz.
C'

f F
GHz

60.0

60.0

60.0
20.1 19.6

60.0 22.2 22.6

Reportedf, Predictedf,

6.0 5.7

13.7 14.9

GHz

silicon static frequency divider is 9.7 GHz, which agrees well with the predicted value of 9.8 GHz. Since the maximum toggle frequency of static frequency dividers is widely used as a benchmark for evaluating the speed performance of bipolar technologies, a large number of papers have been published in the literature on static frequency dividers as shown in Table 111. Among these papers, only four of them have published the electrical parameters of the circuits [4], [12]-[14] as listed in Table IV. In the table, r F , R,, and C, are calculated from reported values of f T and I , by approximating r F = 1/2.rrfT,,,,, RL = A v / I 0 , and c, = 27-~/R,. cL is estimated from the wiring capacitance between two consecutive flip-flop stages taking account of the higher fan-out, and is assumed to be 60 f F for all the circuits. C,, is estimated from the reported emitter area and the doping concentration. The substrate capacitance C,, is assumed to be zero in the HBT circuits because they are manufactured on semi-insulating substrates. Since the base contact resistance is dominant in AlGaAs/GaAs HBT technology, all of the collector junction capacitance can be considered to belong to C,,,, and C J C xis approximately zero, as can be seen by referring to the SPICE

model shown in 111. Using this data, the predicted maximum toggle frequency using (2) for the silicon frequency divider is 5.7 GHz, which agrees well with the measured value of 6 GHz [12]. Excellent agreement is also obtained for the three dividers realized in AlGaAs/GaAs technology as listed in Table IV, which indicates that the maximum toggle frequency expression is also valid for HBT technologies. It is interesting to note that although completely different technologies have been used in these static frequency dividers, the discrepancies between experiment and prediction are less than 10%. It seems reasonable to conclude that the maximum toggle frequency expression of frequency dividers is accurate and should be very useful for design, optimization, and performance prediction. C. Regenerative Frequency Dicider The circuit diagram of the regenerative frequency divider is described in Fig. 4. The relationship between input frequency and output voltage swing of the regenerative frequency divider is shown in Fig. 10 using the

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FANG

et al. : ANALYTICAL

M A X I M U M TOGGLE FREQUENCY EXPRESSION

921

400

r n
5
10

simulation program, which is not only tedious but sometimes the program does not converge due to the positive feedback. More importantly the expression can quantify the contribution of each time constant and therefore is very useful in circuit design, performance optimization, and technology assessment.

A. Figure of Merit for AlGaAs / GaAs Diciders

15
Input Frequency (GHz)

20

25

Fig. 10. SPICE-simulated output voltage swing of a regenerative frequency divider as a function of input frequency.

0.5-km transistor parameters listed in Table I. Notice that there is a minimum input frequency for the regenerative frequency divider and the output voltage swing decreases when the input frequency increases. Therefore, there is no obvious boundary which determines the maximum toggle frequency. However, if the output voltage swing is too small, the next stage of the frequency divider will not be able to work properly. If a minimum output voltage swing equal to half of the original is postulated for correct operation of the subsequent stage, a maximum toggle frequency of approximately 20 GHz can be obtained from the plot, which is about twice the value of 9.8 GHz predicted for the static frequency divider. This is consistent with a weighting factor of unity in (2) for regenerative frequency dividers. The above discussion indicates that it is necessary for regenerative frequency dividers to use an amplifier between two stages to amplify the output voltage so that the output voltage swing of the first stage is large enough to drive the next stage. Otherwise, the output voltage swing of regenerative frequency dividers is too small to drive the next stage at high frequencies. At very high frequencies, the output voltage swing of the regenerative frequency divider decreases markedly. Although the output voltage swing can be amplified by a buffer, the maximum toggle frequency of the regenerative frequency divider is limited by the second stage, which is a static frequency divider. Therefore, the maximum toggle frequency of a cascaded regenerative frequency divider is twice as high as that of the static frequency divider of the second stage. Consequently, in the design of regenerative frequency dividers, attention must be paid not only to the regenerative frequency divider of the first stage, but also to the static frequency divider of the second stage.

Although the maximum toggle frequency expression of frequency dividers has been shown to be a general-purpose expression, it can be considerably simplified for particular technology applications. The generality of the full expression can therefore be traded for a short expression which we have called a figure of merit. One of the advantages of the maximum toggle frequency expression is that it allows us to break down the total propagation delay, and the contribution of each time constant to the propagation delay is quantified as shown in Fig. 11. For state-of-the-art HBT transistors, the ten most important time constants of the expression can readily be identified and therefore the figure of merit for HBT static frequency dividers can be expressed as
1
-=

1.927,- R,(2.57CJ, +0.65CJ, +0.28C,)

2fh4AX

+ RR(2.94CJ, + 1.56CJ, + 1.56CL,) + R,(3.86CJ, +3.49CJ, +1.93CD).

(4)

By substituting some HBT electrical parameters into the above equation, one should be convinced that this figure-of-merit expression is also reasonably accurate. For example, for the three HBT electrical parameters listed in Table IV, the maximum toggle frequencies predicted by the figure-of-merit expression are 16.1, 21.6, and 25.3 GHz, respectively, which agree reasonably well with the reported values of 13.7, 20.1, and 22.2 GHz, respectively.

B. Optimization of HBT Frequency Dir'iders

It can be seen from (4) that the maximum toggle frequency expression takes account of the dependence on collector current automatically since the load resistance R,. is an implicit function of the collector current RL = AV/Z,. The choice of R, involves a trade-off between the C, and R , terms because the diffusion capacitance C, is equal to 2r,/R,, and therefore there is an optimum value of R,. By differentiating the right side of (4) with respect to R, and setting it equal to zero, the optimum R, for both static and regenerative frequency dividers can be expressed as 2 ~ 1 .56R, ~ ( RL,,,,
=

IV. APPLICATIONS
One of the advantages of using the maximum toggle frequency expression is to predict the maximum toggle frequency of a frequency divider without running a SPICE

2.57CJ,

+ 1.93RE) + 0.65CJ, + 0.28CL .

(5)

Substituting the electrical parameters of the state-ofthe-art HBT [13] listed in Table IV into ( 5 ) gives R,,,,, = 139 R (hence I,, = 2.9 mA and J , = 3.6 X lo4 A/cm2

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928

IEEE JOURNAL

or

SOLID-STATF CIRCUITS. VOL.

25, NO. 4, AUGUST 1990

li
Q
v c

6 -

Ref. [14] Ref. [13]

5 0
0)

B
2.

4 -

2-

0 L zp

RLCK RLCJE RLCL R&K R K J ERBCDR.&L R E X R E I SR E D R E L R&K R K J ER ~ C D

Fig. 11. Components of propagation delay for AlGaAs/GaAs frequency dividers predicted using the maximum toggle frequency expression.

25

, , , /
--

optimum current

RB=BOohms RB=4Oohms

1,
0.1
1

-1
10

Collector Current (mA)

Fig. 12. Maximum toggle frequency of HBT frequency dividers as a function of transistor collector current predicted by the maximum toggle frequency expression.

dividers are r F , RI.CJC,and R,C,, and therefore further decreases in r F , R,, and the parasitic capacitances are desirable. However, IC designers are fully aware of the effects of T~ and parasitic capacitances and these parameters are usually kept to a minimum. Hence, the only remaining option for optimizing HBT frequency dividers is to decrease the load resistance R,. According to (51, it is very clear that there is little to be gained from decreasing R, further without optimizing HBT technology. In order to decrease the optimum value of R,, further reduction of R , or R , is important. For example, if R, can be reduced from 80 R to 40 R, the maximum toggle frequency can be increased to 23.6 GHz at a collector current of I , = 3.2 mA, which is equivalent to a load resistance of R , = 125 R as shown in Fig. 12. A way of reducing R , and R , without increasing parasitic capacitances is to decrease the contact resistance of the emitter and base as discussed in [11.

for an output voltage swing of 400 mV). This yields f M A X = 22.1 GHz, which is not much of an improvement over the value of f M A X = 21.6 GHz when the reported 10' value of R , = 185 0 ( I , E 2.2 mA and J , = 2 . 7 ~ A/cm2) is used in the figure-of-merit expression (4). It should be noticed that the predicted optimum value of I, E 2.9 mA, which corresponds to a current density of 3.6X lo4 A/cm2, is well below the current density of 6 X lo4 A/cm2 at which the maximum f T occurs [13]. The relationship between the maximum toggle frequency and the collector current, obtained using the maximum toggle frequency expression (2),is shown in Fig. 12. From the plot, it can be seen clearly that there is an optimum value of I , (or an optimum value of R,) at I , E 2.7 mA (hence R , = 148 R ) which agrees well with the value of R , = 139 R predicted by (5). In order to further optimize the circuit, one can use (4) to obtain a breakdown of the delay components and hence identify the most important terms. Fig. 11 shows that the three most important terms for HBT frequency

C. Figure of Merit for Silicon DiLiders

In Table V, the contribution of each time constant to the propagation delay of silicon frequency dividers is quantified. By inspection of the table, the ten most important terms of the expression can be identified and therefore the figure of merit for silicon static frequency dividers can be expressed as
--

- 1.927,

+ R B ( 1.56C,, + 1.56CD)

2 f MAX

+ RL(2.57C,, + 0.65CJ, + 1.32CJ, + O.28CL) + R,(3.23CJ, +O.78CD + 1.56CJ,) (6) where C,,, is the total collector capacitance C,, = cJ,[+
C,,. These have been combined because the weighting factors for C,,, and C,,, associated with the R, and R , terms are nearly the same as shown in Table 11.

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FREOUENC'Y EXPRESSION

929

TABLE V DFIA Y COMPONFNTS FOR SIII C O N TRA~W\ISTORS

Delay component

I Delay forXOR I DelayforECL 1

KIJRLCJS K,RrCr

I
I

15.84 6.72

3.24 3.72

through the use of a smaller R,-.For example, if the maximum f T was obtained at J , = 4X lo4 A/cm2, the load resistance of the frequency divider could be reduced to R , =200 R. This would yield a maximum toggle frequency f M m of 8.5 GHz, which is 1.4 times faster than the value of 6.1 GHz obtained with R , = 400 R. A way of increasing the current density at which the maximum f7. occurs is to design a transistor with a selective ion1 . implanted collector, which has been discussed in [ 1 If increasing the current density for maximum f r and hence the usable operating current density is not possible, we can still decrease the value of R , but keep the same current density in order to prevent the high-current Kirk effect [16]at the expense of a lower output voltage swing and hence a lower noise immunity. It has been reported in [5]that a circuit using an internal voltage swing of 225 mV is capable of operating 1.5 times faster than that using 450 mV. Although the requirements for optimizing HBT or silicon frequency dividers are totally different, the expressions for the optimum load resistance are similar, as can be seen by comparing ( 5 ) with (7). The only differences are that silicon transistors have a higher collector resistance than HBT devices and the substrate capacitance for HBT devices is zero. Therefore, (5) and (7) could be combined as
KL.oPT =

2rF(1.56RB+ 1.93RE +0.78R,) 2.57C,, +0.65C,,

+ 1.32C,,

+0.28CL .

43.49ps

The accuracy of the figure-of-merit expression for silicon frequency dividers can be verified by substituting the silicon electrical parameters listed in Table IV into (6). The maximum toggle frequency predicted by the figureof-merit expression ( 6 ) is 6.1 GHz, which is in excellent agreement with the reported value of 6 GHz [121.

E. Comparison of Time Constants for ECL and

XOR

Gates

ECL ring oscillators are widely used as test vehicles for evaIuating bipolar technology. However, since real circuits are more complex than ECL inverters, the question arises as to how well they reflect the performance of real circuits. In order to answer this question, we have to compare the weighting factors of ECL inverters and the D. Optimization of Silicon Frequency Dividers weighting factors of real circuits. In a similar way to that described for HBT frequency Suppose an ECL ring oscillator was used for evaluating dividers, according to (6), the optimum load resistance the performance of frequency dividers. The weighting R , , , , , for silicon frequency dividers can be derived as factors for ECL inverters and frequency dividers are listed in Table 11. By comparison, it is seen that there is a close correspondence between the relative magnitudes of 2 r F (1.56 R B + 0.78 R,) the weighting factors for frequency dividers and ECL RL,OPT = 2.57C,, +0.65C,, 1.32C,, +0.28C, ' inverters. In order to establish further confidence in the test (7) vehicle of ECL ring oscillators, a comparison of each time For the silicon electrical parameters listed in Table IV, constant is made between a silicon ECL inverter and a the optimum value of load resistance is R,-,,,, = 194 R frequency divider as shown in Table V using the silicon (hence Io=2.1 mA and Jc=4.1X1O4 A/cm2 for an transistor parameters listed in Table IV. It is found that output voltage swing 400 mV), well below the reported the ECL inverter and XOR circuit have the same five most R,C,,, and value of R, = 400 R (hence I , = 1 mA and J , = 2X lo4 important terms, namely r F , R,C,, R,C,,,, A/cm*). This means that if the silicon transistor could be R,C,, indicating that the use of a ring oscillator to designed to operate at a higher current density, an in- optimize the fabrication process and transistor design crease in the maximum toggle frequency could be achieved should automatically lead to an optimum value for the

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930

IEFE J O U R N A I OF SOLID-STATE

CIRCUITS, VOL. 25, NO.4, AUGUST 1990

maximum toggle frequency of a frequency divider. For instance, the predicted optimum load resistance for the silicon ECL inverter is 225 a, which is very close to that of 194 R for the frequency divider.

V.

CONCLUSIONS

A novel method has been used to analyze static and regenerative frequency dividers by relating their performance to that of the constituent EXCLUSIVE-OR gates. It has been found that the behavior of the propagation delay of XOR gates is quite linear and this has allowed the derivation of a propagation delay expression for XOR gates using a sensitivity analysis. The validity of the expression has been carefully checked over a wide range of transistor and circuit parameter values by comparison with SPICE simulations and reported results in the literature. It has been found that this expression can be used to accurately predict the maximum toggle frequency of frequency dividers. Using this expression, it has also been verified that the maximum toggle frequency of regenerative frequency dividers is about twice as high as that of static frequency dividers. Direct SPICE simulations have proved that for regenerative frequency dividers there is a minimum toggle frequency below which circuit operation ceases, and this is about a third of the maximum toggle frequency. In order to optimize frequency dividers, figures of merit have been proposed for silicon and AlGaAs/GaAs HBT dividers. Expressions for optimum load resistance R,,,,, (hence the optimum collector current density J,) have also been derived from these figure-of-merit expressions. By comparing the predicted optimum collector current densities with the current densities of maximum fT, it is found that increasing the current density at which the maximum fT occurs is very important for silicon transistors, while reductions in r F , R,, and R E are desirable for AlGaAs/GaAs transistors in order to reduce R , and therefore increase the maximum toggle frequency of the dividers. This conclusion is consistent with that of ECL and CML circuits [ll and therefore the study shows that the use of a ring oscillator to optimize the fabrication process and transistor design should automatically lead to an optimum value for the maximum toggle frequency of a frequency divider. This approach can also be used for optimizing adder and multiplier circuits because the basic constituent circuit of them is an XOR gate. REFERENCES
[l] W. Fang, Accurate analytical delay expressions for ECL and CML circuits and their applications to optimising high-speed bipolar circuits, IEEE J . Solid-State Circuits, vol. 25, no. 2, pp. 572-583, Apr. 1990. [2] P. Weger, L. Treitinger, J. Bieger, and H.-M. Rein, 15 GHz static frequency-divider IC in silicon bipolar technology, Electron. Lett., vol. 25, pp. 513-514, 1989. [3] H. Ichino et al., Super self-aligned process technology (SST) and its applications, in BCTM Tech. Dig., 1988, pp. 15-18.

[4] Y. Yamauchi et ul., 22 GHz 1/4 frequency divider using AlGaAs/GaAs HBTs, Electron. Lett., vol. 23, pp. 881-882, 1987. [5] M. Suzuki, K. Hagimoto, H. Ichino, and S. Konaka, A 9-GHz frequency divider using Si bipolar super self-aligned process technology, IEEE Electron Decice Lett., vol. EDL-6, pp. 181-183, 1985. [6] R. D. Miller, Fractional-frequency generators utilizing regenerative modulation, Proc. IRE, vol. 37, pp. 446-457, 1939. [71 I. E. Getreu, Modeling the Bipolar Transistor. Amsterdam: Elsevier, 1984. [81 P. Antognetti and G. Massobrio, Semiconductor Delice Modeling with SPICE. New York: McGraw-Hill, 1988. [9] A. Tahara et al., Low-power high-speed ECL circuits with 0.5-fim rules and 30 GHz f T technology, in BCTM Tech. Dig., 1989, pp. 169-171. [IO] M. C. Wilson, P. C. Hunt, and D. J. Bazley, 10.7 GHz frequency divider using double layer silicon bipolar process technology, Electron. Lett., vol. 24, pp. 920-922, 1988. [ l l ] T. Sakai, S. Konaka, Y. Yammamoto, and M. Suzuki, Prospects of SST technology for high speed LSI, in IEDM Tech. Dig., 1985, pp. 18-21. [12] S. Duncan, M. C. Wilson, P. C. Hunt, and D. J. Bazley, A 1-pm trench isolated high speed bipolar transistor, presented at the VLSI Symp., San Diego, CA, 1988. [13] K.,C. Wang, P. M. Asbeck, M. F. Chang, G. J. Sullivan, and D. L. Miller, A 20-GHz frequency divider implemented with heterojunction bipolar transistors, IEEE Electron Dwice Lett., vol. EDL-8, pp. 383-385, 1987. [I41 T . Ishibashi, Y. Yamauchi, 0. Nakajima, K. Nagata, and H. Ito, High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors, IEEE Electron Decice Lett., vol. EDL-8, pp. 194-196, 1987. [15] K. .Nagata et al., Self-aligned AIGaAs/GaAs HBT with low emitter resistance utilizing InGaAs cap layer, IEEE Trans. Electron Deikes, vol. 35, pp. 2-7, 1988. [I61 C. T. Kirk, A theory of transistor cutoff frequency ( f r ) falloff at high current densities, IRE Trans. Electron Der.ices, vol. ED-9, pp. 164-174, 1962.

Wen Fang (S90) was born in Shanghai, Peoples Republic of China, on July 11, 1956. He received the B.S. degree in physics from Fudan University, China, in 1982, and the M.S. degree in electrical engineering from the Shanghai Institute of Metallurgy, the Chinese Acaiemy of Sciences, in 1985 He joined the Institute in 1985 working in the areas of 16-b microprocessor design, four-chip IC development for color TV receivers, three-chip IC testing for B/W TV receivers, and high-speed CMOS static RAM circuit simulation. In October 1987 he received a grant from the Chinese Academy of Sciences. He is currently working towards the Ph.D. degree at Southampton University, Southampton, England, in the field of high-speed bipolar circuits including ECL and CML gate optimization, high-speed frequency divider simulation, and BiCMOS circuit modeling. Mr. Fang is the recipient of the British Overseas Research Student Awards for the session 1989/1990

Arthur Brunnschweiler (M82) was born in Manchester, England, in 1936. He received the B.A. degree from Cambridge University in 1956, the M.S. degree from Pennsylvania State University in 1960, and the Ph.D. degree from the University of Manchester Institute of Science and Technology in 1966. From 1960 to 1964 he was employed in the Camera Tube Research Department of the English Electric Valve Company, Chelmsford, England, and since 1966 he has been on the academic staff of Southampton University, Southampton, England, where he is currently Senior Lecturer in the Department of Electronics and Computer Science. His research and teaching interests include most areas of microelectronics, particularly device and circuit design. He has acted as consultant to several industrial companies and his present duties include the management of the Microelectronics Industrial Unit at Southampton University.

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931 project on electron lithography, and studied the processing problems encountered when the electron image projector was used to fabricate integrated circuits. In 1978 he joined the academic staff of the Electronics Department of Southampton University, Southampton, England. Hi5 present areas of research are the physics of polysilicon emitter bipolar transistors, heterojunction bipolar transistors, and device technology for high-speed bipolar integrated circuits. Dr. Ashburn is a member of the IEE.

Peter Ashburn (M89) was born in Rotherham, England, in 1950 He received the B S degree in electrical and electronic engineering in 1971 and the Ph D degree in 1974, both from the University of Leeds His dissertation topic was an experimental and theoretical study of rddiation damage in silicon p-n junctions In 1974 he joined the technical staff of the Philips Research Laboratories, Redhill, dnd worked on ion-implanted bipolar integrated-circult transistors In 1976 he was transferred to a

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