1
Lecture 25, Slide 1 EECS40, Fall 2003 Prof. King
Lecture #25
Midterm #2 Information
Date: Monday November 3
rd
Topics to be covered:
capacitors and inductors
1
st
-order circuits (transient response)
semiconductor material properties
pn junctions & their applications
MOSFETs; common-source amplifier
Review session: Friday October 31
st
2-4 PM
OUTLINE
The transconductance amplifier
(from Howe & Sodini Chapter 8.1)
Summary of MOSFET
Lecture 25, Slide 2 EECS40, Fall 2003 Prof. King
1. Voltage amplifier
input & output signals are voltages
2. Current amplifier
input and output signals are currents
3. Transconductance amplifier
input signal is voltage;
output signal is current
4. Transresistance amplifier
input signal is current;
output signal is voltage
Amplifier Types
amplifier
+
v
in
+
v
out
amplifier
i
out
i
in
amplifier
i
out
+
v
in
amplifier
i
in
+
v
out
2
Lecture 25, Slide 3 EECS40, Fall 2003 Prof. King
Two-Port Amplifier Model
for a transconductance amplifier
g
m
v
in
R
out
+
v
in
R
in
i
out
Lecture 25, Slide 4 EECS40, Fall 2003 Prof. King
Effect of Source and Load Resistances
Overall transconductance is degraded by the
source resistance R
s
and load resistance R
L
g
m
v
in
R
out
+
v
in
R
L
R
in
+
v
s
|
|
.
|
\
|
+
|
|
.
|
\
|
+
=
out L
out
m
s in
in
s
out
R R
R
g
R R
R
v
i
i
out
R
s
3
Lecture 25, Slide 5 EECS40, Fall 2003 Prof. King
NMOSFET Summary: Current Flow
Gate current i
G
= 0
Body current i
B
= 0
i
S
= i
D
If V
GS
V
T
, i
D
= 0
If V
GS
> V
T
, i
D
> 0
Current is limited by either
the resistance of the
inversion-charge layer, or
velocity saturation
G
S D
p-type Si
n+ poly-Si
NMOSFET Structure
n+ n+
i
G
NMOSFET Circuit Symbol
i
D
i
S
i
B
+
v
G
S
v
DS
+
Lecture 25, Slide 6 EECS40, Fall 2003 Prof. King
When V
GS
V
T
, an n-type channel is not formed.
No electrons flow from SOURCE to DRAIN
CUTOFF mode
When V
GS
> V
T
, an n-type channel (inversion layer of
electrons at the surface of the semiconductor) is formed.
Electrons may flow from SOURCE to DRAIN (i
D
> 0)
If V
DS
< V
GS
V
T
, the inversion layer exists across the
entire channel length, and current i
D
increases with V
DS
LINEAR mode or TRIODE mode
If V
DS
V
GS
V
T
, the inversion layer is pinched off at the
drain end, and current i
D
does not increase with V
DS
SATURATION mode
NMOSFET Summary: Modes of Operation
4
Lecture 25, Slide 7 EECS40, Fall 2003 Prof. King
NMOSFET Summary: I-V Characteristics
v
DS
i
D
0
p
n+ n+
p
n+ n+
p
n+
SATURATION
LINEAR
or
TRIODE
CUTOFF
p
n+ n+
v
GS
= V
G1
> V
T
v
GS
= V
G3
> V
G2
( v
GS
V
T
)
v
GS
= V
G2
> V
G1
v
DS
= v
GS
V
T
V
DSAT
n+
Lecture 25, Slide 8 EECS40, Fall 2003 Prof. King
NMOSFET Summary: I-V Equations
SATURATION LINEAR or TRIODE
DS
DS
T GS n D
V
V
V V
L
W
k I
(
=
2
( )
2
2
T GS
n
DSAT
V V
L
W k
I
=
v
DS
i
D
0
v
GS
> V
T
v
DS
= v
GS
V
T
V
DSAT
5
Lecture 25, Slide 9 EECS40, Fall 2003 Prof. King
PMOSFET I-V Equations
SATURATION LINEAR or TRIODE
DS
DS
Tp GS p D
V
V
V V
L
W
k I
(
=
2
( )
2
2
Tp GS
p
DSAT
V V
L
W
k
I
=
v
DS
i
D
0
|v
GS
| > |V
Tp
|
v
DS
= v
GS
V
T
V
DSAT
Lecture 25, Slide 10 EECS40, Fall 2003 Prof. King
Channel-length modulation:
The length of the pinch-off region, L, increases with
increasing V
DS
above V
GS
V
T
. It reduces the length of
the inversion layer and hence the resistance of this layer.
i
D
increases noticeably with V
DS
, if L is small
NMOSFET Summary: Non-Ideal Behavior
v
DS
i
D
0
cross-sectional
view of channel:
inversion layer
V
DSAT
is the slope
(channel-length
modulation parameter)
6
Lecture 25, Slide 11 EECS40, Fall 2003 Prof. King
Velocity Saturation:
In a very-short-channel MOSFET, i
D
saturates because
the carrier velocity is limited to ~10
7
cm/sec
i
D
reaches a limit before pinch-off occurs
(continued)
< V
GS
V
T
sat
n
DSAT
sat
DSAT
T GS ox DSAT
v
L
V
v
V
V V WC I
=
(
=
where
2
Lecture 25, Slide 12 EECS40, Fall 2003 Prof. King
(continued)
Subthreshold Leakage:
For V
GS
V
T
, i
D
is exponentially dependent on V
GS
:
The leakage current specification sets the lower limit for
the threshold voltage V
T
leakage current, I
OFF
v
GS
log i
DS
0
V
T
1/S is the slope
7
Lecture 25, Slide 13 EECS40, Fall 2003 Prof. King
NMOSFET Summary: Circuit Models
For analog circuit applications (where we are concerned
only with changes in current and voltage signals, rather
than their total values), the small-signal model is used:
( )
D o
T GS n m
I g
V V k
L
W
g
g
m
v
gs
1/g
o
+
v
gs
i
d
S
D
S
G
transconductance
output conductance where V
GS
& I
D
are the
DC bias (Q point) values
Lecture 25, Slide 14 EECS40, Fall 2003 Prof. King
NMOSFET Summary: Circuit Models
For digital circuit applications, the MOSFET is modeled
as a resistive switch:
R
eq
|
.
|
\
|
DD n
DSATn
DD
eq
V
I
V
R
6
5
1
4
3
( )
2
2
Tn DD
n
DSATn
V V
L
W k
I
=
v
DS
i
D
0
V
DD
V
DD
/2
MOSFET is turned on
(V
GS
= V
DD
) when V
DS
= V
DD
As the load capacitor discharges,
V
DS
decreases to 0 V
s
lo
p
e
VD
D
/ I
D
S
A
T
slope V
DD
/ 2 I
DSAT
